tlb.hh revision 11168:f98eb2da15a4
12SN/A/* 28703Sandreas.hansson@arm.com * Copyright (c) 2006 The Regents of The University of Michigan 38703Sandreas.hansson@arm.com * All rights reserved. 48703Sandreas.hansson@arm.com * 58703Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 68703Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 78703Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 88703Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 98703Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 108703Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 118703Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 128703Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 138703Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 141762SN/A * this software without specific prior written permission. 157897Shestness@cs.utexas.edu * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272SN/A * 282SN/A * Authors: Ali Saidi 292SN/A */ 302SN/A 312SN/A#ifndef __ARCH_SPARC_TLB_HH__ 322SN/A#define __ARCH_SPARC_TLB_HH__ 332SN/A 342SN/A#include "arch/generic/tlb.hh" 352SN/A#include "arch/sparc/asi.hh" 362SN/A#include "arch/sparc/tlb_map.hh" 372SN/A#include "base/misc.hh" 382SN/A#include "mem/request.hh" 392SN/A#include "params/SparcTLB.hh" 402665Ssaidi@eecs.umich.edu 412665Ssaidi@eecs.umich.educlass ThreadContext; 422665Ssaidi@eecs.umich.educlass Packet; 432665Ssaidi@eecs.umich.edu 447897Shestness@cs.utexas.edunamespace SparcISA 452SN/A{ 462SN/A 472SN/Aclass TLB : public BaseTLB 482SN/A{ 492SN/A // These faults need to be able to populate the tlb in SE mode. 502SN/A friend class FastInstructionAccessMMUMiss; 519645SAndreas.Sandberg@ARM.com friend class FastDataAccessMMUMiss; 5275SN/A 532SN/A // TLB state 542439SN/A protected: 552439SN/A // Only used when this is the data TLB. 56603SN/A uint64_t sfar; 57603SN/A uint64_t c0_tsb_ps0; 584762Snate@binkert.org uint64_t c0_tsb_ps1; 598769Sgblack@eecs.umich.edu uint64_t c0_config; 608703Sandreas.hansson@arm.com uint64_t cx_tsb_ps0; 612520SN/A uint64_t cx_tsb_ps1; 629847Sandreas.hansson@arm.com uint64_t cx_config; 638931Sandreas.hansson@arm.com uint64_t sfsr; 644762Snate@binkert.org uint64_t tag_access; 656658Snate@binkert.org 661634SN/A protected: 678769Sgblack@eecs.umich.edu TlbMap lookupTable;; 688769Sgblack@eecs.umich.edu typedef TlbMap::iterator MapIter; 691634SN/A 70803SN/A TlbEntry *tlb; 718769Sgblack@eecs.umich.edu 722SN/A int size; 738703Sandreas.hansson@arm.com int usedEntries; 742SN/A int lastReplaced; 758703Sandreas.hansson@arm.com 768703Sandreas.hansson@arm.com uint64_t cacheState; 778703Sandreas.hansson@arm.com bool cacheValid; 788703Sandreas.hansson@arm.com 798703Sandreas.hansson@arm.com std::list<TlbEntry*> freeList; 808703Sandreas.hansson@arm.com 818703Sandreas.hansson@arm.com enum FaultTypes { 828922Swilliam.wang@arm.com OtherFault = 0, 838703Sandreas.hansson@arm.com PrivViolation = 0x1, 848703Sandreas.hansson@arm.com SideEffect = 0x2, 858703Sandreas.hansson@arm.com AtomicToIo = 0x4, 868703Sandreas.hansson@arm.com IllegalAsi = 0x8, 878703Sandreas.hansson@arm.com LoadFromNfo = 0x10, 888703Sandreas.hansson@arm.com VaOutOfRange = 0x20, 898703Sandreas.hansson@arm.com VaOutOfRangeJmp = 0x40 908922Swilliam.wang@arm.com }; 918703Sandreas.hansson@arm.com 928975Sandreas.hansson@arm.com enum ContextType { 938703Sandreas.hansson@arm.com Primary = 0, 948922Swilliam.wang@arm.com Secondary = 1, 958922Swilliam.wang@arm.com Nucleus = 2 968703Sandreas.hansson@arm.com }; 978703Sandreas.hansson@arm.com 988703Sandreas.hansson@arm.com enum TsbPageSize { 998703Sandreas.hansson@arm.com Ps0, 100603SN/A Ps1 1012901Ssaidi@eecs.umich.edu }; 1028703Sandreas.hansson@arm.com public: 1038706Sandreas.hansson@arm.com /** lookup an entry in the TLB based on the partition id, and real bit if 1048706Sandreas.hansson@arm.com * real is true or the partition id, and context id if real is false. 1058706Sandreas.hansson@arm.com * @param va the virtual address not shifted (e.g. bottom 13 bits are 0) 1068706Sandreas.hansson@arm.com * @param paritition_id partition this entry is for 1078706Sandreas.hansson@arm.com * @param real is this a real->phys or virt->phys translation 1088706Sandreas.hansson@arm.com * @param context_id if this is virt->phys what context 1098852Sandreas.hansson@arm.com * @param update_used should ew update the used bits in the 1108703Sandreas.hansson@arm.com * entries on not useful if we are trying to do a va->pa without 1118703Sandreas.hansson@arm.com * mucking with any state for a debug read for example. 1128703Sandreas.hansson@arm.com * @return A pointer to a tlb entry 1138703Sandreas.hansson@arm.com */ 1148852Sandreas.hansson@arm.com TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0, 1158703Sandreas.hansson@arm.com bool update_used = true); 1168922Swilliam.wang@arm.com 1178703Sandreas.hansson@arm.com /** Remove all entries from the TLB */ 1188703Sandreas.hansson@arm.com void flushAll(); 1198703Sandreas.hansson@arm.com 1208703Sandreas.hansson@arm.com protected: 1219294Sandreas.hansson@arm.com /** Insert a PTE into the TLB. */ 1229294Sandreas.hansson@arm.com void insert(Addr vpn, int partition_id, int context_id, bool real, 1238703Sandreas.hansson@arm.com const PageTableEntry& PTE, int entry = -1); 1249524SAndreas.Sandberg@ARM.com 1252902Ssaidi@eecs.umich.edu /** Given an entry id, read that tlb entries' tag. */ 1269524SAndreas.Sandberg@ARM.com uint64_t TagRead(int entry); 1279524SAndreas.Sandberg@ARM.com 1289524SAndreas.Sandberg@ARM.com /** Remove all non-locked entries from the tlb that match partition id. */ 1299524SAndreas.Sandberg@ARM.com void demapAll(int partition_id); 1309524SAndreas.Sandberg@ARM.com 1319524SAndreas.Sandberg@ARM.com /** Remove all entries that match a given context/partition id. */ 1329524SAndreas.Sandberg@ARM.com void demapContext(int partition_id, int context_id); 1339524SAndreas.Sandberg@ARM.com 1349524SAndreas.Sandberg@ARM.com /** Remve all entries that match a certain partition id, (contextid), and 1359524SAndreas.Sandberg@ARM.com * va). */ 1369524SAndreas.Sandberg@ARM.com void demapPage(Addr va, int partition_id, bool real, int context_id); 1379524SAndreas.Sandberg@ARM.com 1389524SAndreas.Sandberg@ARM.com /** Checks if the virtual address provided is a valid one. */ 1394762Snate@binkert.org bool validVirtualAddress(Addr va, bool am); 1402901Ssaidi@eecs.umich.edu 1419524SAndreas.Sandberg@ARM.com void writeSfsr(bool write, ContextType ct, 1429524SAndreas.Sandberg@ARM.com bool se, FaultTypes ft, int asi); 1439524SAndreas.Sandberg@ARM.com 1449524SAndreas.Sandberg@ARM.com void clearUsedBits(); 1459524SAndreas.Sandberg@ARM.com 1469524SAndreas.Sandberg@ARM.com 1479524SAndreas.Sandberg@ARM.com void writeTagAccess(Addr va, int context); 1489524SAndreas.Sandberg@ARM.com 1499524SAndreas.Sandberg@ARM.com Fault translateInst(RequestPtr req, ThreadContext *tc); 1509524SAndreas.Sandberg@ARM.com Fault translateData(RequestPtr req, ThreadContext *tc, bool write); 1519524SAndreas.Sandberg@ARM.com 1529524SAndreas.Sandberg@ARM.com public: 1539524SAndreas.Sandberg@ARM.com typedef SparcTLBParams Params; 1549524SAndreas.Sandberg@ARM.com TLB(const Params *p); 1559524SAndreas.Sandberg@ARM.com 1569524SAndreas.Sandberg@ARM.com void takeOverFrom(BaseTLB *otlb) {} 1579524SAndreas.Sandberg@ARM.com 1589524SAndreas.Sandberg@ARM.com void 1599524SAndreas.Sandberg@ARM.com demapPage(Addr vaddr, uint64_t asn) 1609524SAndreas.Sandberg@ARM.com { 1619524SAndreas.Sandberg@ARM.com panic("demapPage(Addr) is not implemented.\n"); 1629524SAndreas.Sandberg@ARM.com } 1639524SAndreas.Sandberg@ARM.com 1649524SAndreas.Sandberg@ARM.com void dumpAll(); 1659524SAndreas.Sandberg@ARM.com 1669524SAndreas.Sandberg@ARM.com Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); 1679524SAndreas.Sandberg@ARM.com void translateTiming(RequestPtr req, ThreadContext *tc, 1689524SAndreas.Sandberg@ARM.com Translation *translation, Mode mode); 1699524SAndreas.Sandberg@ARM.com /** Stub function for compilation support with CheckerCPU. SPARC ISA 1709524SAndreas.Sandberg@ARM.com * does not support the Checker model at the moment 1719524SAndreas.Sandberg@ARM.com */ 1729524SAndreas.Sandberg@ARM.com Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode); 1739524SAndreas.Sandberg@ARM.com Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const; 1749524SAndreas.Sandberg@ARM.com Cycles doMmuRegRead(ThreadContext *tc, Packet *pkt); 1759524SAndreas.Sandberg@ARM.com Cycles doMmuRegWrite(ThreadContext *tc, Packet *pkt); 1769524SAndreas.Sandberg@ARM.com void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs); 1779524SAndreas.Sandberg@ARM.com 1782901Ssaidi@eecs.umich.edu // Checkpointing 1794762Snate@binkert.org void serialize(CheckpointOut &cp) const override; 1809524SAndreas.Sandberg@ARM.com void unserialize(CheckpointIn &cp) override; 1812901Ssaidi@eecs.umich.edu 1829814Sandreas.hansson@arm.com /** Give an entry id, read that tlb entries' tte */ 1839814Sandreas.hansson@arm.com uint64_t TteRead(int entry); 1849814Sandreas.hansson@arm.com 1859814Sandreas.hansson@arm.com private: 1869814Sandreas.hansson@arm.com void writeSfsr(Addr a, bool write, ContextType ct, 1879850Sandreas.hansson@arm.com bool se, FaultTypes ft, int asi); 1882SN/A 1899850Sandreas.hansson@arm.com uint64_t MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, 1902SN/A uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config); 1912680Sktlim@umich.edu 1925714Shsul@eecs.umich.edu 1931806SN/A TlbEntry *cacheEntry[2]; 1946221Snate@binkert.org ASI cacheAsi[2]; 1955713Shsul@eecs.umich.edu}; 1965713Shsul@eecs.umich.edu 1975713Shsul@eecs.umich.edu} 1985713Shsul@eecs.umich.edu 1995714Shsul@eecs.umich.edu#endif // __ARCH_SPARC_TLB_HH__ 2001806SN/A