tlb.hh revision 10474:799c8ee4ecba 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#ifndef __ARCH_SPARC_TLB_HH__
32#define __ARCH_SPARC_TLB_HH__
33
34#include "arch/sparc/asi.hh"
35#include "arch/sparc/tlb_map.hh"
36#include "base/misc.hh"
37#include "mem/request.hh"
38#include "params/SparcTLB.hh"
39#include "sim/tlb.hh"
40
41class ThreadContext;
42class Packet;
43
44namespace SparcISA
45{
46
47class TLB : public BaseTLB
48{
49    // These faults need to be able to populate the tlb in SE mode.
50    friend class FastInstructionAccessMMUMiss;
51    friend class FastDataAccessMMUMiss;
52
53    // TLB state
54  protected:
55    // Only used when this is the data TLB.
56    uint64_t sfar;
57    uint64_t c0_tsb_ps0;
58    uint64_t c0_tsb_ps1;
59    uint64_t c0_config;
60    uint64_t cx_tsb_ps0;
61    uint64_t cx_tsb_ps1;
62    uint64_t cx_config;
63    uint64_t sfsr;
64    uint64_t tag_access;
65
66  protected:
67    TlbMap lookupTable;;
68    typedef TlbMap::iterator MapIter;
69
70    TlbEntry *tlb;
71
72    int size;
73    int usedEntries;
74    int lastReplaced;
75
76    uint64_t cacheState;
77    bool cacheValid;
78
79    std::list<TlbEntry*> freeList;
80
81    enum FaultTypes {
82        OtherFault = 0,
83        PrivViolation = 0x1,
84        SideEffect = 0x2,
85        AtomicToIo = 0x4,
86        IllegalAsi = 0x8,
87        LoadFromNfo = 0x10,
88        VaOutOfRange = 0x20,
89        VaOutOfRangeJmp = 0x40
90    };
91
92    enum ContextType {
93        Primary = 0,
94        Secondary = 1,
95        Nucleus = 2
96    };
97
98    enum TsbPageSize {
99        Ps0,
100        Ps1
101    };
102  public:
103    /** lookup an entry in the TLB based on the partition id, and real bit if
104     * real is true or the partition id, and context id if real is false.
105     * @param va the virtual address not shifted (e.g. bottom 13 bits are 0)
106     * @param paritition_id partition this entry is for
107     * @param real is this a real->phys or virt->phys translation
108     * @param context_id if this is virt->phys what context
109     * @param update_used should ew update the used bits in the
110     * entries on not useful if we are trying to do a va->pa without
111     * mucking with any state for a debug read for example.
112     * @return A pointer to a tlb entry
113     */
114    TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0,
115            bool update_used = true);
116
117    /** Remove all entries from the TLB */
118    void flushAll();
119
120  protected:
121    /** Insert a PTE into the TLB. */
122    void insert(Addr vpn, int partition_id, int context_id, bool real,
123            const PageTableEntry& PTE, int entry = -1);
124
125    /** Given an entry id, read that tlb entries' tag. */
126    uint64_t TagRead(int entry);
127
128    /** Remove all non-locked entries from the tlb that match partition id. */
129    void demapAll(int partition_id);
130
131    /** Remove all entries that match a given context/partition id. */
132    void demapContext(int partition_id, int context_id);
133
134    /** Remve all entries that match a certain partition id, (contextid), and
135     * va). */
136    void demapPage(Addr va, int partition_id, bool real, int context_id);
137
138    /** Checks if the virtual address provided is a valid one. */
139    bool validVirtualAddress(Addr va, bool am);
140
141    void writeSfsr(bool write, ContextType ct,
142            bool se, FaultTypes ft, int asi);
143
144    void clearUsedBits();
145
146
147    void writeTagAccess(Addr va, int context);
148
149    Fault translateInst(RequestPtr req, ThreadContext *tc);
150    Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
151
152  public:
153    typedef SparcTLBParams Params;
154    TLB(const Params *p);
155
156    void takeOverFrom(BaseTLB *otlb) {}
157
158    void
159    demapPage(Addr vaddr, uint64_t asn)
160    {
161        panic("demapPage(Addr) is not implemented.\n");
162    }
163
164    void dumpAll();
165
166    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
167    void translateTiming(RequestPtr req, ThreadContext *tc,
168            Translation *translation, Mode mode);
169    /** Stub function for compilation support with CheckerCPU. SPARC ISA
170     *  does not support the Checker model at the moment
171     */
172    Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
173    Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
174    Cycles doMmuRegRead(ThreadContext *tc, Packet *pkt);
175    Cycles doMmuRegWrite(ThreadContext *tc, Packet *pkt);
176    void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
177
178    // Checkpointing
179    virtual void serialize(std::ostream &os);
180    virtual void unserialize(Checkpoint *cp, const std::string &section);
181
182    /** Give an entry id, read that tlb entries' tte */
183    uint64_t TteRead(int entry);
184
185  private:
186    void writeSfsr(Addr a, bool write, ContextType ct,
187            bool se, FaultTypes ft, int asi);
188
189    uint64_t MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
190        uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config);
191
192
193    TlbEntry *cacheEntry[2];
194    ASI cacheAsi[2];
195};
196
197}
198
199#endif // __ARCH_SPARC_TLB_HH__
200