tlb.hh revision 9180
12650Ssaidi@eecs.umich.edu/* 22650Ssaidi@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 32650Ssaidi@eecs.umich.edu * All rights reserved. 42650Ssaidi@eecs.umich.edu * 52650Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 62650Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 72650Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 82650Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 92650Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 102650Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 112650Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 122650Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 132650Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 142650Ssaidi@eecs.umich.edu * this software without specific prior written permission. 152650Ssaidi@eecs.umich.edu * 162650Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172650Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182650Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192650Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202650Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212650Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222650Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232650Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242650Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252650Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262650Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272650Ssaidi@eecs.umich.edu * 282650Ssaidi@eecs.umich.edu * Authors: Ali Saidi 292650Ssaidi@eecs.umich.edu */ 302650Ssaidi@eecs.umich.edu 312650Ssaidi@eecs.umich.edu#ifndef __ARCH_SPARC_TLB_HH__ 322650Ssaidi@eecs.umich.edu#define __ARCH_SPARC_TLB_HH__ 332650Ssaidi@eecs.umich.edu 343836Ssaidi@eecs.umich.edu#include "arch/sparc/asi.hh" 353804Ssaidi@eecs.umich.edu#include "arch/sparc/tlb_map.hh" 363602Sgblack@eecs.umich.edu#include "base/misc.hh" 373569Sgblack@eecs.umich.edu#include "mem/request.hh" 386022Sgblack@eecs.umich.edu#include "params/SparcTLB.hh" 397878Sgblack@eecs.umich.edu#include "sim/fault_fwd.hh" 405358Sgblack@eecs.umich.edu#include "sim/tlb.hh" 413468Sgblack@eecs.umich.edu 423468Sgblack@eecs.umich.educlass ThreadContext; 433806Ssaidi@eecs.umich.educlass Packet; 443468Sgblack@eecs.umich.edu 453468Sgblack@eecs.umich.edunamespace SparcISA 463468Sgblack@eecs.umich.edu{ 473603Ssaidi@eecs.umich.edu 485358Sgblack@eecs.umich.educlass TLB : public BaseTLB 493804Ssaidi@eecs.umich.edu{ 507741Sgblack@eecs.umich.edu // These faults need to be able to populate the tlb in SE mode. 514997Sgblack@eecs.umich.edu friend class FastInstructionAccessMMUMiss; 524997Sgblack@eecs.umich.edu friend class FastDataAccessMMUMiss; 534997Sgblack@eecs.umich.edu 547741Sgblack@eecs.umich.edu // TLB state 554990Sgblack@eecs.umich.edu protected: 566022Sgblack@eecs.umich.edu // Only used when this is the data TLB. 576022Sgblack@eecs.umich.edu uint64_t sfar; 584990Sgblack@eecs.umich.edu uint64_t c0_tsb_ps0; 594990Sgblack@eecs.umich.edu uint64_t c0_tsb_ps1; 604990Sgblack@eecs.umich.edu uint64_t c0_config; 614990Sgblack@eecs.umich.edu uint64_t cx_tsb_ps0; 624990Sgblack@eecs.umich.edu uint64_t cx_tsb_ps1; 634990Sgblack@eecs.umich.edu uint64_t cx_config; 644990Sgblack@eecs.umich.edu uint64_t sfsr; 654990Sgblack@eecs.umich.edu uint64_t tag_access; 664990Sgblack@eecs.umich.edu 673804Ssaidi@eecs.umich.edu protected: 683804Ssaidi@eecs.umich.edu TlbMap lookupTable;; 693804Ssaidi@eecs.umich.edu typedef TlbMap::iterator MapIter; 703804Ssaidi@eecs.umich.edu 713804Ssaidi@eecs.umich.edu TlbEntry *tlb; 723804Ssaidi@eecs.umich.edu 733804Ssaidi@eecs.umich.edu int size; 743804Ssaidi@eecs.umich.edu int usedEntries; 753881Ssaidi@eecs.umich.edu int lastReplaced; 763804Ssaidi@eecs.umich.edu 773836Ssaidi@eecs.umich.edu uint64_t cacheState; 783836Ssaidi@eecs.umich.edu bool cacheValid; 793836Ssaidi@eecs.umich.edu 803881Ssaidi@eecs.umich.edu std::list<TlbEntry*> freeList; 813881Ssaidi@eecs.umich.edu 823804Ssaidi@eecs.umich.edu enum FaultTypes { 833804Ssaidi@eecs.umich.edu OtherFault = 0, 843804Ssaidi@eecs.umich.edu PrivViolation = 0x1, 853804Ssaidi@eecs.umich.edu SideEffect = 0x2, 863804Ssaidi@eecs.umich.edu AtomicToIo = 0x4, 873804Ssaidi@eecs.umich.edu IllegalAsi = 0x8, 883804Ssaidi@eecs.umich.edu LoadFromNfo = 0x10, 893804Ssaidi@eecs.umich.edu VaOutOfRange = 0x20, 903804Ssaidi@eecs.umich.edu VaOutOfRangeJmp = 0x40 913468Sgblack@eecs.umich.edu }; 923468Sgblack@eecs.umich.edu 933804Ssaidi@eecs.umich.edu enum ContextType { 943804Ssaidi@eecs.umich.edu Primary = 0, 953804Ssaidi@eecs.umich.edu Secondary = 1, 963804Ssaidi@eecs.umich.edu Nucleus = 2 973468Sgblack@eecs.umich.edu }; 983468Sgblack@eecs.umich.edu 994070Ssaidi@eecs.umich.edu enum TsbPageSize { 1004070Ssaidi@eecs.umich.edu Ps0, 1014070Ssaidi@eecs.umich.edu Ps1 1024070Ssaidi@eecs.umich.edu }; 1034070Ssaidi@eecs.umich.edu public: 1043804Ssaidi@eecs.umich.edu /** lookup an entry in the TLB based on the partition id, and real bit if 1053804Ssaidi@eecs.umich.edu * real is true or the partition id, and context id if real is false. 1063804Ssaidi@eecs.umich.edu * @param va the virtual address not shifted (e.g. bottom 13 bits are 0) 1073804Ssaidi@eecs.umich.edu * @param paritition_id partition this entry is for 1083804Ssaidi@eecs.umich.edu * @param real is this a real->phys or virt->phys translation 1093804Ssaidi@eecs.umich.edu * @param context_id if this is virt->phys what context 1105555Snate@binkert.org * @param update_used should ew update the used bits in the 1115555Snate@binkert.org * entries on not useful if we are trying to do a va->pa without 1125555Snate@binkert.org * mucking with any state for a debug read for example. 1133804Ssaidi@eecs.umich.edu * @return A pointer to a tlb entry 1143804Ssaidi@eecs.umich.edu */ 1154070Ssaidi@eecs.umich.edu TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0, 1164070Ssaidi@eecs.umich.edu bool update_used = true); 1174070Ssaidi@eecs.umich.edu protected: 1183804Ssaidi@eecs.umich.edu /** Insert a PTE into the TLB. */ 1193804Ssaidi@eecs.umich.edu void insert(Addr vpn, int partition_id, int context_id, bool real, 1203826Ssaidi@eecs.umich.edu const PageTableEntry& PTE, int entry = -1); 1213804Ssaidi@eecs.umich.edu 1223804Ssaidi@eecs.umich.edu /** Given an entry id, read that tlb entries' tag. */ 1233804Ssaidi@eecs.umich.edu uint64_t TagRead(int entry); 1243804Ssaidi@eecs.umich.edu 1253804Ssaidi@eecs.umich.edu /** Remove all entries from the TLB */ 1263804Ssaidi@eecs.umich.edu void invalidateAll(); 1273804Ssaidi@eecs.umich.edu 1283804Ssaidi@eecs.umich.edu /** Remove all non-locked entries from the tlb that match partition id. */ 1293804Ssaidi@eecs.umich.edu void demapAll(int partition_id); 1303804Ssaidi@eecs.umich.edu 1313804Ssaidi@eecs.umich.edu /** Remove all entries that match a given context/partition id. */ 1323804Ssaidi@eecs.umich.edu void demapContext(int partition_id, int context_id); 1333804Ssaidi@eecs.umich.edu 1343804Ssaidi@eecs.umich.edu /** Remve all entries that match a certain partition id, (contextid), and 1353804Ssaidi@eecs.umich.edu * va). */ 1363804Ssaidi@eecs.umich.edu void demapPage(Addr va, int partition_id, bool real, int context_id); 1373804Ssaidi@eecs.umich.edu 1383804Ssaidi@eecs.umich.edu /** Checks if the virtual address provided is a valid one. */ 1393804Ssaidi@eecs.umich.edu bool validVirtualAddress(Addr va, bool am); 1403804Ssaidi@eecs.umich.edu 1414990Sgblack@eecs.umich.edu void writeSfsr(bool write, ContextType ct, 1423804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi); 1433804Ssaidi@eecs.umich.edu 1443834Sgblack@eecs.umich.edu void clearUsedBits(); 1453804Ssaidi@eecs.umich.edu 1463804Ssaidi@eecs.umich.edu 1474990Sgblack@eecs.umich.edu void writeTagAccess(Addr va, int context); 1483826Ssaidi@eecs.umich.edu 1496022Sgblack@eecs.umich.edu Fault translateInst(RequestPtr req, ThreadContext *tc); 1506022Sgblack@eecs.umich.edu Fault translateData(RequestPtr req, ThreadContext *tc, bool write); 1516022Sgblack@eecs.umich.edu 1523804Ssaidi@eecs.umich.edu public: 1535034Smilesck@eecs.umich.edu typedef SparcTLBParams Params; 1545034Smilesck@eecs.umich.edu TLB(const Params *p); 1553804Ssaidi@eecs.umich.edu 1567741Sgblack@eecs.umich.edu void 1577741Sgblack@eecs.umich.edu demapPage(Addr vaddr, uint64_t asn) 1585358Sgblack@eecs.umich.edu { 1595358Sgblack@eecs.umich.edu panic("demapPage(Addr) is not implemented.\n"); 1605358Sgblack@eecs.umich.edu } 1615358Sgblack@eecs.umich.edu 1623826Ssaidi@eecs.umich.edu void dumpAll(); 1633826Ssaidi@eecs.umich.edu 1646023Snate@binkert.org Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); 1655894Sgblack@eecs.umich.edu void translateTiming(RequestPtr req, ThreadContext *tc, 1666023Snate@binkert.org Translation *translation, Mode mode); 1678888Sgeoffrey.blake@arm.com /** Stub function for compilation support with CheckerCPU. SPARC ISA 1688888Sgeoffrey.blake@arm.com * does not support the Checker model at the moment 1698888Sgeoffrey.blake@arm.com */ 1708888Sgeoffrey.blake@arm.com Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode); 1719180Sandreas.hansson@arm.com Cycles doMmuRegRead(ThreadContext *tc, Packet *pkt); 1729180Sandreas.hansson@arm.com Cycles doMmuRegWrite(ThreadContext *tc, Packet *pkt); 1734070Ssaidi@eecs.umich.edu void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs); 1743804Ssaidi@eecs.umich.edu 1754990Sgblack@eecs.umich.edu // Checkpointing 1764990Sgblack@eecs.umich.edu virtual void serialize(std::ostream &os); 1774990Sgblack@eecs.umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 1784990Sgblack@eecs.umich.edu 1796022Sgblack@eecs.umich.edu /** Give an entry id, read that tlb entries' tte */ 1806022Sgblack@eecs.umich.edu uint64_t TteRead(int entry); 1816022Sgblack@eecs.umich.edu 1823804Ssaidi@eecs.umich.edu private: 1834990Sgblack@eecs.umich.edu void writeSfsr(Addr a, bool write, ContextType ct, 1843804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi); 1853826Ssaidi@eecs.umich.edu 1864070Ssaidi@eecs.umich.edu uint64_t MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, 1874070Ssaidi@eecs.umich.edu uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config); 1884070Ssaidi@eecs.umich.edu 1894070Ssaidi@eecs.umich.edu 1903836Ssaidi@eecs.umich.edu TlbEntry *cacheEntry[2]; 1913836Ssaidi@eecs.umich.edu ASI cacheAsi[2]; 1923804Ssaidi@eecs.umich.edu}; 1933804Ssaidi@eecs.umich.edu 1943468Sgblack@eecs.umich.edu} 1952650Ssaidi@eecs.umich.edu 1962650Ssaidi@eecs.umich.edu#endif // __ARCH_SPARC_TLB_HH__ 197