tlb.hh revision 13913
12650Ssaidi@eecs.umich.edu/* 22650Ssaidi@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 32650Ssaidi@eecs.umich.edu * All rights reserved. 42650Ssaidi@eecs.umich.edu * 52650Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 62650Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 72650Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 82650Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 92650Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 102650Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 112650Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 122650Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 132650Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 142650Ssaidi@eecs.umich.edu * this software without specific prior written permission. 152650Ssaidi@eecs.umich.edu * 162650Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172650Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182650Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192650Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202650Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212650Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222650Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232650Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242650Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252650Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262650Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272650Ssaidi@eecs.umich.edu * 282650Ssaidi@eecs.umich.edu * Authors: Ali Saidi 292650Ssaidi@eecs.umich.edu */ 302650Ssaidi@eecs.umich.edu 312650Ssaidi@eecs.umich.edu#ifndef __ARCH_SPARC_TLB_HH__ 322650Ssaidi@eecs.umich.edu#define __ARCH_SPARC_TLB_HH__ 332650Ssaidi@eecs.umich.edu 3410687SAndreas.Sandberg@ARM.com#include "arch/generic/tlb.hh" 353836Ssaidi@eecs.umich.edu#include "arch/sparc/asi.hh" 363804Ssaidi@eecs.umich.edu#include "arch/sparc/tlb_map.hh" 3712334Sgabeblack@google.com#include "base/logging.hh" 383569Sgblack@eecs.umich.edu#include "mem/request.hh" 396022Sgblack@eecs.umich.edu#include "params/SparcTLB.hh" 403468Sgblack@eecs.umich.edu 413468Sgblack@eecs.umich.educlass ThreadContext; 423806Ssaidi@eecs.umich.educlass Packet; 433468Sgblack@eecs.umich.edu 443468Sgblack@eecs.umich.edunamespace SparcISA 453468Sgblack@eecs.umich.edu{ 463603Ssaidi@eecs.umich.edu 4713913Sgabeblack@google.comconst Addr StartVAddrHole = ULL(0x0000800000000000); 4813913Sgabeblack@google.comconst Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF); 4913913Sgabeblack@google.comconst Addr VAddrAMask = ULL(0xFFFFFFFF); 5013913Sgabeblack@google.comconst Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF); 5113913Sgabeblack@google.com 525358Sgblack@eecs.umich.educlass TLB : public BaseTLB 533804Ssaidi@eecs.umich.edu{ 547741Sgblack@eecs.umich.edu // These faults need to be able to populate the tlb in SE mode. 554997Sgblack@eecs.umich.edu friend class FastInstructionAccessMMUMiss; 564997Sgblack@eecs.umich.edu friend class FastDataAccessMMUMiss; 574997Sgblack@eecs.umich.edu 587741Sgblack@eecs.umich.edu // TLB state 594990Sgblack@eecs.umich.edu protected: 606022Sgblack@eecs.umich.edu // Only used when this is the data TLB. 616022Sgblack@eecs.umich.edu uint64_t sfar; 624990Sgblack@eecs.umich.edu uint64_t c0_tsb_ps0; 634990Sgblack@eecs.umich.edu uint64_t c0_tsb_ps1; 644990Sgblack@eecs.umich.edu uint64_t c0_config; 654990Sgblack@eecs.umich.edu uint64_t cx_tsb_ps0; 664990Sgblack@eecs.umich.edu uint64_t cx_tsb_ps1; 674990Sgblack@eecs.umich.edu uint64_t cx_config; 684990Sgblack@eecs.umich.edu uint64_t sfsr; 694990Sgblack@eecs.umich.edu uint64_t tag_access; 704990Sgblack@eecs.umich.edu 713804Ssaidi@eecs.umich.edu protected: 723804Ssaidi@eecs.umich.edu TlbMap lookupTable;; 733804Ssaidi@eecs.umich.edu typedef TlbMap::iterator MapIter; 743804Ssaidi@eecs.umich.edu 753804Ssaidi@eecs.umich.edu TlbEntry *tlb; 763804Ssaidi@eecs.umich.edu 773804Ssaidi@eecs.umich.edu int size; 783804Ssaidi@eecs.umich.edu int usedEntries; 793881Ssaidi@eecs.umich.edu int lastReplaced; 803804Ssaidi@eecs.umich.edu 813836Ssaidi@eecs.umich.edu uint64_t cacheState; 823836Ssaidi@eecs.umich.edu bool cacheValid; 833836Ssaidi@eecs.umich.edu 843881Ssaidi@eecs.umich.edu std::list<TlbEntry*> freeList; 853881Ssaidi@eecs.umich.edu 863804Ssaidi@eecs.umich.edu enum FaultTypes { 873804Ssaidi@eecs.umich.edu OtherFault = 0, 883804Ssaidi@eecs.umich.edu PrivViolation = 0x1, 893804Ssaidi@eecs.umich.edu SideEffect = 0x2, 903804Ssaidi@eecs.umich.edu AtomicToIo = 0x4, 913804Ssaidi@eecs.umich.edu IllegalAsi = 0x8, 923804Ssaidi@eecs.umich.edu LoadFromNfo = 0x10, 933804Ssaidi@eecs.umich.edu VaOutOfRange = 0x20, 943804Ssaidi@eecs.umich.edu VaOutOfRangeJmp = 0x40 953468Sgblack@eecs.umich.edu }; 963468Sgblack@eecs.umich.edu 973804Ssaidi@eecs.umich.edu enum ContextType { 983804Ssaidi@eecs.umich.edu Primary = 0, 993804Ssaidi@eecs.umich.edu Secondary = 1, 1003804Ssaidi@eecs.umich.edu Nucleus = 2 1013468Sgblack@eecs.umich.edu }; 1023468Sgblack@eecs.umich.edu 1034070Ssaidi@eecs.umich.edu enum TsbPageSize { 1044070Ssaidi@eecs.umich.edu Ps0, 1054070Ssaidi@eecs.umich.edu Ps1 1064070Ssaidi@eecs.umich.edu }; 1074070Ssaidi@eecs.umich.edu public: 1083804Ssaidi@eecs.umich.edu /** lookup an entry in the TLB based on the partition id, and real bit if 1093804Ssaidi@eecs.umich.edu * real is true or the partition id, and context id if real is false. 1103804Ssaidi@eecs.umich.edu * @param va the virtual address not shifted (e.g. bottom 13 bits are 0) 1113804Ssaidi@eecs.umich.edu * @param paritition_id partition this entry is for 1123804Ssaidi@eecs.umich.edu * @param real is this a real->phys or virt->phys translation 1133804Ssaidi@eecs.umich.edu * @param context_id if this is virt->phys what context 1145555Snate@binkert.org * @param update_used should ew update the used bits in the 1155555Snate@binkert.org * entries on not useful if we are trying to do a va->pa without 1165555Snate@binkert.org * mucking with any state for a debug read for example. 1173804Ssaidi@eecs.umich.edu * @return A pointer to a tlb entry 1183804Ssaidi@eecs.umich.edu */ 1194070Ssaidi@eecs.umich.edu TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0, 1204070Ssaidi@eecs.umich.edu bool update_used = true); 1219446SAndreas.Sandberg@ARM.com 1229446SAndreas.Sandberg@ARM.com /** Remove all entries from the TLB */ 12311341Sandreas.hansson@arm.com void flushAll() override; 1249446SAndreas.Sandberg@ARM.com 1254070Ssaidi@eecs.umich.edu protected: 1263804Ssaidi@eecs.umich.edu /** Insert a PTE into the TLB. */ 1273804Ssaidi@eecs.umich.edu void insert(Addr vpn, int partition_id, int context_id, bool real, 1283826Ssaidi@eecs.umich.edu const PageTableEntry& PTE, int entry = -1); 1293804Ssaidi@eecs.umich.edu 1303804Ssaidi@eecs.umich.edu /** Given an entry id, read that tlb entries' tag. */ 1313804Ssaidi@eecs.umich.edu uint64_t TagRead(int entry); 1323804Ssaidi@eecs.umich.edu 1333804Ssaidi@eecs.umich.edu /** Remove all non-locked entries from the tlb that match partition id. */ 1343804Ssaidi@eecs.umich.edu void demapAll(int partition_id); 1353804Ssaidi@eecs.umich.edu 1363804Ssaidi@eecs.umich.edu /** Remove all entries that match a given context/partition id. */ 1373804Ssaidi@eecs.umich.edu void demapContext(int partition_id, int context_id); 1383804Ssaidi@eecs.umich.edu 1393804Ssaidi@eecs.umich.edu /** Remve all entries that match a certain partition id, (contextid), and 1403804Ssaidi@eecs.umich.edu * va). */ 1413804Ssaidi@eecs.umich.edu void demapPage(Addr va, int partition_id, bool real, int context_id); 1423804Ssaidi@eecs.umich.edu 1433804Ssaidi@eecs.umich.edu /** Checks if the virtual address provided is a valid one. */ 1443804Ssaidi@eecs.umich.edu bool validVirtualAddress(Addr va, bool am); 1453804Ssaidi@eecs.umich.edu 1464990Sgblack@eecs.umich.edu void writeSfsr(bool write, ContextType ct, 1473804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi); 1483804Ssaidi@eecs.umich.edu 1493834Sgblack@eecs.umich.edu void clearUsedBits(); 1503804Ssaidi@eecs.umich.edu 1513804Ssaidi@eecs.umich.edu 1524990Sgblack@eecs.umich.edu void writeTagAccess(Addr va, int context); 1533826Ssaidi@eecs.umich.edu 15412749Sgiacomo.travaglini@arm.com Fault translateInst(const RequestPtr &req, ThreadContext *tc); 15512749Sgiacomo.travaglini@arm.com Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write); 1566022Sgblack@eecs.umich.edu 1573804Ssaidi@eecs.umich.edu public: 1585034Smilesck@eecs.umich.edu typedef SparcTLBParams Params; 1595034Smilesck@eecs.umich.edu TLB(const Params *p); 1603804Ssaidi@eecs.umich.edu 16111341Sandreas.hansson@arm.com void takeOverFrom(BaseTLB *otlb) override {} 16210194SGeoffrey.Blake@arm.com 1637741Sgblack@eecs.umich.edu void 16411341Sandreas.hansson@arm.com demapPage(Addr vaddr, uint64_t asn) override 1655358Sgblack@eecs.umich.edu { 1665358Sgblack@eecs.umich.edu panic("demapPage(Addr) is not implemented.\n"); 1675358Sgblack@eecs.umich.edu } 1685358Sgblack@eecs.umich.edu 1693826Ssaidi@eecs.umich.edu void dumpAll(); 1703826Ssaidi@eecs.umich.edu 17112406Sgabeblack@google.com Fault translateAtomic( 17212749Sgiacomo.travaglini@arm.com const RequestPtr &req, ThreadContext *tc, Mode mode) override; 17312406Sgabeblack@google.com void translateTiming( 17412749Sgiacomo.travaglini@arm.com const RequestPtr &req, ThreadContext *tc, 17512406Sgabeblack@google.com Translation *translation, Mode mode) override; 17612406Sgabeblack@google.com Fault finalizePhysical( 17712749Sgiacomo.travaglini@arm.com const RequestPtr &req, 17812749Sgiacomo.travaglini@arm.com ThreadContext *tc, Mode mode) const override; 1799180Sandreas.hansson@arm.com Cycles doMmuRegRead(ThreadContext *tc, Packet *pkt); 1809180Sandreas.hansson@arm.com Cycles doMmuRegWrite(ThreadContext *tc, Packet *pkt); 1814070Ssaidi@eecs.umich.edu void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs); 1823804Ssaidi@eecs.umich.edu 1834990Sgblack@eecs.umich.edu // Checkpointing 18411168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 18511168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 1864990Sgblack@eecs.umich.edu 1876022Sgblack@eecs.umich.edu /** Give an entry id, read that tlb entries' tte */ 1886022Sgblack@eecs.umich.edu uint64_t TteRead(int entry); 1896022Sgblack@eecs.umich.edu 1903804Ssaidi@eecs.umich.edu private: 1914990Sgblack@eecs.umich.edu void writeSfsr(Addr a, bool write, ContextType ct, 1923804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi); 1933826Ssaidi@eecs.umich.edu 1944070Ssaidi@eecs.umich.edu uint64_t MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, 1954070Ssaidi@eecs.umich.edu uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config); 1964070Ssaidi@eecs.umich.edu 1974070Ssaidi@eecs.umich.edu 1983836Ssaidi@eecs.umich.edu TlbEntry *cacheEntry[2]; 1993836Ssaidi@eecs.umich.edu ASI cacheAsi[2]; 2003804Ssaidi@eecs.umich.edu}; 2013804Ssaidi@eecs.umich.edu 2023468Sgblack@eecs.umich.edu} 2032650Ssaidi@eecs.umich.edu 2042650Ssaidi@eecs.umich.edu#endif // __ARCH_SPARC_TLB_HH__ 205