process.cc revision 11389:1e55f16160cb
17008Snate@binkert.org/* 27008Snate@binkert.org * Copyright (c) 2003-2004 The Regents of The University of Michigan 37008Snate@binkert.org * All rights reserved. 47008Snate@binkert.org * 57008Snate@binkert.org * Redistribution and use in source and binary forms, with or without 67008Snate@binkert.org * modification, are permitted provided that the following conditions are 77008Snate@binkert.org * met: redistributions of source code must retain the above copyright 87008Snate@binkert.org * notice, this list of conditions and the following disclaimer; 97008Snate@binkert.org * redistributions in binary form must reproduce the above copyright 107008Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 117008Snate@binkert.org * documentation and/or other materials provided with the distribution; 127008Snate@binkert.org * neither the name of the copyright holders nor the names of its 137008Snate@binkert.org * contributors may be used to endorse or promote products derived from 147008Snate@binkert.org * this software without specific prior written permission. 157008Snate@binkert.org * 167008Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177008Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187008Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197008Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207008Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217008Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227008Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237008Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247008Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257008Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267008Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277008Snate@binkert.org * 286285Snate@binkert.org * Authors: Gabe Black 2910472Sandreas.hansson@arm.com * Ali Saidi 3010472Sandreas.hansson@arm.com */ 318232Snate@binkert.org 329104Shestness@cs.utexas.edu#include "arch/sparc/asi.hh" 337039Snate@binkert.org#include "arch/sparc/handlers.hh" 3411339SMichael.Lebeane@amd.com#include "arch/sparc/isa_traits.hh" 357039Snate@binkert.org#include "arch/sparc/process.hh" 3611108Sdavid.hashe@amd.com#include "arch/sparc/registers.hh" 376285Snate@binkert.org#include "arch/sparc/types.hh" 386876Ssteve.reinhardt@amd.com#include "base/loader/elf_object.hh" 3911339SMichael.Lebeane@amd.com#include "base/loader/object_file.hh" 406285Snate@binkert.org#include "base/misc.hh" 416285Snate@binkert.org#include "cpu/thread_context.hh" 426285Snate@binkert.org#include "debug/Stack.hh" 437039Snate@binkert.org#include "mem/page_table.hh" 447039Snate@binkert.org#include "sim/process_impl.hh" 456285Snate@binkert.org#include "sim/system.hh" 4611339SMichael.Lebeane@amd.com 477039Snate@binkert.orgusing namespace std; 487039Snate@binkert.orgusing namespace SparcISA; 4910518Snilay@cs.wisc.edu 5010518Snilay@cs.wisc.edustatic const int FirstArgumentReg = 8; 517039Snate@binkert.org 528615Snilay@cs.wisc.edu 536285Snate@binkert.orgSparcLiveProcess::SparcLiveProcess(LiveProcessParams * params, 547544SBrad.Beckmann@amd.com ObjectFile *objFile, Addr _StackBias) 557544SBrad.Beckmann@amd.com : LiveProcess(params, objFile), StackBias(_StackBias) 567544SBrad.Beckmann@amd.com{ 577544SBrad.Beckmann@amd.com 5811025Snilay@cs.wisc.edu // XXX all the below need to be updated for SPARC - Ali 5910562Sandreas.hansson@arm.com brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); 608615Snilay@cs.wisc.edu brk_point = roundUp(brk_point, PageBytes); 618615Snilay@cs.wisc.edu 626285Snate@binkert.org // Set pointer for next thread stack. Reserve 8M for main stack. 637039Snate@binkert.org next_thread_stack_base = stack_base - (8 * 1024 * 1024); 647039Snate@binkert.org 656285Snate@binkert.org // Initialize these to 0s 667039Snate@binkert.org fillStart = 0; 677039Snate@binkert.org spillStart = 0; 687039Snate@binkert.org} 697039Snate@binkert.org 707039Snate@binkert.orgvoid 717039Snate@binkert.orgSparcLiveProcess::handleTrap(int trapNum, ThreadContext *tc) 728615Snilay@cs.wisc.edu{ 736285Snate@binkert.org PCState pc = tc->pcState(); 7410472Sandreas.hansson@arm.com switch (trapNum) { 7510472Sandreas.hansson@arm.com case 0x01: // Software breakpoint 7611025Snilay@cs.wisc.edu warn("Software breakpoint encountered at pc %#x.\n", pc.pc()); 7711025Snilay@cs.wisc.edu break; 787453Snate@binkert.org case 0x02: // Division by zero 797039Snate@binkert.org warn("Software signaled a division by zero at pc %#x.\n", pc.pc()); 806888SBrad.Beckmann@amd.com break; 817453Snate@binkert.org case 0x03: // Flush window trap 827039Snate@binkert.org flushWindows(tc); 836888SBrad.Beckmann@amd.com break; 847915SBrad.Beckmann@amd.com case 0x04: // Clean windows 857915SBrad.Beckmann@amd.com warn("Ignoring process request for clean register " 867915SBrad.Beckmann@amd.com "windows at pc %#x.\n", pc.pc()); 877915SBrad.Beckmann@amd.com break; 887039Snate@binkert.org case 0x05: // Range check 896888SBrad.Beckmann@amd.com warn("Software signaled a range check at pc %#x.\n", pc.pc()); 907039Snate@binkert.org break; 9111111Snilay@cs.wisc.edu case 0x06: // Fix alignment 927453Snate@binkert.org warn("Ignoring process request for os assisted unaligned accesses " 936285Snate@binkert.org "at pc %#x.\n", pc.pc()); 947039Snate@binkert.org break; 956285Snate@binkert.org case 0x07: // Integer overflow 966285Snate@binkert.org warn("Software signaled an integer overflow at pc %#x.\n", pc.pc()); 977039Snate@binkert.org break; 987039Snate@binkert.org case 0x32: // Get integer condition codes 996285Snate@binkert.org warn("Ignoring process request to get the integer condition codes " 10010231Ssteve.reinhardt@amd.com "at pc %#x.\n", pc.pc()); 1017039Snate@binkert.org break; 1027039Snate@binkert.org case 0x33: // Set integer condition codes 1038162SBrad.Beckmann@amd.com warn("Ignoring process request to set the integer condition codes " 1048162SBrad.Beckmann@amd.com "at pc %#x.\n", pc.pc()); 1058162SBrad.Beckmann@amd.com break; 1068162SBrad.Beckmann@amd.com default: 1078162SBrad.Beckmann@amd.com panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum); 1088162SBrad.Beckmann@amd.com } 1097039Snate@binkert.org} 1107039Snate@binkert.org 1117039Snate@binkert.orgvoid 1126285Snate@binkert.orgSparcLiveProcess::initState() 11310472Sandreas.hansson@arm.com{ 11410472Sandreas.hansson@arm.com LiveProcess::initState(); 11511025Snilay@cs.wisc.edu 11611025Snilay@cs.wisc.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 1176888SBrad.Beckmann@amd.com // From the SPARC ABI 11811025Snilay@cs.wisc.edu 11911025Snilay@cs.wisc.edu // Setup default FP state 1206888SBrad.Beckmann@amd.com tc->setMiscRegNoEffect(MISCREG_FSR, 0); 1217453Snate@binkert.org 1227039Snate@binkert.org tc->setMiscRegNoEffect(MISCREG_TICK, 0); 1236888SBrad.Beckmann@amd.com 1247453Snate@binkert.org /* 1257039Snate@binkert.org * Register window management registers 1267039Snate@binkert.org */ 1277039Snate@binkert.org 1287039Snate@binkert.org // No windows contain info from other programs 1296888SBrad.Beckmann@amd.com // tc->setMiscRegNoEffect(MISCREG_OTHERWIN, 0); 1307039Snate@binkert.org tc->setIntReg(NumIntArchRegs + 6, 0); 1317453Snate@binkert.org // There are no windows to pop 1327039Snate@binkert.org // tc->setMiscRegNoEffect(MISCREG_CANRESTORE, 0); 1337453Snate@binkert.org tc->setIntReg(NumIntArchRegs + 4, 0); 1347039Snate@binkert.org // All windows are available to save into 1356888SBrad.Beckmann@amd.com // tc->setMiscRegNoEffect(MISCREG_CANSAVE, NWindows - 2); 1367039Snate@binkert.org tc->setIntReg(NumIntArchRegs + 3, NWindows - 2); 13711111Snilay@cs.wisc.edu // All windows are "clean" 1387453Snate@binkert.org // tc->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows); 13910917Sbrandon.potter@amd.com tc->setIntReg(NumIntArchRegs + 5, NWindows); 1408160SBrad.Beckmann@amd.com // Start with register window 0 1418160SBrad.Beckmann@amd.com tc->setMiscReg(MISCREG_CWP, 0); 1428160SBrad.Beckmann@amd.com // Always use spill and fill traps 0 1436285Snate@binkert.org // tc->setMiscRegNoEffect(MISCREG_WSTATE, 0); 1446285Snate@binkert.org tc->setIntReg(NumIntArchRegs + 7, 0); 1457039Snate@binkert.org // Set the trap level to 0 1467039Snate@binkert.org tc->setMiscRegNoEffect(MISCREG_TL, 0); 1476285Snate@binkert.org // Set the ASI register to something fixed 14810231Ssteve.reinhardt@amd.com tc->setMiscReg(MISCREG_ASI, ASI_PRIMARY); 1497039Snate@binkert.org 1507039Snate@binkert.org /* 1517039Snate@binkert.org * T1 specific registers 1527039Snate@binkert.org */ 15310231Ssteve.reinhardt@amd.com // Turn on the icache, dcache, dtb translation, and itb translation. 1547915SBrad.Beckmann@amd.com tc->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15); 1557915SBrad.Beckmann@amd.com} 1567915SBrad.Beckmann@amd.com 1577915SBrad.Beckmann@amd.comvoid 1587039Snate@binkert.orgSparc32LiveProcess::initState() 1596285Snate@binkert.org{ 1606285Snate@binkert.org SparcLiveProcess::initState(); 1617039Snate@binkert.org 1627039Snate@binkert.org ThreadContext *tc = system->getThreadContext(contextIds[0]); 1636285Snate@binkert.org // The process runs in user mode with 32 bit addresses 1647039Snate@binkert.org PSTATE pstate = 0; 1656285Snate@binkert.org pstate.ie = 1; 1666285Snate@binkert.org pstate.am = 1; 1677039Snate@binkert.org tc->setMiscReg(MISCREG_PSTATE, pstate); 16810518Snilay@cs.wisc.edu 16910518Snilay@cs.wisc.edu argsInit(32 / 8, PageBytes); 1709104Shestness@cs.utexas.edu} 1719104Shestness@cs.utexas.edu 1729104Shestness@cs.utexas.eduvoid 1739104Shestness@cs.utexas.eduSparc64LiveProcess::initState() 1746876Ssteve.reinhardt@amd.com{ 1756876Ssteve.reinhardt@amd.com SparcLiveProcess::initState(); 1766876Ssteve.reinhardt@amd.com 1776876Ssteve.reinhardt@amd.com ThreadContext *tc = system->getThreadContext(contextIds[0]); 1786876Ssteve.reinhardt@amd.com // The process runs in user mode 179 PSTATE pstate = 0; 180 pstate.ie = 1; 181 tc->setMiscReg(MISCREG_PSTATE, pstate); 182 183 argsInit(sizeof(IntReg), PageBytes); 184} 185 186template<class IntType> 187void 188SparcLiveProcess::argsInit(int pageSize) 189{ 190 int intSize = sizeof(IntType); 191 192 typedef AuxVector<IntType> auxv_t; 193 194 std::vector<auxv_t> auxv; 195 196 string filename; 197 if (argv.size() < 1) 198 filename = ""; 199 else 200 filename = argv[0]; 201 202 // Even for a 32 bit process, the ABI says we still need to 203 // maintain double word alignment of the stack pointer. 204 uint64_t align = 16; 205 206 // Patch the ld_bias for dynamic executables. 207 updateBias(); 208 209 // load object file into target memory 210 objFile->loadSections(initVirtMem); 211 212 enum hardwareCaps 213 { 214 M5_HWCAP_SPARC_FLUSH = 1, 215 M5_HWCAP_SPARC_STBAR = 2, 216 M5_HWCAP_SPARC_SWAP = 4, 217 M5_HWCAP_SPARC_MULDIV = 8, 218 M5_HWCAP_SPARC_V9 = 16, 219 // This one should technically only be set 220 // if there is a cheetah or cheetah_plus tlb, 221 // but we'll use it all the time 222 M5_HWCAP_SPARC_ULTRA3 = 32 223 }; 224 225 const int64_t hwcap = 226 M5_HWCAP_SPARC_FLUSH | 227 M5_HWCAP_SPARC_STBAR | 228 M5_HWCAP_SPARC_SWAP | 229 M5_HWCAP_SPARC_MULDIV | 230 M5_HWCAP_SPARC_V9 | 231 M5_HWCAP_SPARC_ULTRA3; 232 233 // Setup the auxilliary vectors. These will already have endian conversion. 234 // Auxilliary vectors are loaded only for elf formatted executables. 235 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 236 if (elfObject) { 237 // Bits which describe the system hardware capabilities 238 auxv.push_back(auxv_t(M5_AT_HWCAP, hwcap)); 239 // The system page size 240 auxv.push_back(auxv_t(M5_AT_PAGESZ, SparcISA::PageBytes)); 241 // Defined to be 100 in the kernel source. 242 // Frequency at which times() increments 243 auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 244 // For statically linked executables, this is the virtual address of the 245 // program header tables if they appear in the executable image 246 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 247 // This is the size of a program header entry from the elf file. 248 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 249 // This is the number of program headers from the original elf file. 250 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 251 // This is the base address of the ELF interpreter; it should be 252 // zero for static executables or contain the base address for 253 // dynamic executables. 254 auxv.push_back(auxv_t(M5_AT_BASE, getBias())); 255 // This is hardwired to 0 in the elf loading code in the kernel 256 auxv.push_back(auxv_t(M5_AT_FLAGS, 0)); 257 // The entry point to the program 258 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 259 // Different user and group IDs 260 auxv.push_back(auxv_t(M5_AT_UID, uid())); 261 auxv.push_back(auxv_t(M5_AT_EUID, euid())); 262 auxv.push_back(auxv_t(M5_AT_GID, gid())); 263 auxv.push_back(auxv_t(M5_AT_EGID, egid())); 264 // Whether to enable "secure mode" in the executable 265 auxv.push_back(auxv_t(M5_AT_SECURE, 0)); 266 } 267 268 // Figure out how big the initial stack needs to be 269 270 // The unaccounted for 8 byte 0 at the top of the stack 271 int sentry_size = 8; 272 273 // This is the name of the file which is present on the initial stack 274 // It's purpose is to let the user space linker examine the original file. 275 int file_name_size = filename.size() + 1; 276 277 int env_data_size = 0; 278 for (int i = 0; i < envp.size(); ++i) { 279 env_data_size += envp[i].size() + 1; 280 } 281 int arg_data_size = 0; 282 for (int i = 0; i < argv.size(); ++i) { 283 arg_data_size += argv[i].size() + 1; 284 } 285 286 // The info_block. 287 int base_info_block_size = 288 sentry_size + file_name_size + env_data_size + arg_data_size; 289 290 int info_block_size = roundUp(base_info_block_size, align); 291 292 int info_block_padding = info_block_size - base_info_block_size; 293 294 // Each auxilliary vector is two words 295 int aux_array_size = intSize * 2 * (auxv.size() + 1); 296 297 int envp_array_size = intSize * (envp.size() + 1); 298 int argv_array_size = intSize * (argv.size() + 1); 299 300 int argc_size = intSize; 301 int window_save_size = intSize * 16; 302 303 // Figure out the size of the contents of the actual initial frame 304 int frame_size = 305 aux_array_size + 306 envp_array_size + 307 argv_array_size + 308 argc_size + 309 window_save_size; 310 311 // There needs to be padding after the auxiliary vector data so that the 312 // very bottom of the stack is aligned properly. 313 int aligned_partial_size = roundUp(frame_size, align); 314 int aux_padding = aligned_partial_size - frame_size; 315 316 int space_needed = 317 info_block_size + 318 aux_padding + 319 frame_size; 320 321 stack_min = stack_base - space_needed; 322 stack_min = roundDown(stack_min, align); 323 stack_size = stack_base - stack_min; 324 325 // Allocate space for the stack 326 allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize)); 327 328 // map out initial stack contents 329 IntType sentry_base = stack_base - sentry_size; 330 IntType file_name_base = sentry_base - file_name_size; 331 IntType env_data_base = file_name_base - env_data_size; 332 IntType arg_data_base = env_data_base - arg_data_size; 333 IntType auxv_array_base = arg_data_base - 334 info_block_padding - aux_array_size - aux_padding; 335 IntType envp_array_base = auxv_array_base - envp_array_size; 336 IntType argv_array_base = envp_array_base - argv_array_size; 337 IntType argc_base = argv_array_base - argc_size; 338#if TRACING_ON 339 IntType window_save_base = argc_base - window_save_size; 340#endif 341 342 DPRINTF(Stack, "The addresses of items on the initial stack:\n"); 343 DPRINTF(Stack, "%#x - sentry NULL\n", sentry_base); 344 DPRINTF(Stack, "filename = %s\n", filename); 345 DPRINTF(Stack, "%#x - file name\n", file_name_base); 346 DPRINTF(Stack, "%#x - env data\n", env_data_base); 347 DPRINTF(Stack, "%#x - arg data\n", arg_data_base); 348 DPRINTF(Stack, "%#x - auxv array\n", auxv_array_base); 349 DPRINTF(Stack, "%#x - envp array\n", envp_array_base); 350 DPRINTF(Stack, "%#x - argv array\n", argv_array_base); 351 DPRINTF(Stack, "%#x - argc \n", argc_base); 352 DPRINTF(Stack, "%#x - window save\n", window_save_base); 353 DPRINTF(Stack, "%#x - stack min\n", stack_min); 354 355 assert(window_save_base == stack_min); 356 357 // write contents to stack 358 359 // figure out argc 360 IntType argc = argv.size(); 361 IntType guestArgc = SparcISA::htog(argc); 362 363 // Write out the sentry void * 364 uint64_t sentry_NULL = 0; 365 initVirtMem.writeBlob(sentry_base, 366 (uint8_t*)&sentry_NULL, sentry_size); 367 368 // Write the file name 369 initVirtMem.writeString(file_name_base, filename.c_str()); 370 371 // Copy the aux stuff 372 for (int x = 0; x < auxv.size(); x++) { 373 initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize, 374 (uint8_t*)&(auxv[x].a_type), intSize); 375 initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 376 (uint8_t*)&(auxv[x].a_val), intSize); 377 } 378 379 // Write out the terminating zeroed auxilliary vector 380 const IntType zero = 0; 381 initVirtMem.writeBlob(auxv_array_base + intSize * 2 * auxv.size(), 382 (uint8_t*)&zero, intSize); 383 initVirtMem.writeBlob(auxv_array_base + intSize * (2 * auxv.size() + 1), 384 (uint8_t*)&zero, intSize); 385 386 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 387 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 388 389 initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); 390 391 // Set up space for the trap handlers into the processes address space. 392 // Since the stack grows down and there is reserved address space abov 393 // it, we can put stuff above it and stay out of the way. 394 fillStart = stack_base; 395 spillStart = fillStart + sizeof(MachInst) * numFillInsts; 396 397 ThreadContext *tc = system->getThreadContext(contextIds[0]); 398 // Set up the thread context to start running the process 399 // assert(NumArgumentRegs >= 2); 400 // tc->setIntReg(ArgumentReg[0], argc); 401 // tc->setIntReg(ArgumentReg[1], argv_array_base); 402 tc->setIntReg(StackPointerReg, stack_min - StackBias); 403 404 // %g1 is a pointer to a function that should be run at exit. Since we 405 // don't have anything like that, it should be set to 0. 406 tc->setIntReg(1, 0); 407 408 tc->pcState(getStartPC()); 409 410 // Align the "stack_min" to a page boundary. 411 stack_min = roundDown(stack_min, pageSize); 412 413// num_processes++; 414} 415 416void 417Sparc64LiveProcess::argsInit(int intSize, int pageSize) 418{ 419 SparcLiveProcess::argsInit<uint64_t>(pageSize); 420 421 // Stuff the trap handlers into the process address space 422 initVirtMem.writeBlob(fillStart, 423 (uint8_t*)fillHandler64, sizeof(MachInst) * numFillInsts); 424 initVirtMem.writeBlob(spillStart, 425 (uint8_t*)spillHandler64, sizeof(MachInst) * numSpillInsts); 426} 427 428void 429Sparc32LiveProcess::argsInit(int intSize, int pageSize) 430{ 431 SparcLiveProcess::argsInit<uint32_t>(pageSize); 432 433 // Stuff the trap handlers into the process address space 434 initVirtMem.writeBlob(fillStart, 435 (uint8_t*)fillHandler32, sizeof(MachInst) * numFillInsts); 436 initVirtMem.writeBlob(spillStart, 437 (uint8_t*)spillHandler32, sizeof(MachInst) * numSpillInsts); 438} 439 440void Sparc32LiveProcess::flushWindows(ThreadContext *tc) 441{ 442 IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); 443 IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); 444 IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); 445 MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 446 MiscReg origCWP = CWP; 447 CWP = (CWP + Cansave + 2) % NWindows; 448 while (NWindows - 2 - Cansave != 0) { 449 if (Otherwin) { 450 panic("Otherwin non-zero.\n"); 451 } else { 452 tc->setMiscReg(MISCREG_CWP, CWP); 453 // Do the stores 454 IntReg sp = tc->readIntReg(StackPointerReg); 455 for (int index = 16; index < 32; index++) { 456 uint32_t regVal = tc->readIntReg(index); 457 regVal = htog(regVal); 458 if (!tc->getMemProxy().tryWriteBlob( 459 sp + (index - 16) * 4, (uint8_t *)®Val, 4)) { 460 warn("Failed to save register to the stack when " 461 "flushing windows.\n"); 462 } 463 } 464 Canrestore--; 465 Cansave++; 466 CWP = (CWP + 1) % NWindows; 467 } 468 } 469 tc->setIntReg(NumIntArchRegs + 3, Cansave); 470 tc->setIntReg(NumIntArchRegs + 4, Canrestore); 471 tc->setMiscReg(MISCREG_CWP, origCWP); 472} 473 474void 475Sparc64LiveProcess::flushWindows(ThreadContext *tc) 476{ 477 IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); 478 IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); 479 IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); 480 MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 481 MiscReg origCWP = CWP; 482 CWP = (CWP + Cansave + 2) % NWindows; 483 while (NWindows - 2 - Cansave != 0) { 484 if (Otherwin) { 485 panic("Otherwin non-zero.\n"); 486 } else { 487 tc->setMiscReg(MISCREG_CWP, CWP); 488 // Do the stores 489 IntReg sp = tc->readIntReg(StackPointerReg); 490 for (int index = 16; index < 32; index++) { 491 IntReg regVal = tc->readIntReg(index); 492 regVal = htog(regVal); 493 if (!tc->getMemProxy().tryWriteBlob( 494 sp + 2047 + (index - 16) * 8, (uint8_t *)®Val, 8)) { 495 warn("Failed to save register to the stack when " 496 "flushing windows.\n"); 497 } 498 } 499 Canrestore--; 500 Cansave++; 501 CWP = (CWP + 1) % NWindows; 502 } 503 } 504 tc->setIntReg(NumIntArchRegs + 3, Cansave); 505 tc->setIntReg(NumIntArchRegs + 4, Canrestore); 506 tc->setMiscReg(MISCREG_CWP, origCWP); 507} 508 509IntReg 510Sparc32LiveProcess::getSyscallArg(ThreadContext *tc, int &i) 511{ 512 assert(i < 6); 513 return bits(tc->readIntReg(FirstArgumentReg + i++), 31, 0); 514} 515 516void 517Sparc32LiveProcess::setSyscallArg(ThreadContext *tc, int i, IntReg val) 518{ 519 assert(i < 6); 520 tc->setIntReg(FirstArgumentReg + i, bits(val, 31, 0)); 521} 522 523IntReg 524Sparc64LiveProcess::getSyscallArg(ThreadContext *tc, int &i) 525{ 526 assert(i < 6); 527 return tc->readIntReg(FirstArgumentReg + i++); 528} 529 530void 531Sparc64LiveProcess::setSyscallArg(ThreadContext *tc, int i, IntReg val) 532{ 533 assert(i < 6); 534 tc->setIntReg(FirstArgumentReg + i, val); 535} 536 537void 538SparcLiveProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) 539{ 540 // check for error condition. SPARC syscall convention is to 541 // indicate success/failure in reg the carry bit of the ccr 542 // and put the return value itself in the standard return value reg (). 543 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); 544 if (sysret.successful()) { 545 // no error, clear XCC.C 546 tc->setIntReg(NumIntArchRegs + 2, 547 tc->readIntReg(NumIntArchRegs + 2) & 0xEE); 548 IntReg val = sysret.returnValue(); 549 if (pstate.am) 550 val = bits(val, 31, 0); 551 tc->setIntReg(ReturnValueReg, val); 552 } else { 553 // got an error, set XCC.C 554 tc->setIntReg(NumIntArchRegs + 2, 555 tc->readIntReg(NumIntArchRegs + 2) | 0x11); 556 IntReg val = sysret.errnoValue(); 557 if (pstate.am) 558 val = bits(val, 31, 0); 559 tc->setIntReg(ReturnValueReg, val); 560 } 561} 562