process.cc revision 8232
12207SN/A/* 22207SN/A * Copyright (c) 2003-2004 The Regents of The University of Michigan 32207SN/A * All rights reserved. 42207SN/A * 52207SN/A * Redistribution and use in source and binary forms, with or without 62207SN/A * modification, are permitted provided that the following conditions are 72207SN/A * met: redistributions of source code must retain the above copyright 82207SN/A * notice, this list of conditions and the following disclaimer; 92207SN/A * redistributions in binary form must reproduce the above copyright 102207SN/A * notice, this list of conditions and the following disclaimer in the 112207SN/A * documentation and/or other materials provided with the distribution; 122207SN/A * neither the name of the copyright holders nor the names of its 132207SN/A * contributors may be used to endorse or promote products derived from 142207SN/A * this software without specific prior written permission. 152207SN/A * 162207SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172207SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182207SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192207SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202207SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212207SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222207SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232207SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242207SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252207SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262207SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Gabe Black 292665Ssaidi@eecs.umich.edu * Ali Saidi 302207SN/A */ 312207SN/A 323589Sgblack@eecs.umich.edu#include "arch/sparc/asi.hh" 334111Sgblack@eecs.umich.edu#include "arch/sparc/handlers.hh" 342474SN/A#include "arch/sparc/isa_traits.hh" 358229Snate@binkert.org#include "arch/sparc/process.hh" 366335Sgblack@eecs.umich.edu#include "arch/sparc/registers.hh" 373760Sgblack@eecs.umich.edu#include "arch/sparc/types.hh" 388229Snate@binkert.org#include "base/loader/elf_object.hh" 392454SN/A#include "base/loader/object_file.hh" 402454SN/A#include "base/misc.hh" 412680Sktlim@umich.edu#include "cpu/thread_context.hh" 428232Snate@binkert.org#include "debug/Stack.hh" 432561SN/A#include "mem/page_table.hh" 448229Snate@binkert.org#include "mem/translating_port.hh" 454434Ssaidi@eecs.umich.edu#include "sim/process_impl.hh" 462474SN/A#include "sim/system.hh" 472207SN/A 482458SN/Ausing namespace std; 492474SN/Ausing namespace SparcISA; 502458SN/A 515958Sgblack@eecs.umich.edustatic const int FirstArgumentReg = 8; 525958Sgblack@eecs.umich.edu 532207SN/A 545154Sgblack@eecs.umich.eduSparcLiveProcess::SparcLiveProcess(LiveProcessParams * params, 555285Sgblack@eecs.umich.edu ObjectFile *objFile, Addr _StackBias) 565285Sgblack@eecs.umich.edu : LiveProcess(params, objFile), StackBias(_StackBias) 572474SN/A{ 582474SN/A 592474SN/A // XXX all the below need to be updated for SPARC - Ali 602474SN/A brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); 612474SN/A brk_point = roundUp(brk_point, VMPageSize); 622474SN/A 632474SN/A // Set pointer for next thread stack. Reserve 8M for main stack. 642474SN/A next_thread_stack_base = stack_base - (8 * 1024 * 1024); 653415Sgblack@eecs.umich.edu 667741Sgblack@eecs.umich.edu // Initialize these to 0s 673415Sgblack@eecs.umich.edu fillStart = 0; 683415Sgblack@eecs.umich.edu spillStart = 0; 692474SN/A} 702474SN/A 717741Sgblack@eecs.umich.eduvoid 727741Sgblack@eecs.umich.eduSparcLiveProcess::handleTrap(int trapNum, ThreadContext *tc) 734111Sgblack@eecs.umich.edu{ 747720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 757741Sgblack@eecs.umich.edu switch (trapNum) { 767741Sgblack@eecs.umich.edu case 0x01: // Software breakpoint 777720Sgblack@eecs.umich.edu warn("Software breakpoint encountered at pc %#x.\n", pc.pc()); 785128Sgblack@eecs.umich.edu break; 797741Sgblack@eecs.umich.edu case 0x02: // Division by zero 807720Sgblack@eecs.umich.edu warn("Software signaled a division by zero at pc %#x.\n", pc.pc()); 815128Sgblack@eecs.umich.edu break; 827741Sgblack@eecs.umich.edu case 0x03: // Flush window trap 835128Sgblack@eecs.umich.edu flushWindows(tc); 845128Sgblack@eecs.umich.edu break; 857741Sgblack@eecs.umich.edu case 0x04: // Clean windows 865128Sgblack@eecs.umich.edu warn("Ignoring process request for clean register " 877720Sgblack@eecs.umich.edu "windows at pc %#x.\n", pc.pc()); 885128Sgblack@eecs.umich.edu break; 897741Sgblack@eecs.umich.edu case 0x05: // Range check 907720Sgblack@eecs.umich.edu warn("Software signaled a range check at pc %#x.\n", pc.pc()); 915128Sgblack@eecs.umich.edu break; 927741Sgblack@eecs.umich.edu case 0x06: // Fix alignment 935128Sgblack@eecs.umich.edu warn("Ignoring process request for os assisted unaligned accesses " 947720Sgblack@eecs.umich.edu "at pc %#x.\n", pc.pc()); 955128Sgblack@eecs.umich.edu break; 967741Sgblack@eecs.umich.edu case 0x07: // Integer overflow 977720Sgblack@eecs.umich.edu warn("Software signaled an integer overflow at pc %#x.\n", pc.pc()); 985128Sgblack@eecs.umich.edu break; 997741Sgblack@eecs.umich.edu case 0x32: // Get integer condition codes 1005128Sgblack@eecs.umich.edu warn("Ignoring process request to get the integer condition codes " 1017720Sgblack@eecs.umich.edu "at pc %#x.\n", pc.pc()); 1025128Sgblack@eecs.umich.edu break; 1037741Sgblack@eecs.umich.edu case 0x33: // Set integer condition codes 1045128Sgblack@eecs.umich.edu warn("Ignoring process request to set the integer condition codes " 1057720Sgblack@eecs.umich.edu "at pc %#x.\n", pc.pc()); 1064111Sgblack@eecs.umich.edu break; 1074111Sgblack@eecs.umich.edu default: 1084111Sgblack@eecs.umich.edu panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum); 1094111Sgblack@eecs.umich.edu } 1104111Sgblack@eecs.umich.edu} 1114111Sgblack@eecs.umich.edu 1122474SN/Avoid 1137532Ssteve.reinhardt@amd.comSparcLiveProcess::initState() 1144111Sgblack@eecs.umich.edu{ 1157532Ssteve.reinhardt@amd.com LiveProcess::initState(); 1164111Sgblack@eecs.umich.edu 1175713Shsul@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 1187741Sgblack@eecs.umich.edu // From the SPARC ABI 1194111Sgblack@eecs.umich.edu 1207741Sgblack@eecs.umich.edu // Setup default FP state 1215713Shsul@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_FSR, 0); 1222646Ssaidi@eecs.umich.edu 1235713Shsul@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TICK, 0); 1244997Sgblack@eecs.umich.edu 1252561SN/A /* 1262561SN/A * Register window management registers 1272561SN/A */ 1282561SN/A 1297741Sgblack@eecs.umich.edu // No windows contain info from other programs 1307741Sgblack@eecs.umich.edu // tc->setMiscRegNoEffect(MISCREG_OTHERWIN, 0); 1315713Shsul@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 6, 0); 1327741Sgblack@eecs.umich.edu // There are no windows to pop 1337741Sgblack@eecs.umich.edu // tc->setMiscRegNoEffect(MISCREG_CANRESTORE, 0); 1345713Shsul@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 4, 0); 1357741Sgblack@eecs.umich.edu // All windows are available to save into 1367741Sgblack@eecs.umich.edu // tc->setMiscRegNoEffect(MISCREG_CANSAVE, NWindows - 2); 1375713Shsul@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 3, NWindows - 2); 1387741Sgblack@eecs.umich.edu // All windows are "clean" 1397741Sgblack@eecs.umich.edu // tc->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows); 1405713Shsul@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 5, NWindows); 1417741Sgblack@eecs.umich.edu // Start with register window 0 1426337Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, 0); 1437741Sgblack@eecs.umich.edu // Always use spill and fill traps 0 1447741Sgblack@eecs.umich.edu // tc->setMiscRegNoEffect(MISCREG_WSTATE, 0); 1455713Shsul@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 7, 0); 1467741Sgblack@eecs.umich.edu // Set the trap level to 0 1475713Shsul@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TL, 0); 1487741Sgblack@eecs.umich.edu // Set the ASI register to something fixed 1495713Shsul@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY); 1504997Sgblack@eecs.umich.edu 1514997Sgblack@eecs.umich.edu /* 1524997Sgblack@eecs.umich.edu * T1 specific registers 1534997Sgblack@eecs.umich.edu */ 1547741Sgblack@eecs.umich.edu // Turn on the icache, dcache, dtb translation, and itb translation. 1555713Shsul@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15); 1562474SN/A} 1572474SN/A 1585285Sgblack@eecs.umich.eduvoid 1597532Ssteve.reinhardt@amd.comSparc32LiveProcess::initState() 1602585SN/A{ 1617532Ssteve.reinhardt@amd.com SparcLiveProcess::initState(); 1625285Sgblack@eecs.umich.edu 1635713Shsul@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 1647741Sgblack@eecs.umich.edu // The process runs in user mode with 32 bit addresses 1655713Shsul@eecs.umich.edu tc->setMiscReg(MISCREG_PSTATE, 0x0a); 1665285Sgblack@eecs.umich.edu 1675285Sgblack@eecs.umich.edu argsInit(32 / 8, VMPageSize); 1684111Sgblack@eecs.umich.edu} 1693415Sgblack@eecs.umich.edu 1702561SN/Avoid 1717532Ssteve.reinhardt@amd.comSparc64LiveProcess::initState() 1722561SN/A{ 1737532Ssteve.reinhardt@amd.com SparcLiveProcess::initState(); 1745285Sgblack@eecs.umich.edu 1755713Shsul@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 1767741Sgblack@eecs.umich.edu // The process runs in user mode 1775713Shsul@eecs.umich.edu tc->setMiscReg(MISCREG_PSTATE, 0x02); 1785285Sgblack@eecs.umich.edu 1795285Sgblack@eecs.umich.edu argsInit(sizeof(IntReg), VMPageSize); 1805285Sgblack@eecs.umich.edu} 1815285Sgblack@eecs.umich.edu 1825285Sgblack@eecs.umich.edutemplate<class IntType> 1835285Sgblack@eecs.umich.eduvoid 1845285Sgblack@eecs.umich.eduSparcLiveProcess::argsInit(int pageSize) 1855285Sgblack@eecs.umich.edu{ 1865285Sgblack@eecs.umich.edu int intSize = sizeof(IntType); 1875285Sgblack@eecs.umich.edu 1885771Shsul@eecs.umich.edu typedef AuxVector<IntType> auxv_t; 1895285Sgblack@eecs.umich.edu 1905285Sgblack@eecs.umich.edu std::vector<auxv_t> auxv; 1912474SN/A 1923044Sgblack@eecs.umich.edu string filename; 1937741Sgblack@eecs.umich.edu if (argv.size() < 1) 1943044Sgblack@eecs.umich.edu filename = ""; 1953044Sgblack@eecs.umich.edu else 1963044Sgblack@eecs.umich.edu filename = argv[0]; 1973044Sgblack@eecs.umich.edu 1987741Sgblack@eecs.umich.edu // Even for a 32 bit process, the ABI says we still need to 1997741Sgblack@eecs.umich.edu // maintain double word alignment of the stack pointer. 2005286Sgblack@eecs.umich.edu uint64_t align = 16; 2012561SN/A 2022561SN/A // load object file into target memory 2032561SN/A objFile->loadSections(initVirtMem); 2042561SN/A 2052585SN/A enum hardwareCaps 2062585SN/A { 2072585SN/A M5_HWCAP_SPARC_FLUSH = 1, 2082585SN/A M5_HWCAP_SPARC_STBAR = 2, 2092585SN/A M5_HWCAP_SPARC_SWAP = 4, 2102585SN/A M5_HWCAP_SPARC_MULDIV = 8, 2112585SN/A M5_HWCAP_SPARC_V9 = 16, 2127741Sgblack@eecs.umich.edu // This one should technically only be set 2137741Sgblack@eecs.umich.edu // if there is a cheetah or cheetah_plus tlb, 2147741Sgblack@eecs.umich.edu // but we'll use it all the time 2152585SN/A M5_HWCAP_SPARC_ULTRA3 = 32 2162585SN/A }; 2172585SN/A 2182585SN/A const int64_t hwcap = 2192585SN/A M5_HWCAP_SPARC_FLUSH | 2202585SN/A M5_HWCAP_SPARC_STBAR | 2212585SN/A M5_HWCAP_SPARC_SWAP | 2222585SN/A M5_HWCAP_SPARC_MULDIV | 2232585SN/A M5_HWCAP_SPARC_V9 | 2242585SN/A M5_HWCAP_SPARC_ULTRA3; 2252585SN/A 2267741Sgblack@eecs.umich.edu // Setup the auxilliary vectors. These will already have endian conversion. 2277741Sgblack@eecs.umich.edu // Auxilliary vectors are loaded only for elf formatted executables. 2282976Sgblack@eecs.umich.edu ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 2297741Sgblack@eecs.umich.edu if (elfObject) { 2307741Sgblack@eecs.umich.edu // Bits which describe the system hardware capabilities 2314793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_HWCAP, hwcap)); 2327741Sgblack@eecs.umich.edu // The system page size 2334793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PAGESZ, SparcISA::VMPageSize)); 2347741Sgblack@eecs.umich.edu // Defined to be 100 in the kernel source. 2357741Sgblack@eecs.umich.edu // Frequency at which times() increments 2364793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 2372976Sgblack@eecs.umich.edu // For statically linked executables, this is the virtual address of the 2382976Sgblack@eecs.umich.edu // program header tables if they appear in the executable image 2394793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 2402976Sgblack@eecs.umich.edu // This is the size of a program header entry from the elf file. 2414793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 2422976Sgblack@eecs.umich.edu // This is the number of program headers from the original elf file. 2434793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 2447741Sgblack@eecs.umich.edu // This is the address of the elf "interpreter", It should be set 2457741Sgblack@eecs.umich.edu // to 0 for regular executables. It should be something else 2467741Sgblack@eecs.umich.edu // (not sure what) for dynamic libraries. 2474793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_BASE, 0)); 2487741Sgblack@eecs.umich.edu // This is hardwired to 0 in the elf loading code in the kernel 2494793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_FLAGS, 0)); 2507741Sgblack@eecs.umich.edu // The entry point to the program 2514793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 2527741Sgblack@eecs.umich.edu // Different user and group IDs 2534793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_UID, uid())); 2544793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_EUID, euid())); 2554793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_GID, gid())); 2564793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_EGID, egid())); 2577741Sgblack@eecs.umich.edu // Whether to enable "secure mode" in the executable 2584793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_SECURE, 0)); 2592976Sgblack@eecs.umich.edu } 2602585SN/A 2617741Sgblack@eecs.umich.edu // Figure out how big the initial stack needs to be 2622561SN/A 2634164Sgblack@eecs.umich.edu // The unaccounted for 8 byte 0 at the top of the stack 2645286Sgblack@eecs.umich.edu int sentry_size = 8; 2654111Sgblack@eecs.umich.edu 2667741Sgblack@eecs.umich.edu // This is the name of the file which is present on the initial stack 2677741Sgblack@eecs.umich.edu // It's purpose is to let the user space linker examine the original file. 2684111Sgblack@eecs.umich.edu int file_name_size = filename.size() + 1; 2694111Sgblack@eecs.umich.edu 2704111Sgblack@eecs.umich.edu int env_data_size = 0; 2714111Sgblack@eecs.umich.edu for (int i = 0; i < envp.size(); ++i) { 2724111Sgblack@eecs.umich.edu env_data_size += envp[i].size() + 1; 2734111Sgblack@eecs.umich.edu } 2744111Sgblack@eecs.umich.edu int arg_data_size = 0; 2754111Sgblack@eecs.umich.edu for (int i = 0; i < argv.size(); ++i) { 2764111Sgblack@eecs.umich.edu arg_data_size += argv[i].size() + 1; 2774111Sgblack@eecs.umich.edu } 2784111Sgblack@eecs.umich.edu 2797741Sgblack@eecs.umich.edu // The info_block. 2805286Sgblack@eecs.umich.edu int base_info_block_size = 2815286Sgblack@eecs.umich.edu sentry_size + file_name_size + env_data_size + arg_data_size; 2825286Sgblack@eecs.umich.edu 2835286Sgblack@eecs.umich.edu int info_block_size = roundUp(base_info_block_size, align); 2845286Sgblack@eecs.umich.edu 2855286Sgblack@eecs.umich.edu int info_block_padding = info_block_size - base_info_block_size; 2864111Sgblack@eecs.umich.edu 2877741Sgblack@eecs.umich.edu // Each auxilliary vector is two words 2884111Sgblack@eecs.umich.edu int aux_array_size = intSize * 2 * (auxv.size() + 1); 2894111Sgblack@eecs.umich.edu 2904111Sgblack@eecs.umich.edu int envp_array_size = intSize * (envp.size() + 1); 2914111Sgblack@eecs.umich.edu int argv_array_size = intSize * (argv.size() + 1); 2924111Sgblack@eecs.umich.edu 2934111Sgblack@eecs.umich.edu int argc_size = intSize; 2944111Sgblack@eecs.umich.edu int window_save_size = intSize * 16; 2954111Sgblack@eecs.umich.edu 2967741Sgblack@eecs.umich.edu // Figure out the size of the contents of the actual initial frame 2975286Sgblack@eecs.umich.edu int frame_size = 2984111Sgblack@eecs.umich.edu aux_array_size + 2994111Sgblack@eecs.umich.edu envp_array_size + 3004111Sgblack@eecs.umich.edu argv_array_size + 3014111Sgblack@eecs.umich.edu argc_size + 3024111Sgblack@eecs.umich.edu window_save_size; 3034111Sgblack@eecs.umich.edu 3047741Sgblack@eecs.umich.edu // There needs to be padding after the auxiliary vector data so that the 3057741Sgblack@eecs.umich.edu // very bottom of the stack is aligned properly. 3065286Sgblack@eecs.umich.edu int aligned_partial_size = roundUp(frame_size, align); 3075286Sgblack@eecs.umich.edu int aux_padding = aligned_partial_size - frame_size; 3085286Sgblack@eecs.umich.edu 3095286Sgblack@eecs.umich.edu int space_needed = 3105286Sgblack@eecs.umich.edu info_block_size + 3115286Sgblack@eecs.umich.edu aux_padding + 3125286Sgblack@eecs.umich.edu frame_size; 3135286Sgblack@eecs.umich.edu 3144111Sgblack@eecs.umich.edu stack_min = stack_base - space_needed; 3155286Sgblack@eecs.umich.edu stack_min = roundDown(stack_min, align); 3164111Sgblack@eecs.umich.edu stack_size = stack_base - stack_min; 3174111Sgblack@eecs.umich.edu 3185285Sgblack@eecs.umich.edu // Allocate space for the stack 3194111Sgblack@eecs.umich.edu pTable->allocate(roundDown(stack_min, pageSize), 3204111Sgblack@eecs.umich.edu roundUp(stack_size, pageSize)); 3214111Sgblack@eecs.umich.edu 3224111Sgblack@eecs.umich.edu // map out initial stack contents 3235286Sgblack@eecs.umich.edu IntType sentry_base = stack_base - sentry_size; 3245286Sgblack@eecs.umich.edu IntType file_name_base = sentry_base - file_name_size; 3255286Sgblack@eecs.umich.edu IntType env_data_base = file_name_base - env_data_size; 3265286Sgblack@eecs.umich.edu IntType arg_data_base = env_data_base - arg_data_size; 3275286Sgblack@eecs.umich.edu IntType auxv_array_base = arg_data_base - 3285286Sgblack@eecs.umich.edu info_block_padding - aux_array_size - aux_padding; 3295286Sgblack@eecs.umich.edu IntType envp_array_base = auxv_array_base - envp_array_size; 3305286Sgblack@eecs.umich.edu IntType argv_array_base = envp_array_base - argv_array_size; 3315286Sgblack@eecs.umich.edu IntType argc_base = argv_array_base - argc_size; 3325286Sgblack@eecs.umich.edu#if TRACING_ON 3335286Sgblack@eecs.umich.edu IntType window_save_base = argc_base - window_save_size; 3345286Sgblack@eecs.umich.edu#endif 3354111Sgblack@eecs.umich.edu 3365941Sgblack@eecs.umich.edu DPRINTF(Stack, "The addresses of items on the initial stack:\n"); 3375941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - sentry NULL\n", sentry_base); 3385941Sgblack@eecs.umich.edu DPRINTF(Stack, "filename = %s\n", filename); 3395941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - file name\n", file_name_base); 3405941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - env data\n", env_data_base); 3415941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - arg data\n", arg_data_base); 3425941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - auxv array\n", auxv_array_base); 3435941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - envp array\n", envp_array_base); 3445941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - argv array\n", argv_array_base); 3455941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - argc \n", argc_base); 3465941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - window save\n", window_save_base); 3475941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - stack min\n", stack_min); 3484111Sgblack@eecs.umich.edu 3495286Sgblack@eecs.umich.edu assert(window_save_base == stack_min); 3505286Sgblack@eecs.umich.edu 3514111Sgblack@eecs.umich.edu // write contents to stack 3524111Sgblack@eecs.umich.edu 3534111Sgblack@eecs.umich.edu // figure out argc 3545285Sgblack@eecs.umich.edu IntType argc = argv.size(); 3555567Snate@binkert.org IntType guestArgc = SparcISA::htog(argc); 3564111Sgblack@eecs.umich.edu 3577741Sgblack@eecs.umich.edu // Write out the sentry void * 3585286Sgblack@eecs.umich.edu uint64_t sentry_NULL = 0; 3595286Sgblack@eecs.umich.edu initVirtMem->writeBlob(sentry_base, 3605286Sgblack@eecs.umich.edu (uint8_t*)&sentry_NULL, sentry_size); 3614111Sgblack@eecs.umich.edu 3627741Sgblack@eecs.umich.edu // Write the file name 3634111Sgblack@eecs.umich.edu initVirtMem->writeString(file_name_base, filename.c_str()); 3644111Sgblack@eecs.umich.edu 3657741Sgblack@eecs.umich.edu // Copy the aux stuff 3667741Sgblack@eecs.umich.edu for (int x = 0; x < auxv.size(); x++) { 3674111Sgblack@eecs.umich.edu initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize, 3684111Sgblack@eecs.umich.edu (uint8_t*)&(auxv[x].a_type), intSize); 3694111Sgblack@eecs.umich.edu initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 3704111Sgblack@eecs.umich.edu (uint8_t*)&(auxv[x].a_val), intSize); 3714111Sgblack@eecs.umich.edu } 3725285Sgblack@eecs.umich.edu 3737741Sgblack@eecs.umich.edu // Write out the terminating zeroed auxilliary vector 3745285Sgblack@eecs.umich.edu const IntType zero = 0; 3755286Sgblack@eecs.umich.edu initVirtMem->writeBlob(auxv_array_base + intSize * 2 * auxv.size(), 3765286Sgblack@eecs.umich.edu (uint8_t*)&zero, intSize); 3775286Sgblack@eecs.umich.edu initVirtMem->writeBlob(auxv_array_base + intSize * (2 * auxv.size() + 1), 3785286Sgblack@eecs.umich.edu (uint8_t*)&zero, intSize); 3794111Sgblack@eecs.umich.edu 3804117Sgblack@eecs.umich.edu copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 3814117Sgblack@eecs.umich.edu copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 3824111Sgblack@eecs.umich.edu 3834111Sgblack@eecs.umich.edu initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); 3844111Sgblack@eecs.umich.edu 3857741Sgblack@eecs.umich.edu // Set up space for the trap handlers into the processes address space. 3867741Sgblack@eecs.umich.edu // Since the stack grows down and there is reserved address space abov 3877741Sgblack@eecs.umich.edu // it, we can put stuff above it and stay out of the way. 3884111Sgblack@eecs.umich.edu fillStart = stack_base; 3895285Sgblack@eecs.umich.edu spillStart = fillStart + sizeof(MachInst) * numFillInsts; 3904111Sgblack@eecs.umich.edu 3915713Shsul@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 3927741Sgblack@eecs.umich.edu // Set up the thread context to start running the process 3937741Sgblack@eecs.umich.edu // assert(NumArgumentRegs >= 2); 3947741Sgblack@eecs.umich.edu // tc->setIntReg(ArgumentReg[0], argc); 3957741Sgblack@eecs.umich.edu // tc->setIntReg(ArgumentReg[1], argv_array_base); 3965713Shsul@eecs.umich.edu tc->setIntReg(StackPointerReg, stack_min - StackBias); 3974111Sgblack@eecs.umich.edu 3985231Sgblack@eecs.umich.edu // %g1 is a pointer to a function that should be run at exit. Since we 3995231Sgblack@eecs.umich.edu // don't have anything like that, it should be set to 0. 4005713Shsul@eecs.umich.edu tc->setIntReg(1, 0); 4015231Sgblack@eecs.umich.edu 4027720Sgblack@eecs.umich.edu tc->pcState(objFile->entryPoint()); 4034111Sgblack@eecs.umich.edu 4047741Sgblack@eecs.umich.edu // Align the "stack_min" to a page boundary. 4054111Sgblack@eecs.umich.edu stack_min = roundDown(stack_min, pageSize); 4064111Sgblack@eecs.umich.edu 4074111Sgblack@eecs.umich.edu// num_processes++; 4084111Sgblack@eecs.umich.edu} 4095128Sgblack@eecs.umich.edu 4105285Sgblack@eecs.umich.eduvoid 4115285Sgblack@eecs.umich.eduSparc64LiveProcess::argsInit(int intSize, int pageSize) 4125285Sgblack@eecs.umich.edu{ 4135285Sgblack@eecs.umich.edu SparcLiveProcess::argsInit<uint64_t>(pageSize); 4145285Sgblack@eecs.umich.edu 4155285Sgblack@eecs.umich.edu // Stuff the trap handlers into the process address space 4165285Sgblack@eecs.umich.edu initVirtMem->writeBlob(fillStart, 4175285Sgblack@eecs.umich.edu (uint8_t*)fillHandler64, sizeof(MachInst) * numFillInsts); 4185285Sgblack@eecs.umich.edu initVirtMem->writeBlob(spillStart, 4195285Sgblack@eecs.umich.edu (uint8_t*)spillHandler64, sizeof(MachInst) * numSpillInsts); 4205285Sgblack@eecs.umich.edu} 4215285Sgblack@eecs.umich.edu 4225285Sgblack@eecs.umich.eduvoid 4235285Sgblack@eecs.umich.eduSparc32LiveProcess::argsInit(int intSize, int pageSize) 4245285Sgblack@eecs.umich.edu{ 4255285Sgblack@eecs.umich.edu SparcLiveProcess::argsInit<uint32_t>(pageSize); 4265285Sgblack@eecs.umich.edu 4275285Sgblack@eecs.umich.edu // Stuff the trap handlers into the process address space 4285285Sgblack@eecs.umich.edu initVirtMem->writeBlob(fillStart, 4295285Sgblack@eecs.umich.edu (uint8_t*)fillHandler32, sizeof(MachInst) * numFillInsts); 4305285Sgblack@eecs.umich.edu initVirtMem->writeBlob(spillStart, 4315285Sgblack@eecs.umich.edu (uint8_t*)spillHandler32, sizeof(MachInst) * numSpillInsts); 4325285Sgblack@eecs.umich.edu} 4335285Sgblack@eecs.umich.edu 4345128Sgblack@eecs.umich.eduvoid Sparc32LiveProcess::flushWindows(ThreadContext *tc) 4355128Sgblack@eecs.umich.edu{ 4365128Sgblack@eecs.umich.edu IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); 4375128Sgblack@eecs.umich.edu IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); 4385128Sgblack@eecs.umich.edu IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); 4395128Sgblack@eecs.umich.edu MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 4405128Sgblack@eecs.umich.edu MiscReg origCWP = CWP; 4415128Sgblack@eecs.umich.edu CWP = (CWP + Cansave + 2) % NWindows; 4427741Sgblack@eecs.umich.edu while (NWindows - 2 - Cansave != 0) { 4435128Sgblack@eecs.umich.edu if (Otherwin) { 4445128Sgblack@eecs.umich.edu panic("Otherwin non-zero.\n"); 4455128Sgblack@eecs.umich.edu } else { 4465128Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, CWP); 4477741Sgblack@eecs.umich.edu // Do the stores 4485128Sgblack@eecs.umich.edu IntReg sp = tc->readIntReg(StackPointerReg); 4495128Sgblack@eecs.umich.edu for (int index = 16; index < 32; index++) { 4505287Sgblack@eecs.umich.edu uint32_t regVal = tc->readIntReg(index); 4515128Sgblack@eecs.umich.edu regVal = htog(regVal); 4525128Sgblack@eecs.umich.edu if (!tc->getMemPort()->tryWriteBlob( 4535128Sgblack@eecs.umich.edu sp + (index - 16) * 4, (uint8_t *)®Val, 4)) { 4545128Sgblack@eecs.umich.edu warn("Failed to save register to the stack when " 4555128Sgblack@eecs.umich.edu "flushing windows.\n"); 4565128Sgblack@eecs.umich.edu } 4575128Sgblack@eecs.umich.edu } 4585128Sgblack@eecs.umich.edu Canrestore--; 4595128Sgblack@eecs.umich.edu Cansave++; 4605128Sgblack@eecs.umich.edu CWP = (CWP + 1) % NWindows; 4615128Sgblack@eecs.umich.edu } 4625128Sgblack@eecs.umich.edu } 4635128Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 3, Cansave); 4645128Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 4, Canrestore); 4655128Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, origCWP); 4665128Sgblack@eecs.umich.edu} 4675128Sgblack@eecs.umich.edu 4687741Sgblack@eecs.umich.eduvoid 4697741Sgblack@eecs.umich.eduSparc64LiveProcess::flushWindows(ThreadContext *tc) 4705128Sgblack@eecs.umich.edu{ 4715128Sgblack@eecs.umich.edu IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); 4725128Sgblack@eecs.umich.edu IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); 4735128Sgblack@eecs.umich.edu IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); 4745128Sgblack@eecs.umich.edu MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 4755128Sgblack@eecs.umich.edu MiscReg origCWP = CWP; 4765128Sgblack@eecs.umich.edu CWP = (CWP + Cansave + 2) % NWindows; 4777741Sgblack@eecs.umich.edu while (NWindows - 2 - Cansave != 0) { 4785128Sgblack@eecs.umich.edu if (Otherwin) { 4795128Sgblack@eecs.umich.edu panic("Otherwin non-zero.\n"); 4805128Sgblack@eecs.umich.edu } else { 4815128Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, CWP); 4827741Sgblack@eecs.umich.edu // Do the stores 4835128Sgblack@eecs.umich.edu IntReg sp = tc->readIntReg(StackPointerReg); 4845128Sgblack@eecs.umich.edu for (int index = 16; index < 32; index++) { 4855128Sgblack@eecs.umich.edu IntReg regVal = tc->readIntReg(index); 4865128Sgblack@eecs.umich.edu regVal = htog(regVal); 4875128Sgblack@eecs.umich.edu if (!tc->getMemPort()->tryWriteBlob( 4885128Sgblack@eecs.umich.edu sp + 2047 + (index - 16) * 8, (uint8_t *)®Val, 8)) { 4895128Sgblack@eecs.umich.edu warn("Failed to save register to the stack when " 4905128Sgblack@eecs.umich.edu "flushing windows.\n"); 4915128Sgblack@eecs.umich.edu } 4925128Sgblack@eecs.umich.edu } 4935128Sgblack@eecs.umich.edu Canrestore--; 4945128Sgblack@eecs.umich.edu Cansave++; 4955128Sgblack@eecs.umich.edu CWP = (CWP + 1) % NWindows; 4965128Sgblack@eecs.umich.edu } 4975128Sgblack@eecs.umich.edu } 4985128Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 3, Cansave); 4995128Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 4, Canrestore); 5005128Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, origCWP); 5015128Sgblack@eecs.umich.edu} 5025958Sgblack@eecs.umich.edu 5035958Sgblack@eecs.umich.eduIntReg 5046701Sgblack@eecs.umich.eduSparc32LiveProcess::getSyscallArg(ThreadContext *tc, int &i) 5055958Sgblack@eecs.umich.edu{ 5065958Sgblack@eecs.umich.edu assert(i < 6); 5076701Sgblack@eecs.umich.edu return bits(tc->readIntReg(FirstArgumentReg + i++), 31, 0); 5085958Sgblack@eecs.umich.edu} 5095958Sgblack@eecs.umich.edu 5105958Sgblack@eecs.umich.eduvoid 5115958Sgblack@eecs.umich.eduSparc32LiveProcess::setSyscallArg(ThreadContext *tc, int i, IntReg val) 5125958Sgblack@eecs.umich.edu{ 5135958Sgblack@eecs.umich.edu assert(i < 6); 5145958Sgblack@eecs.umich.edu tc->setIntReg(FirstArgumentReg + i, bits(val, 31, 0)); 5155958Sgblack@eecs.umich.edu} 5165958Sgblack@eecs.umich.edu 5175958Sgblack@eecs.umich.eduIntReg 5186701Sgblack@eecs.umich.eduSparc64LiveProcess::getSyscallArg(ThreadContext *tc, int &i) 5195958Sgblack@eecs.umich.edu{ 5205958Sgblack@eecs.umich.edu assert(i < 6); 5216701Sgblack@eecs.umich.edu return tc->readIntReg(FirstArgumentReg + i++); 5225958Sgblack@eecs.umich.edu} 5235958Sgblack@eecs.umich.edu 5245958Sgblack@eecs.umich.eduvoid 5255958Sgblack@eecs.umich.eduSparc64LiveProcess::setSyscallArg(ThreadContext *tc, int i, IntReg val) 5265958Sgblack@eecs.umich.edu{ 5275958Sgblack@eecs.umich.edu assert(i < 6); 5285958Sgblack@eecs.umich.edu tc->setIntReg(FirstArgumentReg + i, val); 5295958Sgblack@eecs.umich.edu} 5305958Sgblack@eecs.umich.edu 5315958Sgblack@eecs.umich.eduvoid 5325958Sgblack@eecs.umich.eduSparcLiveProcess::setSyscallReturn(ThreadContext *tc, 5335958Sgblack@eecs.umich.edu SyscallReturn return_value) 5345958Sgblack@eecs.umich.edu{ 5355958Sgblack@eecs.umich.edu // check for error condition. SPARC syscall convention is to 5365958Sgblack@eecs.umich.edu // indicate success/failure in reg the carry bit of the ccr 5375958Sgblack@eecs.umich.edu // and put the return value itself in the standard return value reg (). 5385958Sgblack@eecs.umich.edu if (return_value.successful()) { 5395958Sgblack@eecs.umich.edu // no error, clear XCC.C 5405958Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 2, 5415958Sgblack@eecs.umich.edu tc->readIntReg(NumIntArchRegs + 2) & 0xEE); 5427741Sgblack@eecs.umich.edu // tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) & 0xEE); 5435958Sgblack@eecs.umich.edu IntReg val = return_value.value(); 5445958Sgblack@eecs.umich.edu if (bits(tc->readMiscRegNoEffect( 5455958Sgblack@eecs.umich.edu SparcISA::MISCREG_PSTATE), 3, 3)) { 5465958Sgblack@eecs.umich.edu val = bits(val, 31, 0); 5475958Sgblack@eecs.umich.edu } 5485958Sgblack@eecs.umich.edu tc->setIntReg(ReturnValueReg, val); 5495958Sgblack@eecs.umich.edu } else { 5505958Sgblack@eecs.umich.edu // got an error, set XCC.C 5515958Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 2, 5525958Sgblack@eecs.umich.edu tc->readIntReg(NumIntArchRegs + 2) | 0x11); 5537741Sgblack@eecs.umich.edu // tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) | 0x11); 5545958Sgblack@eecs.umich.edu IntReg val = -return_value.value(); 5555958Sgblack@eecs.umich.edu if (bits(tc->readMiscRegNoEffect( 5565958Sgblack@eecs.umich.edu SparcISA::MISCREG_PSTATE), 3, 3)) { 5575958Sgblack@eecs.umich.edu val = bits(val, 31, 0); 5585958Sgblack@eecs.umich.edu } 5595958Sgblack@eecs.umich.edu tc->setIntReg(ReturnValueReg, val); 5605958Sgblack@eecs.umich.edu } 5615958Sgblack@eecs.umich.edu} 562