process.cc revision 12431
12207SN/A/* 22207SN/A * Copyright (c) 2003-2004 The Regents of The University of Michigan 32207SN/A * All rights reserved. 42207SN/A * 52207SN/A * Redistribution and use in source and binary forms, with or without 62207SN/A * modification, are permitted provided that the following conditions are 72207SN/A * met: redistributions of source code must retain the above copyright 82207SN/A * notice, this list of conditions and the following disclaimer; 92207SN/A * redistributions in binary form must reproduce the above copyright 102207SN/A * notice, this list of conditions and the following disclaimer in the 112207SN/A * documentation and/or other materials provided with the distribution; 122207SN/A * neither the name of the copyright holders nor the names of its 132207SN/A * contributors may be used to endorse or promote products derived from 142207SN/A * this software without specific prior written permission. 152207SN/A * 162207SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172207SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182207SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192207SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202207SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212207SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222207SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232207SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242207SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252207SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262207SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Gabe Black 292665Ssaidi@eecs.umich.edu * Ali Saidi 302207SN/A */ 312207SN/A 3211793Sbrandon.potter@amd.com#include "arch/sparc/process.hh" 3311793Sbrandon.potter@amd.com 343589Sgblack@eecs.umich.edu#include "arch/sparc/asi.hh" 354111Sgblack@eecs.umich.edu#include "arch/sparc/handlers.hh" 362474SN/A#include "arch/sparc/isa_traits.hh" 376335Sgblack@eecs.umich.edu#include "arch/sparc/registers.hh" 383760Sgblack@eecs.umich.edu#include "arch/sparc/types.hh" 398229Snate@binkert.org#include "base/loader/elf_object.hh" 402454SN/A#include "base/loader/object_file.hh" 4112334Sgabeblack@google.com#include "base/logging.hh" 422680Sktlim@umich.edu#include "cpu/thread_context.hh" 438232Snate@binkert.org#include "debug/Stack.hh" 442561SN/A#include "mem/page_table.hh" 4512431Sgabeblack@google.com#include "params/Process.hh" 4611854Sbrandon.potter@amd.com#include "sim/aux_vector.hh" 474434Ssaidi@eecs.umich.edu#include "sim/process_impl.hh" 4811800Sbrandon.potter@amd.com#include "sim/syscall_return.hh" 492474SN/A#include "sim/system.hh" 502207SN/A 512458SN/Ausing namespace std; 522474SN/Ausing namespace SparcISA; 532458SN/A 545958Sgblack@eecs.umich.edustatic const int FirstArgumentReg = 8; 555958Sgblack@eecs.umich.edu 562207SN/A 5712431Sgabeblack@google.comSparcProcess::SparcProcess(ProcessParams *params, ObjectFile *objFile, 5811851Sbrandon.potter@amd.com Addr _StackBias) 5912431Sgabeblack@google.com : Process(params, new FuncPageTable(params->name, params->pid), objFile), 6012431Sgabeblack@google.com StackBias(_StackBias) 612474SN/A{ 6212431Sgabeblack@google.com fatal_if(!params->useArchPT, "Arch page tables not implemented."); 637741Sgblack@eecs.umich.edu // Initialize these to 0s 643415Sgblack@eecs.umich.edu fillStart = 0; 653415Sgblack@eecs.umich.edu spillStart = 0; 662474SN/A} 672474SN/A 687741Sgblack@eecs.umich.eduvoid 6911877Sbrandon.potter@amd.comSparcProcess::handleTrap(int trapNum, ThreadContext *tc, Fault *fault) 704111Sgblack@eecs.umich.edu{ 717720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 727741Sgblack@eecs.umich.edu switch (trapNum) { 737741Sgblack@eecs.umich.edu case 0x01: // Software breakpoint 747720Sgblack@eecs.umich.edu warn("Software breakpoint encountered at pc %#x.\n", pc.pc()); 755128Sgblack@eecs.umich.edu break; 767741Sgblack@eecs.umich.edu case 0x02: // Division by zero 777720Sgblack@eecs.umich.edu warn("Software signaled a division by zero at pc %#x.\n", pc.pc()); 785128Sgblack@eecs.umich.edu break; 797741Sgblack@eecs.umich.edu case 0x03: // Flush window trap 805128Sgblack@eecs.umich.edu flushWindows(tc); 815128Sgblack@eecs.umich.edu break; 827741Sgblack@eecs.umich.edu case 0x04: // Clean windows 835128Sgblack@eecs.umich.edu warn("Ignoring process request for clean register " 847720Sgblack@eecs.umich.edu "windows at pc %#x.\n", pc.pc()); 855128Sgblack@eecs.umich.edu break; 867741Sgblack@eecs.umich.edu case 0x05: // Range check 877720Sgblack@eecs.umich.edu warn("Software signaled a range check at pc %#x.\n", pc.pc()); 885128Sgblack@eecs.umich.edu break; 897741Sgblack@eecs.umich.edu case 0x06: // Fix alignment 905128Sgblack@eecs.umich.edu warn("Ignoring process request for os assisted unaligned accesses " 917720Sgblack@eecs.umich.edu "at pc %#x.\n", pc.pc()); 925128Sgblack@eecs.umich.edu break; 937741Sgblack@eecs.umich.edu case 0x07: // Integer overflow 947720Sgblack@eecs.umich.edu warn("Software signaled an integer overflow at pc %#x.\n", pc.pc()); 955128Sgblack@eecs.umich.edu break; 967741Sgblack@eecs.umich.edu case 0x32: // Get integer condition codes 975128Sgblack@eecs.umich.edu warn("Ignoring process request to get the integer condition codes " 987720Sgblack@eecs.umich.edu "at pc %#x.\n", pc.pc()); 995128Sgblack@eecs.umich.edu break; 1007741Sgblack@eecs.umich.edu case 0x33: // Set integer condition codes 1015128Sgblack@eecs.umich.edu warn("Ignoring process request to set the integer condition codes " 1027720Sgblack@eecs.umich.edu "at pc %#x.\n", pc.pc()); 1034111Sgblack@eecs.umich.edu break; 1044111Sgblack@eecs.umich.edu default: 1054111Sgblack@eecs.umich.edu panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum); 1064111Sgblack@eecs.umich.edu } 1074111Sgblack@eecs.umich.edu} 1084111Sgblack@eecs.umich.edu 1092474SN/Avoid 11011851Sbrandon.potter@amd.comSparcProcess::initState() 1114111Sgblack@eecs.umich.edu{ 11211851Sbrandon.potter@amd.com Process::initState(); 1134111Sgblack@eecs.umich.edu 1145713Shsul@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 1157741Sgblack@eecs.umich.edu // From the SPARC ABI 1164111Sgblack@eecs.umich.edu 1177741Sgblack@eecs.umich.edu // Setup default FP state 1185713Shsul@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_FSR, 0); 1192646Ssaidi@eecs.umich.edu 1205713Shsul@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TICK, 0); 1214997Sgblack@eecs.umich.edu 1222561SN/A /* 1232561SN/A * Register window management registers 1242561SN/A */ 1252561SN/A 1267741Sgblack@eecs.umich.edu // No windows contain info from other programs 1277741Sgblack@eecs.umich.edu // tc->setMiscRegNoEffect(MISCREG_OTHERWIN, 0); 1285713Shsul@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 6, 0); 1297741Sgblack@eecs.umich.edu // There are no windows to pop 1307741Sgblack@eecs.umich.edu // tc->setMiscRegNoEffect(MISCREG_CANRESTORE, 0); 1315713Shsul@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 4, 0); 1327741Sgblack@eecs.umich.edu // All windows are available to save into 1337741Sgblack@eecs.umich.edu // tc->setMiscRegNoEffect(MISCREG_CANSAVE, NWindows - 2); 1345713Shsul@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 3, NWindows - 2); 1357741Sgblack@eecs.umich.edu // All windows are "clean" 1367741Sgblack@eecs.umich.edu // tc->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows); 1375713Shsul@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 5, NWindows); 1387741Sgblack@eecs.umich.edu // Start with register window 0 1396337Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, 0); 1407741Sgblack@eecs.umich.edu // Always use spill and fill traps 0 1417741Sgblack@eecs.umich.edu // tc->setMiscRegNoEffect(MISCREG_WSTATE, 0); 1425713Shsul@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 7, 0); 1437741Sgblack@eecs.umich.edu // Set the trap level to 0 1445713Shsul@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TL, 0); 1457741Sgblack@eecs.umich.edu // Set the ASI register to something fixed 1469375Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_ASI, ASI_PRIMARY); 1474997Sgblack@eecs.umich.edu 14811850Sbrandon.potter@amd.com // Set the MMU Primary Context Register to hold the process' pid 14911850Sbrandon.potter@amd.com tc->setMiscReg(MISCREG_MMU_P_CONTEXT, _pid); 15011850Sbrandon.potter@amd.com 1514997Sgblack@eecs.umich.edu /* 1524997Sgblack@eecs.umich.edu * T1 specific registers 1534997Sgblack@eecs.umich.edu */ 1547741Sgblack@eecs.umich.edu // Turn on the icache, dcache, dtb translation, and itb translation. 1555713Shsul@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15); 1562474SN/A} 1572474SN/A 1585285Sgblack@eecs.umich.eduvoid 15911851Sbrandon.potter@amd.comSparc32Process::initState() 1602585SN/A{ 16111851Sbrandon.potter@amd.com SparcProcess::initState(); 1625285Sgblack@eecs.umich.edu 1635713Shsul@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 1647741Sgblack@eecs.umich.edu // The process runs in user mode with 32 bit addresses 1658829Sgblack@eecs.umich.edu PSTATE pstate = 0; 1668829Sgblack@eecs.umich.edu pstate.ie = 1; 1678829Sgblack@eecs.umich.edu pstate.am = 1; 1688829Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_PSTATE, pstate); 1695285Sgblack@eecs.umich.edu 17010318Sandreas.hansson@arm.com argsInit(32 / 8, PageBytes); 1714111Sgblack@eecs.umich.edu} 1723415Sgblack@eecs.umich.edu 1732561SN/Avoid 17411851Sbrandon.potter@amd.comSparc64Process::initState() 1752561SN/A{ 17611851Sbrandon.potter@amd.com SparcProcess::initState(); 1775285Sgblack@eecs.umich.edu 1785713Shsul@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 1797741Sgblack@eecs.umich.edu // The process runs in user mode 1808829Sgblack@eecs.umich.edu PSTATE pstate = 0; 1818829Sgblack@eecs.umich.edu pstate.ie = 1; 1828829Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_PSTATE, pstate); 1835285Sgblack@eecs.umich.edu 18410318Sandreas.hansson@arm.com argsInit(sizeof(IntReg), PageBytes); 1855285Sgblack@eecs.umich.edu} 1865285Sgblack@eecs.umich.edu 1875285Sgblack@eecs.umich.edutemplate<class IntType> 1885285Sgblack@eecs.umich.eduvoid 18911851Sbrandon.potter@amd.comSparcProcess::argsInit(int pageSize) 1905285Sgblack@eecs.umich.edu{ 1915285Sgblack@eecs.umich.edu int intSize = sizeof(IntType); 1925285Sgblack@eecs.umich.edu 1935771Shsul@eecs.umich.edu typedef AuxVector<IntType> auxv_t; 1945285Sgblack@eecs.umich.edu 1955285Sgblack@eecs.umich.edu std::vector<auxv_t> auxv; 1962474SN/A 1973044Sgblack@eecs.umich.edu string filename; 1987741Sgblack@eecs.umich.edu if (argv.size() < 1) 1993044Sgblack@eecs.umich.edu filename = ""; 2003044Sgblack@eecs.umich.edu else 2013044Sgblack@eecs.umich.edu filename = argv[0]; 2023044Sgblack@eecs.umich.edu 2037741Sgblack@eecs.umich.edu // Even for a 32 bit process, the ABI says we still need to 2047741Sgblack@eecs.umich.edu // maintain double word alignment of the stack pointer. 2055286Sgblack@eecs.umich.edu uint64_t align = 16; 2062561SN/A 20711389Sbrandon.potter@amd.com // Patch the ld_bias for dynamic executables. 20811389Sbrandon.potter@amd.com updateBias(); 20911389Sbrandon.potter@amd.com 2102561SN/A // load object file into target memory 2112561SN/A objFile->loadSections(initVirtMem); 2122561SN/A 2132585SN/A enum hardwareCaps 2142585SN/A { 2152585SN/A M5_HWCAP_SPARC_FLUSH = 1, 2162585SN/A M5_HWCAP_SPARC_STBAR = 2, 2172585SN/A M5_HWCAP_SPARC_SWAP = 4, 2182585SN/A M5_HWCAP_SPARC_MULDIV = 8, 2192585SN/A M5_HWCAP_SPARC_V9 = 16, 2207741Sgblack@eecs.umich.edu // This one should technically only be set 2217741Sgblack@eecs.umich.edu // if there is a cheetah or cheetah_plus tlb, 2227741Sgblack@eecs.umich.edu // but we'll use it all the time 2232585SN/A M5_HWCAP_SPARC_ULTRA3 = 32 2242585SN/A }; 2252585SN/A 2262585SN/A const int64_t hwcap = 2272585SN/A M5_HWCAP_SPARC_FLUSH | 2282585SN/A M5_HWCAP_SPARC_STBAR | 2292585SN/A M5_HWCAP_SPARC_SWAP | 2302585SN/A M5_HWCAP_SPARC_MULDIV | 2312585SN/A M5_HWCAP_SPARC_V9 | 2322585SN/A M5_HWCAP_SPARC_ULTRA3; 2332585SN/A 2347741Sgblack@eecs.umich.edu // Setup the auxilliary vectors. These will already have endian conversion. 2357741Sgblack@eecs.umich.edu // Auxilliary vectors are loaded only for elf formatted executables. 2362976Sgblack@eecs.umich.edu ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 2377741Sgblack@eecs.umich.edu if (elfObject) { 2387741Sgblack@eecs.umich.edu // Bits which describe the system hardware capabilities 2394793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_HWCAP, hwcap)); 2407741Sgblack@eecs.umich.edu // The system page size 24110318Sandreas.hansson@arm.com auxv.push_back(auxv_t(M5_AT_PAGESZ, SparcISA::PageBytes)); 2427741Sgblack@eecs.umich.edu // Defined to be 100 in the kernel source. 2437741Sgblack@eecs.umich.edu // Frequency at which times() increments 2444793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 2452976Sgblack@eecs.umich.edu // For statically linked executables, this is the virtual address of the 2462976Sgblack@eecs.umich.edu // program header tables if they appear in the executable image 2474793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 2482976Sgblack@eecs.umich.edu // This is the size of a program header entry from the elf file. 2494793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 2502976Sgblack@eecs.umich.edu // This is the number of program headers from the original elf file. 2514793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 25211389Sbrandon.potter@amd.com // This is the base address of the ELF interpreter; it should be 25311389Sbrandon.potter@amd.com // zero for static executables or contain the base address for 25411389Sbrandon.potter@amd.com // dynamic executables. 25511389Sbrandon.potter@amd.com auxv.push_back(auxv_t(M5_AT_BASE, getBias())); 2567741Sgblack@eecs.umich.edu // This is hardwired to 0 in the elf loading code in the kernel 2574793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_FLAGS, 0)); 2587741Sgblack@eecs.umich.edu // The entry point to the program 2594793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 2607741Sgblack@eecs.umich.edu // Different user and group IDs 2614793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_UID, uid())); 2624793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_EUID, euid())); 2634793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_GID, gid())); 2644793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_EGID, egid())); 2657741Sgblack@eecs.umich.edu // Whether to enable "secure mode" in the executable 2664793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_SECURE, 0)); 2672976Sgblack@eecs.umich.edu } 2682585SN/A 2697741Sgblack@eecs.umich.edu // Figure out how big the initial stack needs to be 2702561SN/A 2714164Sgblack@eecs.umich.edu // The unaccounted for 8 byte 0 at the top of the stack 2725286Sgblack@eecs.umich.edu int sentry_size = 8; 2734111Sgblack@eecs.umich.edu 2747741Sgblack@eecs.umich.edu // This is the name of the file which is present on the initial stack 2757741Sgblack@eecs.umich.edu // It's purpose is to let the user space linker examine the original file. 2764111Sgblack@eecs.umich.edu int file_name_size = filename.size() + 1; 2774111Sgblack@eecs.umich.edu 2784111Sgblack@eecs.umich.edu int env_data_size = 0; 2794111Sgblack@eecs.umich.edu for (int i = 0; i < envp.size(); ++i) { 2804111Sgblack@eecs.umich.edu env_data_size += envp[i].size() + 1; 2814111Sgblack@eecs.umich.edu } 2824111Sgblack@eecs.umich.edu int arg_data_size = 0; 2834111Sgblack@eecs.umich.edu for (int i = 0; i < argv.size(); ++i) { 2844111Sgblack@eecs.umich.edu arg_data_size += argv[i].size() + 1; 2854111Sgblack@eecs.umich.edu } 2864111Sgblack@eecs.umich.edu 2877741Sgblack@eecs.umich.edu // The info_block. 2885286Sgblack@eecs.umich.edu int base_info_block_size = 2895286Sgblack@eecs.umich.edu sentry_size + file_name_size + env_data_size + arg_data_size; 2905286Sgblack@eecs.umich.edu 2915286Sgblack@eecs.umich.edu int info_block_size = roundUp(base_info_block_size, align); 2925286Sgblack@eecs.umich.edu 2935286Sgblack@eecs.umich.edu int info_block_padding = info_block_size - base_info_block_size; 2944111Sgblack@eecs.umich.edu 2957741Sgblack@eecs.umich.edu // Each auxilliary vector is two words 2964111Sgblack@eecs.umich.edu int aux_array_size = intSize * 2 * (auxv.size() + 1); 2974111Sgblack@eecs.umich.edu 2984111Sgblack@eecs.umich.edu int envp_array_size = intSize * (envp.size() + 1); 2994111Sgblack@eecs.umich.edu int argv_array_size = intSize * (argv.size() + 1); 3004111Sgblack@eecs.umich.edu 3014111Sgblack@eecs.umich.edu int argc_size = intSize; 3024111Sgblack@eecs.umich.edu int window_save_size = intSize * 16; 3034111Sgblack@eecs.umich.edu 3047741Sgblack@eecs.umich.edu // Figure out the size of the contents of the actual initial frame 3055286Sgblack@eecs.umich.edu int frame_size = 3064111Sgblack@eecs.umich.edu aux_array_size + 3074111Sgblack@eecs.umich.edu envp_array_size + 3084111Sgblack@eecs.umich.edu argv_array_size + 3094111Sgblack@eecs.umich.edu argc_size + 3104111Sgblack@eecs.umich.edu window_save_size; 3114111Sgblack@eecs.umich.edu 3127741Sgblack@eecs.umich.edu // There needs to be padding after the auxiliary vector data so that the 3137741Sgblack@eecs.umich.edu // very bottom of the stack is aligned properly. 3145286Sgblack@eecs.umich.edu int aligned_partial_size = roundUp(frame_size, align); 3155286Sgblack@eecs.umich.edu int aux_padding = aligned_partial_size - frame_size; 3165286Sgblack@eecs.umich.edu 3175286Sgblack@eecs.umich.edu int space_needed = 3185286Sgblack@eecs.umich.edu info_block_size + 3195286Sgblack@eecs.umich.edu aux_padding + 3205286Sgblack@eecs.umich.edu frame_size; 3215286Sgblack@eecs.umich.edu 32211905SBrandon.Potter@amd.com memState->setStackMin(memState->getStackBase() - space_needed); 32311905SBrandon.Potter@amd.com memState->setStackMin(roundDown(memState->getStackMin(), align)); 32411905SBrandon.Potter@amd.com memState->setStackSize(memState->getStackBase() - memState->getStackMin()); 3254111Sgblack@eecs.umich.edu 3265285Sgblack@eecs.umich.edu // Allocate space for the stack 32711905SBrandon.Potter@amd.com allocateMem(roundDown(memState->getStackMin(), pageSize), 32811905SBrandon.Potter@amd.com roundUp(memState->getStackSize(), pageSize)); 3294111Sgblack@eecs.umich.edu 3304111Sgblack@eecs.umich.edu // map out initial stack contents 33111905SBrandon.Potter@amd.com IntType sentry_base = memState->getStackBase() - sentry_size; 3325286Sgblack@eecs.umich.edu IntType file_name_base = sentry_base - file_name_size; 3335286Sgblack@eecs.umich.edu IntType env_data_base = file_name_base - env_data_size; 3345286Sgblack@eecs.umich.edu IntType arg_data_base = env_data_base - arg_data_size; 3355286Sgblack@eecs.umich.edu IntType auxv_array_base = arg_data_base - 3365286Sgblack@eecs.umich.edu info_block_padding - aux_array_size - aux_padding; 3375286Sgblack@eecs.umich.edu IntType envp_array_base = auxv_array_base - envp_array_size; 3385286Sgblack@eecs.umich.edu IntType argv_array_base = envp_array_base - argv_array_size; 3395286Sgblack@eecs.umich.edu IntType argc_base = argv_array_base - argc_size; 3405286Sgblack@eecs.umich.edu#if TRACING_ON 3415286Sgblack@eecs.umich.edu IntType window_save_base = argc_base - window_save_size; 3425286Sgblack@eecs.umich.edu#endif 3434111Sgblack@eecs.umich.edu 3445941Sgblack@eecs.umich.edu DPRINTF(Stack, "The addresses of items on the initial stack:\n"); 3455941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - sentry NULL\n", sentry_base); 3465941Sgblack@eecs.umich.edu DPRINTF(Stack, "filename = %s\n", filename); 3475941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - file name\n", file_name_base); 3485941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - env data\n", env_data_base); 3495941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - arg data\n", arg_data_base); 3505941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - auxv array\n", auxv_array_base); 3515941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - envp array\n", envp_array_base); 3525941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - argv array\n", argv_array_base); 3535941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - argc \n", argc_base); 3545941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - window save\n", window_save_base); 35511905SBrandon.Potter@amd.com DPRINTF(Stack, "%#x - stack min\n", memState->getStackMin()); 3564111Sgblack@eecs.umich.edu 35711905SBrandon.Potter@amd.com assert(window_save_base == memState->getStackMin()); 3585286Sgblack@eecs.umich.edu 3594111Sgblack@eecs.umich.edu // write contents to stack 3604111Sgblack@eecs.umich.edu 3614111Sgblack@eecs.umich.edu // figure out argc 3625285Sgblack@eecs.umich.edu IntType argc = argv.size(); 3635567Snate@binkert.org IntType guestArgc = SparcISA::htog(argc); 3644111Sgblack@eecs.umich.edu 3657741Sgblack@eecs.umich.edu // Write out the sentry void * 3665286Sgblack@eecs.umich.edu uint64_t sentry_NULL = 0; 3678852Sandreas.hansson@arm.com initVirtMem.writeBlob(sentry_base, 3685286Sgblack@eecs.umich.edu (uint8_t*)&sentry_NULL, sentry_size); 3694111Sgblack@eecs.umich.edu 3707741Sgblack@eecs.umich.edu // Write the file name 3718852Sandreas.hansson@arm.com initVirtMem.writeString(file_name_base, filename.c_str()); 3724111Sgblack@eecs.umich.edu 3737741Sgblack@eecs.umich.edu // Copy the aux stuff 3747741Sgblack@eecs.umich.edu for (int x = 0; x < auxv.size(); x++) { 3758852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize, 3764111Sgblack@eecs.umich.edu (uint8_t*)&(auxv[x].a_type), intSize); 3778852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 3784111Sgblack@eecs.umich.edu (uint8_t*)&(auxv[x].a_val), intSize); 3794111Sgblack@eecs.umich.edu } 3805285Sgblack@eecs.umich.edu 3817741Sgblack@eecs.umich.edu // Write out the terminating zeroed auxilliary vector 3825285Sgblack@eecs.umich.edu const IntType zero = 0; 3838852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + intSize * 2 * auxv.size(), 3845286Sgblack@eecs.umich.edu (uint8_t*)&zero, intSize); 3858852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + intSize * (2 * auxv.size() + 1), 3865286Sgblack@eecs.umich.edu (uint8_t*)&zero, intSize); 3874111Sgblack@eecs.umich.edu 3884117Sgblack@eecs.umich.edu copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 3894117Sgblack@eecs.umich.edu copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 3904111Sgblack@eecs.umich.edu 3918852Sandreas.hansson@arm.com initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); 3924111Sgblack@eecs.umich.edu 3937741Sgblack@eecs.umich.edu // Set up space for the trap handlers into the processes address space. 3947741Sgblack@eecs.umich.edu // Since the stack grows down and there is reserved address space abov 3957741Sgblack@eecs.umich.edu // it, we can put stuff above it and stay out of the way. 39611905SBrandon.Potter@amd.com fillStart = memState->getStackBase(); 3975285Sgblack@eecs.umich.edu spillStart = fillStart + sizeof(MachInst) * numFillInsts; 3984111Sgblack@eecs.umich.edu 3995713Shsul@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 4007741Sgblack@eecs.umich.edu // Set up the thread context to start running the process 4017741Sgblack@eecs.umich.edu // assert(NumArgumentRegs >= 2); 4027741Sgblack@eecs.umich.edu // tc->setIntReg(ArgumentReg[0], argc); 4037741Sgblack@eecs.umich.edu // tc->setIntReg(ArgumentReg[1], argv_array_base); 40411905SBrandon.Potter@amd.com tc->setIntReg(StackPointerReg, memState->getStackMin() - StackBias); 4054111Sgblack@eecs.umich.edu 4065231Sgblack@eecs.umich.edu // %g1 is a pointer to a function that should be run at exit. Since we 4075231Sgblack@eecs.umich.edu // don't have anything like that, it should be set to 0. 4085713Shsul@eecs.umich.edu tc->setIntReg(1, 0); 4095231Sgblack@eecs.umich.edu 41011389Sbrandon.potter@amd.com tc->pcState(getStartPC()); 4114111Sgblack@eecs.umich.edu 4127741Sgblack@eecs.umich.edu // Align the "stack_min" to a page boundary. 41311905SBrandon.Potter@amd.com memState->setStackMin(roundDown(memState->getStackMin(), pageSize)); 4144111Sgblack@eecs.umich.edu} 4155128Sgblack@eecs.umich.edu 4165285Sgblack@eecs.umich.eduvoid 41711851Sbrandon.potter@amd.comSparc64Process::argsInit(int intSize, int pageSize) 4185285Sgblack@eecs.umich.edu{ 41911851Sbrandon.potter@amd.com SparcProcess::argsInit<uint64_t>(pageSize); 4205285Sgblack@eecs.umich.edu 4215285Sgblack@eecs.umich.edu // Stuff the trap handlers into the process address space 4228852Sandreas.hansson@arm.com initVirtMem.writeBlob(fillStart, 4235285Sgblack@eecs.umich.edu (uint8_t*)fillHandler64, sizeof(MachInst) * numFillInsts); 4248852Sandreas.hansson@arm.com initVirtMem.writeBlob(spillStart, 4255285Sgblack@eecs.umich.edu (uint8_t*)spillHandler64, sizeof(MachInst) * numSpillInsts); 4265285Sgblack@eecs.umich.edu} 4275285Sgblack@eecs.umich.edu 4285285Sgblack@eecs.umich.eduvoid 42911851Sbrandon.potter@amd.comSparc32Process::argsInit(int intSize, int pageSize) 4305285Sgblack@eecs.umich.edu{ 43111851Sbrandon.potter@amd.com SparcProcess::argsInit<uint32_t>(pageSize); 4325285Sgblack@eecs.umich.edu 4335285Sgblack@eecs.umich.edu // Stuff the trap handlers into the process address space 4348852Sandreas.hansson@arm.com initVirtMem.writeBlob(fillStart, 4355285Sgblack@eecs.umich.edu (uint8_t*)fillHandler32, sizeof(MachInst) * numFillInsts); 4368852Sandreas.hansson@arm.com initVirtMem.writeBlob(spillStart, 4375285Sgblack@eecs.umich.edu (uint8_t*)spillHandler32, sizeof(MachInst) * numSpillInsts); 4385285Sgblack@eecs.umich.edu} 4395285Sgblack@eecs.umich.edu 44011851Sbrandon.potter@amd.comvoid Sparc32Process::flushWindows(ThreadContext *tc) 4415128Sgblack@eecs.umich.edu{ 4425128Sgblack@eecs.umich.edu IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); 4435128Sgblack@eecs.umich.edu IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); 4445128Sgblack@eecs.umich.edu IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); 4455128Sgblack@eecs.umich.edu MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 4465128Sgblack@eecs.umich.edu MiscReg origCWP = CWP; 4475128Sgblack@eecs.umich.edu CWP = (CWP + Cansave + 2) % NWindows; 4487741Sgblack@eecs.umich.edu while (NWindows - 2 - Cansave != 0) { 4495128Sgblack@eecs.umich.edu if (Otherwin) { 4505128Sgblack@eecs.umich.edu panic("Otherwin non-zero.\n"); 4515128Sgblack@eecs.umich.edu } else { 4525128Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, CWP); 4537741Sgblack@eecs.umich.edu // Do the stores 4545128Sgblack@eecs.umich.edu IntReg sp = tc->readIntReg(StackPointerReg); 4555128Sgblack@eecs.umich.edu for (int index = 16; index < 32; index++) { 4565287Sgblack@eecs.umich.edu uint32_t regVal = tc->readIntReg(index); 4575128Sgblack@eecs.umich.edu regVal = htog(regVal); 4588852Sandreas.hansson@arm.com if (!tc->getMemProxy().tryWriteBlob( 4595128Sgblack@eecs.umich.edu sp + (index - 16) * 4, (uint8_t *)®Val, 4)) { 4605128Sgblack@eecs.umich.edu warn("Failed to save register to the stack when " 4615128Sgblack@eecs.umich.edu "flushing windows.\n"); 4625128Sgblack@eecs.umich.edu } 4635128Sgblack@eecs.umich.edu } 4645128Sgblack@eecs.umich.edu Canrestore--; 4655128Sgblack@eecs.umich.edu Cansave++; 4665128Sgblack@eecs.umich.edu CWP = (CWP + 1) % NWindows; 4675128Sgblack@eecs.umich.edu } 4685128Sgblack@eecs.umich.edu } 4695128Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 3, Cansave); 4705128Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 4, Canrestore); 4715128Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, origCWP); 4725128Sgblack@eecs.umich.edu} 4735128Sgblack@eecs.umich.edu 4747741Sgblack@eecs.umich.eduvoid 47511851Sbrandon.potter@amd.comSparc64Process::flushWindows(ThreadContext *tc) 4765128Sgblack@eecs.umich.edu{ 4775128Sgblack@eecs.umich.edu IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); 4785128Sgblack@eecs.umich.edu IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); 4795128Sgblack@eecs.umich.edu IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); 4805128Sgblack@eecs.umich.edu MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 4815128Sgblack@eecs.umich.edu MiscReg origCWP = CWP; 4825128Sgblack@eecs.umich.edu CWP = (CWP + Cansave + 2) % NWindows; 4837741Sgblack@eecs.umich.edu while (NWindows - 2 - Cansave != 0) { 4845128Sgblack@eecs.umich.edu if (Otherwin) { 4855128Sgblack@eecs.umich.edu panic("Otherwin non-zero.\n"); 4865128Sgblack@eecs.umich.edu } else { 4875128Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, CWP); 4887741Sgblack@eecs.umich.edu // Do the stores 4895128Sgblack@eecs.umich.edu IntReg sp = tc->readIntReg(StackPointerReg); 4905128Sgblack@eecs.umich.edu for (int index = 16; index < 32; index++) { 4915128Sgblack@eecs.umich.edu IntReg regVal = tc->readIntReg(index); 4925128Sgblack@eecs.umich.edu regVal = htog(regVal); 4938852Sandreas.hansson@arm.com if (!tc->getMemProxy().tryWriteBlob( 4945128Sgblack@eecs.umich.edu sp + 2047 + (index - 16) * 8, (uint8_t *)®Val, 8)) { 4955128Sgblack@eecs.umich.edu warn("Failed to save register to the stack when " 4965128Sgblack@eecs.umich.edu "flushing windows.\n"); 4975128Sgblack@eecs.umich.edu } 4985128Sgblack@eecs.umich.edu } 4995128Sgblack@eecs.umich.edu Canrestore--; 5005128Sgblack@eecs.umich.edu Cansave++; 5015128Sgblack@eecs.umich.edu CWP = (CWP + 1) % NWindows; 5025128Sgblack@eecs.umich.edu } 5035128Sgblack@eecs.umich.edu } 5045128Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 3, Cansave); 5055128Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 4, Canrestore); 5065128Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, origCWP); 5075128Sgblack@eecs.umich.edu} 5085958Sgblack@eecs.umich.edu 5095958Sgblack@eecs.umich.eduIntReg 51011851Sbrandon.potter@amd.comSparc32Process::getSyscallArg(ThreadContext *tc, int &i) 5115958Sgblack@eecs.umich.edu{ 5125958Sgblack@eecs.umich.edu assert(i < 6); 5136701Sgblack@eecs.umich.edu return bits(tc->readIntReg(FirstArgumentReg + i++), 31, 0); 5145958Sgblack@eecs.umich.edu} 5155958Sgblack@eecs.umich.edu 5165958Sgblack@eecs.umich.eduvoid 51711851Sbrandon.potter@amd.comSparc32Process::setSyscallArg(ThreadContext *tc, int i, IntReg val) 5185958Sgblack@eecs.umich.edu{ 5195958Sgblack@eecs.umich.edu assert(i < 6); 5205958Sgblack@eecs.umich.edu tc->setIntReg(FirstArgumentReg + i, bits(val, 31, 0)); 5215958Sgblack@eecs.umich.edu} 5225958Sgblack@eecs.umich.edu 5235958Sgblack@eecs.umich.eduIntReg 52411851Sbrandon.potter@amd.comSparc64Process::getSyscallArg(ThreadContext *tc, int &i) 5255958Sgblack@eecs.umich.edu{ 5265958Sgblack@eecs.umich.edu assert(i < 6); 5276701Sgblack@eecs.umich.edu return tc->readIntReg(FirstArgumentReg + i++); 5285958Sgblack@eecs.umich.edu} 5295958Sgblack@eecs.umich.edu 5305958Sgblack@eecs.umich.eduvoid 53111851Sbrandon.potter@amd.comSparc64Process::setSyscallArg(ThreadContext *tc, int i, IntReg val) 5325958Sgblack@eecs.umich.edu{ 5335958Sgblack@eecs.umich.edu assert(i < 6); 5345958Sgblack@eecs.umich.edu tc->setIntReg(FirstArgumentReg + i, val); 5355958Sgblack@eecs.umich.edu} 5365958Sgblack@eecs.umich.edu 5375958Sgblack@eecs.umich.eduvoid 53811851Sbrandon.potter@amd.comSparcProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) 5395958Sgblack@eecs.umich.edu{ 5405958Sgblack@eecs.umich.edu // check for error condition. SPARC syscall convention is to 5415958Sgblack@eecs.umich.edu // indicate success/failure in reg the carry bit of the ccr 5425958Sgblack@eecs.umich.edu // and put the return value itself in the standard return value reg (). 5438829Sgblack@eecs.umich.edu PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); 54410223Ssteve.reinhardt@amd.com if (sysret.successful()) { 5455958Sgblack@eecs.umich.edu // no error, clear XCC.C 5465958Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 2, 54710223Ssteve.reinhardt@amd.com tc->readIntReg(NumIntArchRegs + 2) & 0xEE); 54810223Ssteve.reinhardt@amd.com IntReg val = sysret.returnValue(); 5498829Sgblack@eecs.umich.edu if (pstate.am) 5505958Sgblack@eecs.umich.edu val = bits(val, 31, 0); 5515958Sgblack@eecs.umich.edu tc->setIntReg(ReturnValueReg, val); 5525958Sgblack@eecs.umich.edu } else { 5535958Sgblack@eecs.umich.edu // got an error, set XCC.C 5545958Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 2, 55510223Ssteve.reinhardt@amd.com tc->readIntReg(NumIntArchRegs + 2) | 0x11); 55610223Ssteve.reinhardt@amd.com IntReg val = sysret.errnoValue(); 5578829Sgblack@eecs.umich.edu if (pstate.am) 5585958Sgblack@eecs.umich.edu val = bits(val, 31, 0); 5595958Sgblack@eecs.umich.edu tc->setIntReg(ReturnValueReg, val); 5605958Sgblack@eecs.umich.edu } 5615958Sgblack@eecs.umich.edu} 562