process.cc revision 11385
110259SAndrew.Bardsley@arm.com/* 210259SAndrew.Bardsley@arm.com * Copyright (c) 2003-2004 The Regents of The University of Michigan 310259SAndrew.Bardsley@arm.com * All rights reserved. 410259SAndrew.Bardsley@arm.com * 510259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 610259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 710259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 810259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 910259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 1010259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 1110259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 1210259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 1310259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 1410259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 1510259SAndrew.Bardsley@arm.com * 1610259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710259SAndrew.Bardsley@arm.com * 2810259SAndrew.Bardsley@arm.com * Authors: Gabe Black 2910259SAndrew.Bardsley@arm.com * Ali Saidi 3010259SAndrew.Bardsley@arm.com */ 3110259SAndrew.Bardsley@arm.com 3210259SAndrew.Bardsley@arm.com#include "arch/sparc/asi.hh" 3310259SAndrew.Bardsley@arm.com#include "arch/sparc/handlers.hh" 3410259SAndrew.Bardsley@arm.com#include "arch/sparc/isa_traits.hh" 3510259SAndrew.Bardsley@arm.com#include "arch/sparc/process.hh" 3610259SAndrew.Bardsley@arm.com#include "arch/sparc/registers.hh" 3710259SAndrew.Bardsley@arm.com#include "arch/sparc/types.hh" 3810259SAndrew.Bardsley@arm.com#include "base/loader/elf_object.hh" 3910259SAndrew.Bardsley@arm.com#include "base/loader/object_file.hh" 4011793Sbrandon.potter@amd.com#include "base/misc.hh" 4111793Sbrandon.potter@amd.com#include "cpu/thread_context.hh" 4210259SAndrew.Bardsley@arm.com#include "debug/Stack.hh" 4310259SAndrew.Bardsley@arm.com#include "mem/page_table.hh" 4410259SAndrew.Bardsley@arm.com#include "sim/process_impl.hh" 4510259SAndrew.Bardsley@arm.com#include "sim/system.hh" 4610259SAndrew.Bardsley@arm.com 4710259SAndrew.Bardsley@arm.comusing namespace std; 4810259SAndrew.Bardsley@arm.comusing namespace SparcISA; 4910259SAndrew.Bardsley@arm.com 5010259SAndrew.Bardsley@arm.comstatic const int FirstArgumentReg = 8; 5110259SAndrew.Bardsley@arm.com 5210259SAndrew.Bardsley@arm.com 5310259SAndrew.Bardsley@arm.comSparcLiveProcess::SparcLiveProcess(LiveProcessParams * params, 5410259SAndrew.Bardsley@arm.com ObjectFile *objFile, Addr _StackBias) 5510259SAndrew.Bardsley@arm.com : LiveProcess(params, objFile), StackBias(_StackBias) 5610259SAndrew.Bardsley@arm.com{ 5710259SAndrew.Bardsley@arm.com 5810259SAndrew.Bardsley@arm.com // XXX all the below need to be updated for SPARC - Ali 5910259SAndrew.Bardsley@arm.com brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); 6010259SAndrew.Bardsley@arm.com brk_point = roundUp(brk_point, PageBytes); 6111567Smitch.hayenga@arm.com 6210259SAndrew.Bardsley@arm.com // Set pointer for next thread stack. Reserve 8M for main stack. 6310259SAndrew.Bardsley@arm.com next_thread_stack_base = stack_base - (8 * 1024 * 1024); 6410259SAndrew.Bardsley@arm.com 6510259SAndrew.Bardsley@arm.com // Initialize these to 0s 6610259SAndrew.Bardsley@arm.com fillStart = 0; 6710259SAndrew.Bardsley@arm.com spillStart = 0; 6810259SAndrew.Bardsley@arm.com} 6910259SAndrew.Bardsley@arm.com 7010259SAndrew.Bardsley@arm.comvoid 7110259SAndrew.Bardsley@arm.comSparcLiveProcess::handleTrap(int trapNum, ThreadContext *tc) 7211567Smitch.hayenga@arm.com{ 7311567Smitch.hayenga@arm.com PCState pc = tc->pcState(); 7410259SAndrew.Bardsley@arm.com switch (trapNum) { 7510259SAndrew.Bardsley@arm.com case 0x01: // Software breakpoint 7610259SAndrew.Bardsley@arm.com warn("Software breakpoint encountered at pc %#x.\n", pc.pc()); 7710259SAndrew.Bardsley@arm.com break; 7810259SAndrew.Bardsley@arm.com case 0x02: // Division by zero 7910259SAndrew.Bardsley@arm.com warn("Software signaled a division by zero at pc %#x.\n", pc.pc()); 8010259SAndrew.Bardsley@arm.com break; 8110259SAndrew.Bardsley@arm.com case 0x03: // Flush window trap 8210259SAndrew.Bardsley@arm.com flushWindows(tc); 8310259SAndrew.Bardsley@arm.com break; 8410259SAndrew.Bardsley@arm.com case 0x04: // Clean windows 8510259SAndrew.Bardsley@arm.com warn("Ignoring process request for clean register " 8610259SAndrew.Bardsley@arm.com "windows at pc %#x.\n", pc.pc()); 8710259SAndrew.Bardsley@arm.com break; 8810259SAndrew.Bardsley@arm.com case 0x05: // Range check 8910259SAndrew.Bardsley@arm.com warn("Software signaled a range check at pc %#x.\n", pc.pc()); 9010259SAndrew.Bardsley@arm.com break; 9110259SAndrew.Bardsley@arm.com case 0x06: // Fix alignment 9210259SAndrew.Bardsley@arm.com warn("Ignoring process request for os assisted unaligned accesses " 9310259SAndrew.Bardsley@arm.com "at pc %#x.\n", pc.pc()); 9410259SAndrew.Bardsley@arm.com break; 9510259SAndrew.Bardsley@arm.com case 0x07: // Integer overflow 9610259SAndrew.Bardsley@arm.com warn("Software signaled an integer overflow at pc %#x.\n", pc.pc()); 9710259SAndrew.Bardsley@arm.com break; 9810259SAndrew.Bardsley@arm.com case 0x32: // Get integer condition codes 9910259SAndrew.Bardsley@arm.com warn("Ignoring process request to get the integer condition codes " 10010259SAndrew.Bardsley@arm.com "at pc %#x.\n", pc.pc()); 10110259SAndrew.Bardsley@arm.com break; 10210259SAndrew.Bardsley@arm.com case 0x33: // Set integer condition codes 10310259SAndrew.Bardsley@arm.com warn("Ignoring process request to set the integer condition codes " 10410259SAndrew.Bardsley@arm.com "at pc %#x.\n", pc.pc()); 10510259SAndrew.Bardsley@arm.com break; 10610259SAndrew.Bardsley@arm.com default: 10710259SAndrew.Bardsley@arm.com panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum); 10810259SAndrew.Bardsley@arm.com } 10910259SAndrew.Bardsley@arm.com} 11010259SAndrew.Bardsley@arm.com 11110259SAndrew.Bardsley@arm.comvoid 11210259SAndrew.Bardsley@arm.comSparcLiveProcess::initState() 11310259SAndrew.Bardsley@arm.com{ 11410259SAndrew.Bardsley@arm.com LiveProcess::initState(); 11511567Smitch.hayenga@arm.com 11611567Smitch.hayenga@arm.com ThreadContext *tc = system->getThreadContext(contextIds[0]); 11711567Smitch.hayenga@arm.com // From the SPARC ABI 11811567Smitch.hayenga@arm.com 11911567Smitch.hayenga@arm.com // Setup default FP state 12011567Smitch.hayenga@arm.com tc->setMiscRegNoEffect(MISCREG_FSR, 0); 12111567Smitch.hayenga@arm.com 12211567Smitch.hayenga@arm.com tc->setMiscRegNoEffect(MISCREG_TICK, 0); 12311567Smitch.hayenga@arm.com 12411567Smitch.hayenga@arm.com /* 12511567Smitch.hayenga@arm.com * Register window management registers 12611567Smitch.hayenga@arm.com */ 12711567Smitch.hayenga@arm.com 12811567Smitch.hayenga@arm.com // No windows contain info from other programs 12911567Smitch.hayenga@arm.com // tc->setMiscRegNoEffect(MISCREG_OTHERWIN, 0); 13011567Smitch.hayenga@arm.com tc->setIntReg(NumIntArchRegs + 6, 0); 13111567Smitch.hayenga@arm.com // There are no windows to pop 13211567Smitch.hayenga@arm.com // tc->setMiscRegNoEffect(MISCREG_CANRESTORE, 0); 13311567Smitch.hayenga@arm.com tc->setIntReg(NumIntArchRegs + 4, 0); 13411567Smitch.hayenga@arm.com // All windows are available to save into 13511567Smitch.hayenga@arm.com // tc->setMiscRegNoEffect(MISCREG_CANSAVE, NWindows - 2); 13611567Smitch.hayenga@arm.com tc->setIntReg(NumIntArchRegs + 3, NWindows - 2); 13711567Smitch.hayenga@arm.com // All windows are "clean" 13811567Smitch.hayenga@arm.com // tc->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows); 13911567Smitch.hayenga@arm.com tc->setIntReg(NumIntArchRegs + 5, NWindows); 14011567Smitch.hayenga@arm.com // Start with register window 0 14111567Smitch.hayenga@arm.com tc->setMiscReg(MISCREG_CWP, 0); 14211567Smitch.hayenga@arm.com // Always use spill and fill traps 0 14311567Smitch.hayenga@arm.com // tc->setMiscRegNoEffect(MISCREG_WSTATE, 0); 14411567Smitch.hayenga@arm.com tc->setIntReg(NumIntArchRegs + 7, 0); 14511567Smitch.hayenga@arm.com // Set the trap level to 0 14611567Smitch.hayenga@arm.com tc->setMiscRegNoEffect(MISCREG_TL, 0); 14710259SAndrew.Bardsley@arm.com // Set the ASI register to something fixed 14811567Smitch.hayenga@arm.com tc->setMiscReg(MISCREG_ASI, ASI_PRIMARY); 14910259SAndrew.Bardsley@arm.com 15011567Smitch.hayenga@arm.com /* 15111567Smitch.hayenga@arm.com * T1 specific registers 15211567Smitch.hayenga@arm.com */ 15310259SAndrew.Bardsley@arm.com // Turn on the icache, dcache, dtb translation, and itb translation. 15410259SAndrew.Bardsley@arm.com tc->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15); 15510259SAndrew.Bardsley@arm.com} 15611567Smitch.hayenga@arm.com 15710259SAndrew.Bardsley@arm.comvoid 15810259SAndrew.Bardsley@arm.comSparc32LiveProcess::initState() 15910259SAndrew.Bardsley@arm.com{ 16010259SAndrew.Bardsley@arm.com SparcLiveProcess::initState(); 16111567Smitch.hayenga@arm.com 16211567Smitch.hayenga@arm.com ThreadContext *tc = system->getThreadContext(contextIds[0]); 16310259SAndrew.Bardsley@arm.com // The process runs in user mode with 32 bit addresses 16410259SAndrew.Bardsley@arm.com PSTATE pstate = 0; 16511567Smitch.hayenga@arm.com pstate.ie = 1; 16610259SAndrew.Bardsley@arm.com pstate.am = 1; 16710259SAndrew.Bardsley@arm.com tc->setMiscReg(MISCREG_PSTATE, pstate); 16810259SAndrew.Bardsley@arm.com 16911567Smitch.hayenga@arm.com argsInit(32 / 8, PageBytes); 17010259SAndrew.Bardsley@arm.com} 17111567Smitch.hayenga@arm.com 17210259SAndrew.Bardsley@arm.comvoid 17310259SAndrew.Bardsley@arm.comSparc64LiveProcess::initState() 17410259SAndrew.Bardsley@arm.com{ 17511567Smitch.hayenga@arm.com SparcLiveProcess::initState(); 17610259SAndrew.Bardsley@arm.com 17710259SAndrew.Bardsley@arm.com ThreadContext *tc = system->getThreadContext(contextIds[0]); 17810259SAndrew.Bardsley@arm.com // The process runs in user mode 17910259SAndrew.Bardsley@arm.com PSTATE pstate = 0; 18010259SAndrew.Bardsley@arm.com pstate.ie = 1; 18110259SAndrew.Bardsley@arm.com tc->setMiscReg(MISCREG_PSTATE, pstate); 18210259SAndrew.Bardsley@arm.com 18310259SAndrew.Bardsley@arm.com argsInit(sizeof(IntReg), PageBytes); 18410259SAndrew.Bardsley@arm.com} 18510259SAndrew.Bardsley@arm.com 18610259SAndrew.Bardsley@arm.comtemplate<class IntType> 18710259SAndrew.Bardsley@arm.comvoid 18810259SAndrew.Bardsley@arm.comSparcLiveProcess::argsInit(int pageSize) 18910259SAndrew.Bardsley@arm.com{ 19010259SAndrew.Bardsley@arm.com int intSize = sizeof(IntType); 19110259SAndrew.Bardsley@arm.com 19210259SAndrew.Bardsley@arm.com typedef AuxVector<IntType> auxv_t; 19310259SAndrew.Bardsley@arm.com 19410259SAndrew.Bardsley@arm.com std::vector<auxv_t> auxv; 19510259SAndrew.Bardsley@arm.com 19610259SAndrew.Bardsley@arm.com string filename; 19710259SAndrew.Bardsley@arm.com if (argv.size() < 1) 19810259SAndrew.Bardsley@arm.com filename = ""; 19910259SAndrew.Bardsley@arm.com else 20010259SAndrew.Bardsley@arm.com filename = argv[0]; 20111567Smitch.hayenga@arm.com 20210259SAndrew.Bardsley@arm.com // Even for a 32 bit process, the ABI says we still need to 20310259SAndrew.Bardsley@arm.com // maintain double word alignment of the stack pointer. 20411567Smitch.hayenga@arm.com uint64_t align = 16; 20510259SAndrew.Bardsley@arm.com 20611567Smitch.hayenga@arm.com // load object file into target memory 20710259SAndrew.Bardsley@arm.com objFile->loadSections(initVirtMem); 20810259SAndrew.Bardsley@arm.com 20910259SAndrew.Bardsley@arm.com enum hardwareCaps 21010259SAndrew.Bardsley@arm.com { 21110259SAndrew.Bardsley@arm.com M5_HWCAP_SPARC_FLUSH = 1, 21210259SAndrew.Bardsley@arm.com M5_HWCAP_SPARC_STBAR = 2, 21310259SAndrew.Bardsley@arm.com M5_HWCAP_SPARC_SWAP = 4, 21410259SAndrew.Bardsley@arm.com M5_HWCAP_SPARC_MULDIV = 8, 21510259SAndrew.Bardsley@arm.com M5_HWCAP_SPARC_V9 = 16, 21610259SAndrew.Bardsley@arm.com // This one should technically only be set 21710259SAndrew.Bardsley@arm.com // if there is a cheetah or cheetah_plus tlb, 21810259SAndrew.Bardsley@arm.com // but we'll use it all the time 21910259SAndrew.Bardsley@arm.com M5_HWCAP_SPARC_ULTRA3 = 32 22010259SAndrew.Bardsley@arm.com }; 22110259SAndrew.Bardsley@arm.com 22210259SAndrew.Bardsley@arm.com const int64_t hwcap = 22310259SAndrew.Bardsley@arm.com M5_HWCAP_SPARC_FLUSH | 22410259SAndrew.Bardsley@arm.com M5_HWCAP_SPARC_STBAR | 22510259SAndrew.Bardsley@arm.com M5_HWCAP_SPARC_SWAP | 22610259SAndrew.Bardsley@arm.com M5_HWCAP_SPARC_MULDIV | 22710259SAndrew.Bardsley@arm.com M5_HWCAP_SPARC_V9 | 22810259SAndrew.Bardsley@arm.com M5_HWCAP_SPARC_ULTRA3; 22910259SAndrew.Bardsley@arm.com 23010259SAndrew.Bardsley@arm.com // Setup the auxilliary vectors. These will already have endian conversion. 23110259SAndrew.Bardsley@arm.com // Auxilliary vectors are loaded only for elf formatted executables. 23210259SAndrew.Bardsley@arm.com ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 23310259SAndrew.Bardsley@arm.com if (elfObject) { 23410259SAndrew.Bardsley@arm.com // Bits which describe the system hardware capabilities 23510259SAndrew.Bardsley@arm.com auxv.push_back(auxv_t(M5_AT_HWCAP, hwcap)); 23610259SAndrew.Bardsley@arm.com // The system page size 23710259SAndrew.Bardsley@arm.com auxv.push_back(auxv_t(M5_AT_PAGESZ, SparcISA::PageBytes)); 23810259SAndrew.Bardsley@arm.com // Defined to be 100 in the kernel source. 23910259SAndrew.Bardsley@arm.com // Frequency at which times() increments 24010379Sandreas.hansson@arm.com auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 24110379Sandreas.hansson@arm.com // For statically linked executables, this is the virtual address of the 24210259SAndrew.Bardsley@arm.com // program header tables if they appear in the executable image 24310259SAndrew.Bardsley@arm.com auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 24410259SAndrew.Bardsley@arm.com // This is the size of a program header entry from the elf file. 24510259SAndrew.Bardsley@arm.com auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 24610259SAndrew.Bardsley@arm.com // This is the number of program headers from the original elf file. 24710259SAndrew.Bardsley@arm.com auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 24810259SAndrew.Bardsley@arm.com // This is the address of the elf "interpreter", It should be set 24910259SAndrew.Bardsley@arm.com // to 0 for regular executables. It should be something else 25010259SAndrew.Bardsley@arm.com // (not sure what) for dynamic libraries. 25110259SAndrew.Bardsley@arm.com auxv.push_back(auxv_t(M5_AT_BASE, 0)); 25210259SAndrew.Bardsley@arm.com // This is hardwired to 0 in the elf loading code in the kernel 25310259SAndrew.Bardsley@arm.com auxv.push_back(auxv_t(M5_AT_FLAGS, 0)); 25410259SAndrew.Bardsley@arm.com // The entry point to the program 25510259SAndrew.Bardsley@arm.com auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 25610259SAndrew.Bardsley@arm.com // Different user and group IDs 25710259SAndrew.Bardsley@arm.com auxv.push_back(auxv_t(M5_AT_UID, uid())); 25810259SAndrew.Bardsley@arm.com auxv.push_back(auxv_t(M5_AT_EUID, euid())); 25910259SAndrew.Bardsley@arm.com auxv.push_back(auxv_t(M5_AT_GID, gid())); 26010259SAndrew.Bardsley@arm.com auxv.push_back(auxv_t(M5_AT_EGID, egid())); 26110259SAndrew.Bardsley@arm.com // Whether to enable "secure mode" in the executable 26210259SAndrew.Bardsley@arm.com auxv.push_back(auxv_t(M5_AT_SECURE, 0)); 26310259SAndrew.Bardsley@arm.com } 26410259SAndrew.Bardsley@arm.com 26510259SAndrew.Bardsley@arm.com // Figure out how big the initial stack needs to be 26610259SAndrew.Bardsley@arm.com 26710259SAndrew.Bardsley@arm.com // The unaccounted for 8 byte 0 at the top of the stack 26810259SAndrew.Bardsley@arm.com int sentry_size = 8; 26910259SAndrew.Bardsley@arm.com 27010259SAndrew.Bardsley@arm.com // This is the name of the file which is present on the initial stack 27110259SAndrew.Bardsley@arm.com // It's purpose is to let the user space linker examine the original file. 27210259SAndrew.Bardsley@arm.com int file_name_size = filename.size() + 1; 27310259SAndrew.Bardsley@arm.com 27410259SAndrew.Bardsley@arm.com int env_data_size = 0; 27510259SAndrew.Bardsley@arm.com for (int i = 0; i < envp.size(); ++i) { 27610259SAndrew.Bardsley@arm.com env_data_size += envp[i].size() + 1; 27710259SAndrew.Bardsley@arm.com } 27810259SAndrew.Bardsley@arm.com int arg_data_size = 0; 27910259SAndrew.Bardsley@arm.com for (int i = 0; i < argv.size(); ++i) { 28010259SAndrew.Bardsley@arm.com arg_data_size += argv[i].size() + 1; 28110259SAndrew.Bardsley@arm.com } 28210259SAndrew.Bardsley@arm.com 28310259SAndrew.Bardsley@arm.com // The info_block. 28410259SAndrew.Bardsley@arm.com int base_info_block_size = 28510259SAndrew.Bardsley@arm.com sentry_size + file_name_size + env_data_size + arg_data_size; 28610259SAndrew.Bardsley@arm.com 28710259SAndrew.Bardsley@arm.com int info_block_size = roundUp(base_info_block_size, align); 28810259SAndrew.Bardsley@arm.com 28910259SAndrew.Bardsley@arm.com int info_block_padding = info_block_size - base_info_block_size; 29010259SAndrew.Bardsley@arm.com 29110259SAndrew.Bardsley@arm.com // Each auxilliary vector is two words 29210259SAndrew.Bardsley@arm.com int aux_array_size = intSize * 2 * (auxv.size() + 1); 29310259SAndrew.Bardsley@arm.com 29410259SAndrew.Bardsley@arm.com int envp_array_size = intSize * (envp.size() + 1); 29510259SAndrew.Bardsley@arm.com int argv_array_size = intSize * (argv.size() + 1); 29610259SAndrew.Bardsley@arm.com 29710259SAndrew.Bardsley@arm.com int argc_size = intSize; 29810259SAndrew.Bardsley@arm.com int window_save_size = intSize * 16; 29910259SAndrew.Bardsley@arm.com 30010259SAndrew.Bardsley@arm.com // Figure out the size of the contents of the actual initial frame 30110259SAndrew.Bardsley@arm.com int frame_size = 30210259SAndrew.Bardsley@arm.com aux_array_size + 30310259SAndrew.Bardsley@arm.com envp_array_size + 30410259SAndrew.Bardsley@arm.com argv_array_size + 30510259SAndrew.Bardsley@arm.com argc_size + 30610259SAndrew.Bardsley@arm.com window_save_size; 30710259SAndrew.Bardsley@arm.com 30810259SAndrew.Bardsley@arm.com // There needs to be padding after the auxiliary vector data so that the 30910259SAndrew.Bardsley@arm.com // very bottom of the stack is aligned properly. 31010259SAndrew.Bardsley@arm.com int aligned_partial_size = roundUp(frame_size, align); 31110259SAndrew.Bardsley@arm.com int aux_padding = aligned_partial_size - frame_size; 31210259SAndrew.Bardsley@arm.com 31310259SAndrew.Bardsley@arm.com int space_needed = 31410259SAndrew.Bardsley@arm.com info_block_size + 31510259SAndrew.Bardsley@arm.com aux_padding + 31610259SAndrew.Bardsley@arm.com frame_size; 31710259SAndrew.Bardsley@arm.com 31810259SAndrew.Bardsley@arm.com stack_min = stack_base - space_needed; 31910259SAndrew.Bardsley@arm.com stack_min = roundDown(stack_min, align); 32010259SAndrew.Bardsley@arm.com stack_size = stack_base - stack_min; 32110259SAndrew.Bardsley@arm.com 32210259SAndrew.Bardsley@arm.com // Allocate space for the stack 32310259SAndrew.Bardsley@arm.com allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize)); 32410259SAndrew.Bardsley@arm.com 32510259SAndrew.Bardsley@arm.com // map out initial stack contents 32610259SAndrew.Bardsley@arm.com IntType sentry_base = stack_base - sentry_size; 32710259SAndrew.Bardsley@arm.com IntType file_name_base = sentry_base - file_name_size; 32810259SAndrew.Bardsley@arm.com IntType env_data_base = file_name_base - env_data_size; 32910259SAndrew.Bardsley@arm.com IntType arg_data_base = env_data_base - arg_data_size; 33010259SAndrew.Bardsley@arm.com IntType auxv_array_base = arg_data_base - 33110259SAndrew.Bardsley@arm.com info_block_padding - aux_array_size - aux_padding; 33210259SAndrew.Bardsley@arm.com IntType envp_array_base = auxv_array_base - envp_array_size; 33310259SAndrew.Bardsley@arm.com IntType argv_array_base = envp_array_base - argv_array_size; 33410259SAndrew.Bardsley@arm.com IntType argc_base = argv_array_base - argc_size; 33510259SAndrew.Bardsley@arm.com#if TRACING_ON 33610259SAndrew.Bardsley@arm.com IntType window_save_base = argc_base - window_save_size; 33710259SAndrew.Bardsley@arm.com#endif 33810259SAndrew.Bardsley@arm.com 33910259SAndrew.Bardsley@arm.com DPRINTF(Stack, "The addresses of items on the initial stack:\n"); 34010259SAndrew.Bardsley@arm.com DPRINTF(Stack, "%#x - sentry NULL\n", sentry_base); 34110259SAndrew.Bardsley@arm.com DPRINTF(Stack, "filename = %s\n", filename); 34210259SAndrew.Bardsley@arm.com DPRINTF(Stack, "%#x - file name\n", file_name_base); 34310259SAndrew.Bardsley@arm.com DPRINTF(Stack, "%#x - env data\n", env_data_base); 34410259SAndrew.Bardsley@arm.com DPRINTF(Stack, "%#x - arg data\n", arg_data_base); 34510259SAndrew.Bardsley@arm.com DPRINTF(Stack, "%#x - auxv array\n", auxv_array_base); 34610259SAndrew.Bardsley@arm.com DPRINTF(Stack, "%#x - envp array\n", envp_array_base); 34710259SAndrew.Bardsley@arm.com DPRINTF(Stack, "%#x - argv array\n", argv_array_base); 34810259SAndrew.Bardsley@arm.com DPRINTF(Stack, "%#x - argc \n", argc_base); 34910259SAndrew.Bardsley@arm.com DPRINTF(Stack, "%#x - window save\n", window_save_base); 35010259SAndrew.Bardsley@arm.com DPRINTF(Stack, "%#x - stack min\n", stack_min); 35110259SAndrew.Bardsley@arm.com 35210259SAndrew.Bardsley@arm.com assert(window_save_base == stack_min); 35310259SAndrew.Bardsley@arm.com 35410259SAndrew.Bardsley@arm.com // write contents to stack 35510259SAndrew.Bardsley@arm.com 35610259SAndrew.Bardsley@arm.com // figure out argc 35710259SAndrew.Bardsley@arm.com IntType argc = argv.size(); 35810259SAndrew.Bardsley@arm.com IntType guestArgc = SparcISA::htog(argc); 35910259SAndrew.Bardsley@arm.com 36010259SAndrew.Bardsley@arm.com // Write out the sentry void * 36110259SAndrew.Bardsley@arm.com uint64_t sentry_NULL = 0; 36210259SAndrew.Bardsley@arm.com initVirtMem.writeBlob(sentry_base, 36310259SAndrew.Bardsley@arm.com (uint8_t*)&sentry_NULL, sentry_size); 36410259SAndrew.Bardsley@arm.com 36510259SAndrew.Bardsley@arm.com // Write the file name 36610259SAndrew.Bardsley@arm.com initVirtMem.writeString(file_name_base, filename.c_str()); 36710259SAndrew.Bardsley@arm.com 36810259SAndrew.Bardsley@arm.com // Copy the aux stuff 36910259SAndrew.Bardsley@arm.com for (int x = 0; x < auxv.size(); x++) { 37010259SAndrew.Bardsley@arm.com initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize, 37110259SAndrew.Bardsley@arm.com (uint8_t*)&(auxv[x].a_type), intSize); 37210259SAndrew.Bardsley@arm.com initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 37310259SAndrew.Bardsley@arm.com (uint8_t*)&(auxv[x].a_val), intSize); 37410259SAndrew.Bardsley@arm.com } 37510259SAndrew.Bardsley@arm.com 37610259SAndrew.Bardsley@arm.com // Write out the terminating zeroed auxilliary vector 37710259SAndrew.Bardsley@arm.com const IntType zero = 0; 37810259SAndrew.Bardsley@arm.com initVirtMem.writeBlob(auxv_array_base + intSize * 2 * auxv.size(), 37910259SAndrew.Bardsley@arm.com (uint8_t*)&zero, intSize); 38010259SAndrew.Bardsley@arm.com initVirtMem.writeBlob(auxv_array_base + intSize * (2 * auxv.size() + 1), 38110259SAndrew.Bardsley@arm.com (uint8_t*)&zero, intSize); 38210259SAndrew.Bardsley@arm.com 38310259SAndrew.Bardsley@arm.com copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 38410259SAndrew.Bardsley@arm.com copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 38510259SAndrew.Bardsley@arm.com 38610259SAndrew.Bardsley@arm.com initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); 38710259SAndrew.Bardsley@arm.com 38810259SAndrew.Bardsley@arm.com // Set up space for the trap handlers into the processes address space. 38910259SAndrew.Bardsley@arm.com // Since the stack grows down and there is reserved address space abov 39010259SAndrew.Bardsley@arm.com // it, we can put stuff above it and stay out of the way. 39110259SAndrew.Bardsley@arm.com fillStart = stack_base; 39210259SAndrew.Bardsley@arm.com spillStart = fillStart + sizeof(MachInst) * numFillInsts; 39310259SAndrew.Bardsley@arm.com 39410259SAndrew.Bardsley@arm.com ThreadContext *tc = system->getThreadContext(contextIds[0]); 39510259SAndrew.Bardsley@arm.com // Set up the thread context to start running the process 39610259SAndrew.Bardsley@arm.com // assert(NumArgumentRegs >= 2); 39710259SAndrew.Bardsley@arm.com // tc->setIntReg(ArgumentReg[0], argc); 39810259SAndrew.Bardsley@arm.com // tc->setIntReg(ArgumentReg[1], argv_array_base); 39910259SAndrew.Bardsley@arm.com tc->setIntReg(StackPointerReg, stack_min - StackBias); 40010259SAndrew.Bardsley@arm.com 40110259SAndrew.Bardsley@arm.com // %g1 is a pointer to a function that should be run at exit. Since we 40210259SAndrew.Bardsley@arm.com // don't have anything like that, it should be set to 0. 40310259SAndrew.Bardsley@arm.com tc->setIntReg(1, 0); 40410259SAndrew.Bardsley@arm.com 40510259SAndrew.Bardsley@arm.com tc->pcState(objFile->entryPoint()); 40610259SAndrew.Bardsley@arm.com 40710259SAndrew.Bardsley@arm.com // Align the "stack_min" to a page boundary. 40810259SAndrew.Bardsley@arm.com stack_min = roundDown(stack_min, pageSize); 40910259SAndrew.Bardsley@arm.com 41010259SAndrew.Bardsley@arm.com// num_processes++; 41110259SAndrew.Bardsley@arm.com} 41210259SAndrew.Bardsley@arm.com 41310259SAndrew.Bardsley@arm.comvoid 41410259SAndrew.Bardsley@arm.comSparc64LiveProcess::argsInit(int intSize, int pageSize) 41510259SAndrew.Bardsley@arm.com{ 41610259SAndrew.Bardsley@arm.com SparcLiveProcess::argsInit<uint64_t>(pageSize); 41710259SAndrew.Bardsley@arm.com 41810259SAndrew.Bardsley@arm.com // Stuff the trap handlers into the process address space 41910259SAndrew.Bardsley@arm.com initVirtMem.writeBlob(fillStart, 42010259SAndrew.Bardsley@arm.com (uint8_t*)fillHandler64, sizeof(MachInst) * numFillInsts); 42110259SAndrew.Bardsley@arm.com initVirtMem.writeBlob(spillStart, 42210259SAndrew.Bardsley@arm.com (uint8_t*)spillHandler64, sizeof(MachInst) * numSpillInsts); 42310259SAndrew.Bardsley@arm.com} 42410259SAndrew.Bardsley@arm.com 42510259SAndrew.Bardsley@arm.comvoid 42610259SAndrew.Bardsley@arm.comSparc32LiveProcess::argsInit(int intSize, int pageSize) 42710259SAndrew.Bardsley@arm.com{ 42810259SAndrew.Bardsley@arm.com SparcLiveProcess::argsInit<uint32_t>(pageSize); 42910259SAndrew.Bardsley@arm.com 43010259SAndrew.Bardsley@arm.com // Stuff the trap handlers into the process address space 43110259SAndrew.Bardsley@arm.com initVirtMem.writeBlob(fillStart, 43210259SAndrew.Bardsley@arm.com (uint8_t*)fillHandler32, sizeof(MachInst) * numFillInsts); 43310259SAndrew.Bardsley@arm.com initVirtMem.writeBlob(spillStart, 43410259SAndrew.Bardsley@arm.com (uint8_t*)spillHandler32, sizeof(MachInst) * numSpillInsts); 43510259SAndrew.Bardsley@arm.com} 43610259SAndrew.Bardsley@arm.com 43710259SAndrew.Bardsley@arm.comvoid Sparc32LiveProcess::flushWindows(ThreadContext *tc) 43810259SAndrew.Bardsley@arm.com{ 43910259SAndrew.Bardsley@arm.com IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); 44010259SAndrew.Bardsley@arm.com IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); 44110259SAndrew.Bardsley@arm.com IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); 44210259SAndrew.Bardsley@arm.com MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 44310259SAndrew.Bardsley@arm.com MiscReg origCWP = CWP; 44410259SAndrew.Bardsley@arm.com CWP = (CWP + Cansave + 2) % NWindows; 44510259SAndrew.Bardsley@arm.com while (NWindows - 2 - Cansave != 0) { 44610259SAndrew.Bardsley@arm.com if (Otherwin) { 44710259SAndrew.Bardsley@arm.com panic("Otherwin non-zero.\n"); 44810259SAndrew.Bardsley@arm.com } else { 44910259SAndrew.Bardsley@arm.com tc->setMiscReg(MISCREG_CWP, CWP); 45010259SAndrew.Bardsley@arm.com // Do the stores 45110259SAndrew.Bardsley@arm.com IntReg sp = tc->readIntReg(StackPointerReg); 45210259SAndrew.Bardsley@arm.com for (int index = 16; index < 32; index++) { 45310713Sandreas.hansson@arm.com uint32_t regVal = tc->readIntReg(index); 45410259SAndrew.Bardsley@arm.com regVal = htog(regVal); 45510259SAndrew.Bardsley@arm.com if (!tc->getMemProxy().tryWriteBlob( 45610259SAndrew.Bardsley@arm.com sp + (index - 16) * 4, (uint8_t *)®Val, 4)) { 45710259SAndrew.Bardsley@arm.com warn("Failed to save register to the stack when " 45810259SAndrew.Bardsley@arm.com "flushing windows.\n"); 45910259SAndrew.Bardsley@arm.com } 46010259SAndrew.Bardsley@arm.com } 46110259SAndrew.Bardsley@arm.com Canrestore--; 46210259SAndrew.Bardsley@arm.com Cansave++; 46310259SAndrew.Bardsley@arm.com CWP = (CWP + 1) % NWindows; 46410259SAndrew.Bardsley@arm.com } 46510259SAndrew.Bardsley@arm.com } 46610259SAndrew.Bardsley@arm.com tc->setIntReg(NumIntArchRegs + 3, Cansave); 46710259SAndrew.Bardsley@arm.com tc->setIntReg(NumIntArchRegs + 4, Canrestore); 46810259SAndrew.Bardsley@arm.com tc->setMiscReg(MISCREG_CWP, origCWP); 46910259SAndrew.Bardsley@arm.com} 47010259SAndrew.Bardsley@arm.com 47110259SAndrew.Bardsley@arm.comvoid 47210259SAndrew.Bardsley@arm.comSparc64LiveProcess::flushWindows(ThreadContext *tc) 47310259SAndrew.Bardsley@arm.com{ 47410259SAndrew.Bardsley@arm.com IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); 47510259SAndrew.Bardsley@arm.com IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); 47610259SAndrew.Bardsley@arm.com IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); 47710259SAndrew.Bardsley@arm.com MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 47810259SAndrew.Bardsley@arm.com MiscReg origCWP = CWP; 47910259SAndrew.Bardsley@arm.com CWP = (CWP + Cansave + 2) % NWindows; 48010259SAndrew.Bardsley@arm.com while (NWindows - 2 - Cansave != 0) { 48110259SAndrew.Bardsley@arm.com if (Otherwin) { 48210259SAndrew.Bardsley@arm.com panic("Otherwin non-zero.\n"); 48310259SAndrew.Bardsley@arm.com } else { 48410259SAndrew.Bardsley@arm.com tc->setMiscReg(MISCREG_CWP, CWP); 48510259SAndrew.Bardsley@arm.com // Do the stores 48610259SAndrew.Bardsley@arm.com IntReg sp = tc->readIntReg(StackPointerReg); 48710259SAndrew.Bardsley@arm.com for (int index = 16; index < 32; index++) { 48810259SAndrew.Bardsley@arm.com IntReg regVal = tc->readIntReg(index); 48910259SAndrew.Bardsley@arm.com regVal = htog(regVal); 49011567Smitch.hayenga@arm.com if (!tc->getMemProxy().tryWriteBlob( 49111567Smitch.hayenga@arm.com sp + 2047 + (index - 16) * 8, (uint8_t *)®Val, 8)) { 49210259SAndrew.Bardsley@arm.com warn("Failed to save register to the stack when " 49310259SAndrew.Bardsley@arm.com "flushing windows.\n"); 49410259SAndrew.Bardsley@arm.com } 49510259SAndrew.Bardsley@arm.com } 49610259SAndrew.Bardsley@arm.com Canrestore--; 49711567Smitch.hayenga@arm.com Cansave++; 49811567Smitch.hayenga@arm.com CWP = (CWP + 1) % NWindows; 49911567Smitch.hayenga@arm.com } 50011567Smitch.hayenga@arm.com } 50111567Smitch.hayenga@arm.com tc->setIntReg(NumIntArchRegs + 3, Cansave); 50211567Smitch.hayenga@arm.com tc->setIntReg(NumIntArchRegs + 4, Canrestore); 50311567Smitch.hayenga@arm.com tc->setMiscReg(MISCREG_CWP, origCWP); 50411567Smitch.hayenga@arm.com} 50511567Smitch.hayenga@arm.com 50610259SAndrew.Bardsley@arm.comIntReg 50710259SAndrew.Bardsley@arm.comSparc32LiveProcess::getSyscallArg(ThreadContext *tc, int &i) 50810259SAndrew.Bardsley@arm.com{ 50911567Smitch.hayenga@arm.com assert(i < 6); 51010259SAndrew.Bardsley@arm.com return bits(tc->readIntReg(FirstArgumentReg + i++), 31, 0); 51110259SAndrew.Bardsley@arm.com} 51210259SAndrew.Bardsley@arm.com 51311567Smitch.hayenga@arm.comvoid 51410259SAndrew.Bardsley@arm.comSparc32LiveProcess::setSyscallArg(ThreadContext *tc, int i, IntReg val) 51510259SAndrew.Bardsley@arm.com{ 51611567Smitch.hayenga@arm.com assert(i < 6); 51710259SAndrew.Bardsley@arm.com tc->setIntReg(FirstArgumentReg + i, bits(val, 31, 0)); 51810259SAndrew.Bardsley@arm.com} 51910259SAndrew.Bardsley@arm.com 52010259SAndrew.Bardsley@arm.comIntReg 52110259SAndrew.Bardsley@arm.comSparc64LiveProcess::getSyscallArg(ThreadContext *tc, int &i) 52211567Smitch.hayenga@arm.com{ 52311567Smitch.hayenga@arm.com assert(i < 6); 52410259SAndrew.Bardsley@arm.com return tc->readIntReg(FirstArgumentReg + i++); 52510259SAndrew.Bardsley@arm.com} 52611567Smitch.hayenga@arm.com 52711567Smitch.hayenga@arm.comvoid 52810259SAndrew.Bardsley@arm.comSparc64LiveProcess::setSyscallArg(ThreadContext *tc, int i, IntReg val) 52910259SAndrew.Bardsley@arm.com{ 53011567Smitch.hayenga@arm.com assert(i < 6); 53110259SAndrew.Bardsley@arm.com tc->setIntReg(FirstArgumentReg + i, val); 53210259SAndrew.Bardsley@arm.com} 53310259SAndrew.Bardsley@arm.com 53411567Smitch.hayenga@arm.comvoid 53510259SAndrew.Bardsley@arm.comSparcLiveProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) 53610259SAndrew.Bardsley@arm.com{ 53710259SAndrew.Bardsley@arm.com // check for error condition. SPARC syscall convention is to 53810259SAndrew.Bardsley@arm.com // indicate success/failure in reg the carry bit of the ccr 53910259SAndrew.Bardsley@arm.com // and put the return value itself in the standard return value reg (). 54010259SAndrew.Bardsley@arm.com PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); 54111567Smitch.hayenga@arm.com if (sysret.successful()) { 54210259SAndrew.Bardsley@arm.com // no error, clear XCC.C 54310259SAndrew.Bardsley@arm.com tc->setIntReg(NumIntArchRegs + 2, 54410259SAndrew.Bardsley@arm.com tc->readIntReg(NumIntArchRegs + 2) & 0xEE); 54510259SAndrew.Bardsley@arm.com IntReg val = sysret.returnValue(); 54610259SAndrew.Bardsley@arm.com if (pstate.am) 54710259SAndrew.Bardsley@arm.com val = bits(val, 31, 0); 54810259SAndrew.Bardsley@arm.com tc->setIntReg(ReturnValueReg, val); 54910259SAndrew.Bardsley@arm.com } else { 55010259SAndrew.Bardsley@arm.com // got an error, set XCC.C 55110259SAndrew.Bardsley@arm.com tc->setIntReg(NumIntArchRegs + 2, 55210259SAndrew.Bardsley@arm.com tc->readIntReg(NumIntArchRegs + 2) | 0x11); 55310259SAndrew.Bardsley@arm.com IntReg val = sysret.errnoValue(); 55410259SAndrew.Bardsley@arm.com if (pstate.am) 55510259SAndrew.Bardsley@arm.com val = bits(val, 31, 0); 55610259SAndrew.Bardsley@arm.com tc->setIntReg(ReturnValueReg, val); 55710259SAndrew.Bardsley@arm.com } 55810259SAndrew.Bardsley@arm.com} 55910259SAndrew.Bardsley@arm.com