isa_traits.hh revision 2650
12623SN/A/* 22623SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 292623SN/A#ifndef __ARCH_SPARC_ISA_TRAITS_HH__ 302623SN/A#define __ARCH_SPARC_ISA_TRAITS_HH__ 313170Sstever@eecs.umich.edu 323806Ssaidi@eecs.umich.edu#include "base/misc.hh" 332623SN/A#include "config/full_system.hh" 344040Ssaidi@eecs.umich.edu#include "sim/host.hh" 352623SN/A 362623SN/Aclass ExecContext; 373348Sbinkertn@umich.educlass FastCPU; 383348Sbinkertn@umich.edu//class FullCPU; 394762Snate@binkert.orgclass Checkpoint; 402901Ssaidi@eecs.umich.edu 412623SN/Aclass StaticInst; 422623SN/Aclass StaticInstPtr; 432623SN/A 442623SN/Anamespace BigEndianGuest {} 452623SN/A 465606Snate@binkert.org#if !FULL_SYSTEM 472623SN/Aclass SyscallReturn 482623SN/A{ 492623SN/A public: 502623SN/A template <class T> 512623SN/A SyscallReturn(T v, bool s) 522623SN/A { 532623SN/A retval = (uint64_t)v; 542623SN/A success = s; 552623SN/A } 562623SN/A 572623SN/A template <class T> 585336Shines@cs.fsu.edu SyscallReturn(T v) 592623SN/A { 604873Sstever@eecs.umich.edu success = (v >= 0); 612623SN/A retval = (uint64_t)v; 622623SN/A } 632856Srdreslin@umich.edu 642856Srdreslin@umich.edu ~SyscallReturn() {} 652856Srdreslin@umich.edu 662856Srdreslin@umich.edu SyscallReturn& operator=(const SyscallReturn& s) 672856Srdreslin@umich.edu { 682856Srdreslin@umich.edu retval = s.retval; 692856Srdreslin@umich.edu success = s.success; 704968Sacolyte@umich.edu return *this; 714968Sacolyte@umich.edu } 724968Sacolyte@umich.edu 734968Sacolyte@umich.edu bool successful() { return success; } 742856Srdreslin@umich.edu uint64_t value() { return retval; } 752856Srdreslin@umich.edu 762856Srdreslin@umich.edu private: 772623SN/A uint64_t retval; 782623SN/A bool success; 792623SN/A}; 802623SN/A 812623SN/A#endif 822623SN/A 832680Sktlim@umich.edu#if FULL_SYSTEM 842680Sktlim@umich.edu#include "arch/sparc/isa_fullsys_traits.hh" 852623SN/A#endif 862623SN/A 875714Shsul@eecs.umich.edunamespace SparcISA 882623SN/A{ 892623SN/A 904968Sacolyte@umich.edu // These enumerate all the registers for dependence tracking. 914968Sacolyte@umich.edu enum DependenceTags { 924968Sacolyte@umich.edu // 0..31 are the integer regs 0..31 934968Sacolyte@umich.edu // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 944968Sacolyte@umich.edu FP_Base_DepTag = 32, 954968Sacolyte@umich.edu Ctrl_Base_DepTag = 96, 965714Shsul@eecs.umich.edu //XXX These are here solely to get compilation and won't work 975712Shsul@eecs.umich.edu Fpcr_DepTag = 0, 985712Shsul@eecs.umich.edu Uniq_DepTag = 0 995712Shsul@eecs.umich.edu }; 1002623SN/A 1012623SN/A //This makes sure the big endian versions of certain functions are used. 1022623SN/A using namespace BigEndianGuest; 1033349Sbinkertn@umich.edu 1042623SN/A typedef uint32_t MachInst; 1053184Srdreslin@umich.edu typedef uint64_t ExtMachInst; 1062623SN/A 1072623SN/A const int NumIntRegs = 32; 1082623SN/A const int NumFloatRegs = 64; 1092623SN/A const int NumMiscRegs = 32; 1103349Sbinkertn@umich.edu 1112623SN/A // semantically meaningful register indices 1123310Srdreslin@umich.edu const int ZeroReg = 0; // architecturally meaningful 1133649Srdreslin@umich.edu // the rest of these depend on the ABI 1142623SN/A const int StackPointerReg = 14; 1152623SN/A const int ReturnAddressReg = 31; // post call, precall is 15 1162623SN/A const int ReturnValueReg = 8; // Post return, 24 is pre-return. 1173349Sbinkertn@umich.edu const int FramePointerReg = 30; 1182623SN/A const int ArgumentReg0 = 8; 1193184Srdreslin@umich.edu const int ArgumentReg1 = 9; 1203184Srdreslin@umich.edu const int ArgumentReg2 = 10; 1212623SN/A const int ArgumentReg3 = 11; 1222623SN/A const int ArgumentReg4 = 12; 1232623SN/A const int ArgumentReg5 = 13; 1242623SN/A // Some OS syscall use a second register (o1) to return a second value 1252623SN/A const int SyscallPseudoReturnReg = ArgumentReg1; 1263647Srdreslin@umich.edu 1273647Srdreslin@umich.edu //XXX These numbers are bogus 1283647Srdreslin@umich.edu const int MaxInstSrcRegs = 8; 1293647Srdreslin@umich.edu const int MaxInstDestRegs = 9; 1303647Srdreslin@umich.edu 1312626SN/A typedef uint64_t IntReg; 1323647Srdreslin@umich.edu 1332626SN/A // control register file contents 1342623SN/A typedef uint64_t MiscReg; 1352623SN/A 1362623SN/A typedef double FloatReg; 1372657Ssaidi@eecs.umich.edu typedef uint64_t FloatRegBits; 1382623SN/A 1392623SN/A //8K. This value is implmentation specific; and should probably 1402623SN/A //be somewhere else. 1412623SN/A const int LogVMPageSize = 13; 1422623SN/A const int VMPageSize = (1 << LogVMPageSize); 1434192Sktlim@umich.edu 1444192Sktlim@umich.edu //Why does both the previous set of constants and this one exist? 1454192Sktlim@umich.edu const int PageShift = 13; 1464192Sktlim@umich.edu const int PageBytes = ULL(1) << PageShift; 1474192Sktlim@umich.edu 1484192Sktlim@umich.edu const int BranchPredAddrShiftAmt = 2; 1494192Sktlim@umich.edu 1504192Sktlim@umich.edu const int MachineBytes = 8; 1515497Ssaidi@eecs.umich.edu const int WordBytes = 4; 1524192Sktlim@umich.edu const int HalfwordBytes = 2; 1534192Sktlim@umich.edu const int ByteBytes = 1; 1542623SN/A 1555529Snate@binkert.org void serialize(std::ostream & os); 1565487Snate@binkert.org 1575487Snate@binkert.org void unserialize(Checkpoint *cp, const std::string §ion); 1585487Snate@binkert.org 1594968Sacolyte@umich.edu StaticInstPtr decodeInst(ExtMachInst); 1604968Sacolyte@umich.edu 1612623SN/A // return a no-op instruction... used for instruction fetch faults 1622623SN/A extern const MachInst NoopMachInst; 1632623SN/A} 1643647Srdreslin@umich.edu 1653647Srdreslin@umich.edu#include "arch/sparc/regfile.hh" 1663647Srdreslin@umich.edu 1672623SN/Anamespace SparcISA 1682623SN/A{ 1692623SN/A 1702623SN/A#if !FULL_SYSTEM 1712623SN/A static inline void setSyscallReturn(SyscallReturn return_value, 1722623SN/A RegFile *regs) 1732623SN/A { 1742623SN/A // check for error condition. SPARC syscall convention is to 1752623SN/A // indicate success/failure in reg the carry bit of the ccr 1762623SN/A // and put the return value itself in the standard return value reg (). 1772915Sktlim@umich.edu if (return_value.successful()) { 1782915Sktlim@umich.edu // no error, clear XCC.C 1793145Shsul@eecs.umich.edu regs->setMiscReg(MISCREG_CCR, regs->readMiscReg(MISCREG_CCR) & 0xEF); 1802623SN/A regs->setIntReg(ReturnValueReg, return_value.value()); 1812623SN/A } else { 1822623SN/A // got an error, set XCC.C 1832623SN/A regs->setMiscReg(MISCREG_CCR, regs->readMiscReg(MISCREG_CCR) | 0x10); 1842623SN/A regs->setIntReg(ReturnValueReg, return_value.value()); 1852623SN/A } 1862623SN/A } 1872915Sktlim@umich.edu#endif 1882915Sktlim@umich.edu}; 1893145Shsul@eecs.umich.edu 1902915Sktlim@umich.edu#endif // __ARCH_SPARC_ISA_TRAITS_HH__ 1912915Sktlim@umich.edu