isa_traits.hh revision 2650
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __ARCH_SPARC_ISA_TRAITS_HH__ 30#define __ARCH_SPARC_ISA_TRAITS_HH__ 31 32#include "base/misc.hh" 33#include "config/full_system.hh" 34#include "sim/host.hh" 35 36class ExecContext; 37class FastCPU; 38//class FullCPU; 39class Checkpoint; 40 41class StaticInst; 42class StaticInstPtr; 43 44namespace BigEndianGuest {} 45 46#if !FULL_SYSTEM 47class SyscallReturn 48{ 49 public: 50 template <class T> 51 SyscallReturn(T v, bool s) 52 { 53 retval = (uint64_t)v; 54 success = s; 55 } 56 57 template <class T> 58 SyscallReturn(T v) 59 { 60 success = (v >= 0); 61 retval = (uint64_t)v; 62 } 63 64 ~SyscallReturn() {} 65 66 SyscallReturn& operator=(const SyscallReturn& s) 67 { 68 retval = s.retval; 69 success = s.success; 70 return *this; 71 } 72 73 bool successful() { return success; } 74 uint64_t value() { return retval; } 75 76 private: 77 uint64_t retval; 78 bool success; 79}; 80 81#endif 82 83#if FULL_SYSTEM 84#include "arch/sparc/isa_fullsys_traits.hh" 85#endif 86 87namespace SparcISA 88{ 89 90 // These enumerate all the registers for dependence tracking. 91 enum DependenceTags { 92 // 0..31 are the integer regs 0..31 93 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 94 FP_Base_DepTag = 32, 95 Ctrl_Base_DepTag = 96, 96 //XXX These are here solely to get compilation and won't work 97 Fpcr_DepTag = 0, 98 Uniq_DepTag = 0 99 }; 100 101 //This makes sure the big endian versions of certain functions are used. 102 using namespace BigEndianGuest; 103 104 typedef uint32_t MachInst; 105 typedef uint64_t ExtMachInst; 106 107 const int NumIntRegs = 32; 108 const int NumFloatRegs = 64; 109 const int NumMiscRegs = 32; 110 111 // semantically meaningful register indices 112 const int ZeroReg = 0; // architecturally meaningful 113 // the rest of these depend on the ABI 114 const int StackPointerReg = 14; 115 const int ReturnAddressReg = 31; // post call, precall is 15 116 const int ReturnValueReg = 8; // Post return, 24 is pre-return. 117 const int FramePointerReg = 30; 118 const int ArgumentReg0 = 8; 119 const int ArgumentReg1 = 9; 120 const int ArgumentReg2 = 10; 121 const int ArgumentReg3 = 11; 122 const int ArgumentReg4 = 12; 123 const int ArgumentReg5 = 13; 124 // Some OS syscall use a second register (o1) to return a second value 125 const int SyscallPseudoReturnReg = ArgumentReg1; 126 127 //XXX These numbers are bogus 128 const int MaxInstSrcRegs = 8; 129 const int MaxInstDestRegs = 9; 130 131 typedef uint64_t IntReg; 132 133 // control register file contents 134 typedef uint64_t MiscReg; 135 136 typedef double FloatReg; 137 typedef uint64_t FloatRegBits; 138 139 //8K. This value is implmentation specific; and should probably 140 //be somewhere else. 141 const int LogVMPageSize = 13; 142 const int VMPageSize = (1 << LogVMPageSize); 143 144 //Why does both the previous set of constants and this one exist? 145 const int PageShift = 13; 146 const int PageBytes = ULL(1) << PageShift; 147 148 const int BranchPredAddrShiftAmt = 2; 149 150 const int MachineBytes = 8; 151 const int WordBytes = 4; 152 const int HalfwordBytes = 2; 153 const int ByteBytes = 1; 154 155 void serialize(std::ostream & os); 156 157 void unserialize(Checkpoint *cp, const std::string §ion); 158 159 StaticInstPtr decodeInst(ExtMachInst); 160 161 // return a no-op instruction... used for instruction fetch faults 162 extern const MachInst NoopMachInst; 163} 164 165#include "arch/sparc/regfile.hh" 166 167namespace SparcISA 168{ 169 170#if !FULL_SYSTEM 171 static inline void setSyscallReturn(SyscallReturn return_value, 172 RegFile *regs) 173 { 174 // check for error condition. SPARC syscall convention is to 175 // indicate success/failure in reg the carry bit of the ccr 176 // and put the return value itself in the standard return value reg (). 177 if (return_value.successful()) { 178 // no error, clear XCC.C 179 regs->setMiscReg(MISCREG_CCR, regs->readMiscReg(MISCREG_CCR) & 0xEF); 180 regs->setIntReg(ReturnValueReg, return_value.value()); 181 } else { 182 // got an error, set XCC.C 183 regs->setMiscReg(MISCREG_CCR, regs->readMiscReg(MISCREG_CCR) | 0x10); 184 regs->setIntReg(ReturnValueReg, return_value.value()); 185 } 186 } 187#endif 188}; 189 190#endif // __ARCH_SPARC_ISA_TRAITS_HH__ 191