process.cc revision 13612
13115SN/A/* 23115SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 33115SN/A * Copyright (c) 2016 The University of Virginia 43115SN/A * All rights reserved. 53115SN/A * 63115SN/A * Redistribution and use in source and binary forms, with or without 73115SN/A * modification, are permitted provided that the following conditions are 83115SN/A * met: redistributions of source code must retain the above copyright 93115SN/A * notice, this list of conditions and the following disclaimer; 103115SN/A * redistributions in binary form must reproduce the above copyright 113115SN/A * notice, this list of conditions and the following disclaimer in the 123115SN/A * documentation and/or other materials provided with the distribution; 133115SN/A * neither the name of the copyright holders nor the names of its 143115SN/A * contributors may be used to endorse or promote products derived from 153115SN/A * this software without specific prior written permission. 163115SN/A * 173115SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 183115SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 193115SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 203115SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 213115SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 223115SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 233115SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 243115SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 253115SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 263115SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 273115SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 283115SN/A * 293115SN/A * Authors: Gabe Black 303115SN/A * Ali Saidi 313115SN/A * Korey Sewell 323115SN/A * Alec Roelke 333115SN/A */ 348229Snate@binkert.org#include "arch/riscv/process.hh" 358229Snate@binkert.org 363115SN/A#include <algorithm> 373115SN/A#include <cstddef> 383115SN/A#include <iostream> 393115SN/A#include <iterator> 408108SN/A#include <map> 418108SN/A#include <string> 428108SN/A#include <vector> 438108SN/A 448108SN/A#include "arch/riscv/isa.hh" 453115SN/A#include "arch/riscv/isa_traits.hh" 463115SN/A#include "arch/riscv/registers.hh" 473115SN/A#include "base/loader/elf_object.hh" 48#include "base/loader/object_file.hh" 49#include "base/logging.hh" 50#include "base/random.hh" 51#include "cpu/thread_context.hh" 52#include "debug/Stack.hh" 53#include "mem/page_table.hh" 54#include "params/Process.hh" 55#include "sim/aux_vector.hh" 56#include "sim/process.hh" 57#include "sim/process_impl.hh" 58#include "sim/syscall_return.hh" 59#include "sim/system.hh" 60 61using namespace std; 62using namespace RiscvISA; 63 64RiscvProcess::RiscvProcess(ProcessParams *params, ObjectFile *objFile) : 65 Process(params, 66 new EmulationPageTable(params->name, params->pid, PageBytes), 67 objFile) 68{ 69 fatal_if(params->useArchPT, "Arch page tables not implemented."); 70 const Addr stack_base = 0x7FFFFFFFFFFFFFFFL; 71 const Addr max_stack_size = 8 * 1024 * 1024; 72 const Addr next_thread_stack_base = stack_base - max_stack_size; 73 const Addr brk_point = roundUp(objFile->bssBase() + objFile->bssSize(), 74 PageBytes); 75 const Addr mmap_end = 0x4000000000000000L; 76 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size, 77 next_thread_stack_base, mmap_end); 78} 79 80void 81RiscvProcess::initState() 82{ 83 Process::initState(); 84 85 argsInit<uint64_t>(PageBytes); 86 for (ContextID ctx: contextIds) 87 system->getThreadContext(ctx)->setMiscRegNoEffect(MISCREG_PRV, PRV_U); 88} 89 90template<class IntType> void 91RiscvProcess::argsInit(int pageSize) 92{ 93 const int RandomBytes = 16; 94 95 updateBias(); 96 objFile->loadSections(initVirtMem); 97 ElfObject* elfObject = dynamic_cast<ElfObject*>(objFile); 98 memState->setStackMin(memState->getStackBase()); 99 100 // Determine stack size and populate auxv 101 Addr stack_top = memState->getStackMin(); 102 stack_top -= RandomBytes; 103 for (const string& arg: argv) 104 stack_top -= arg.size() + 1; 105 for (const string& env: envp) 106 stack_top -= env.size() + 1; 107 stack_top &= -sizeof(Addr); 108 109 vector<AuxVector<IntType>> auxv; 110 if (elfObject != nullptr) { 111 auxv.push_back({M5_AT_ENTRY, objFile->entryPoint()}); 112 auxv.push_back({M5_AT_PHNUM, elfObject->programHeaderCount()}); 113 auxv.push_back({M5_AT_PHENT, elfObject->programHeaderSize()}); 114 auxv.push_back({M5_AT_PHDR, elfObject->programHeaderTable()}); 115 auxv.push_back({M5_AT_PAGESZ, PageBytes}); 116 auxv.push_back({M5_AT_SECURE, 0}); 117 auxv.push_back({M5_AT_RANDOM, stack_top}); 118 auxv.push_back({M5_AT_NULL, 0}); 119 } 120 stack_top -= (1 + argv.size()) * sizeof(Addr) + 121 (1 + envp.size()) * sizeof(Addr) + 122 sizeof(Addr) + 2 * sizeof(IntType) * auxv.size(); 123 stack_top &= -2*sizeof(Addr); 124 memState->setStackSize(memState->getStackBase() - stack_top); 125 allocateMem(roundDown(stack_top, pageSize), 126 roundUp(memState->getStackSize(), pageSize)); 127 128 // Copy random bytes (for AT_RANDOM) to stack 129 memState->setStackMin(memState->getStackMin() - RandomBytes); 130 uint8_t at_random[RandomBytes]; 131 generate(begin(at_random), end(at_random), 132 [&]{ return random_mt.random(0, 0xFF); }); 133 initVirtMem.writeBlob(memState->getStackMin(), at_random, RandomBytes); 134 135 // Copy argv to stack 136 vector<Addr> argPointers; 137 for (const string& arg: argv) { 138 memState->setStackMin(memState->getStackMin() - (arg.size() + 1)); 139 initVirtMem.writeString(memState->getStackMin(), arg.c_str()); 140 argPointers.push_back(memState->getStackMin()); 141 if (DTRACE(Stack)) { 142 string wrote; 143 initVirtMem.readString(wrote, argPointers.back()); 144 DPRINTFN("Wrote arg \"%s\" to address %p\n", 145 wrote, (void*)memState->getStackMin()); 146 } 147 } 148 argPointers.push_back(0); 149 150 // Copy envp to stack 151 vector<Addr> envPointers; 152 for (const string& env: envp) { 153 memState->setStackMin(memState->getStackMin() - (env.size() + 1)); 154 initVirtMem.writeString(memState->getStackMin(), env.c_str()); 155 envPointers.push_back(memState->getStackMin()); 156 DPRINTF(Stack, "Wrote env \"%s\" to address %p\n", 157 env, (void*)memState->getStackMin()); 158 } 159 envPointers.push_back(0); 160 161 // Align stack 162 memState->setStackMin(memState->getStackMin() & -sizeof(Addr)); 163 164 // Calculate bottom of stack 165 memState->setStackMin(memState->getStackMin() - 166 ((1 + argv.size()) * sizeof(Addr) + 167 (1 + envp.size()) * sizeof(Addr) + 168 sizeof(Addr) + 2 * sizeof(IntType) * auxv.size())); 169 memState->setStackMin(memState->getStackMin() & -2*sizeof(Addr)); 170 Addr sp = memState->getStackMin(); 171 const auto pushOntoStack = 172 [this, &sp](const uint8_t* data, const size_t size) { 173 initVirtMem.writeBlob(sp, data, size); 174 sp += size; 175 }; 176 177 // Push argc and argv pointers onto stack 178 IntType argc = htog((IntType)argv.size()); 179 DPRINTF(Stack, "Wrote argc %d to address %p\n", 180 argv.size(), (void*)sp); 181 pushOntoStack((uint8_t*)&argc, sizeof(IntType)); 182 for (const Addr& argPointer: argPointers) { 183 DPRINTF(Stack, "Wrote argv pointer %p to address %p\n", 184 (void*)argPointer, (void*)sp); 185 pushOntoStack((uint8_t*)&argPointer, sizeof(Addr)); 186 } 187 188 // Push env pointers onto stack 189 for (const Addr& envPointer: envPointers) { 190 DPRINTF(Stack, "Wrote envp pointer %p to address %p\n", 191 (void*)envPointer, (void*)sp); 192 pushOntoStack((uint8_t*)&envPointer, sizeof(Addr)); 193 } 194 195 // Push aux vector onto stack 196 std::map<IntType, string> aux_keys = { 197 {M5_AT_ENTRY, "M5_AT_ENTRY"}, 198 {M5_AT_PHNUM, "M5_AT_PHNUM"}, 199 {M5_AT_PHENT, "M5_AT_PHENT"}, 200 {M5_AT_PHDR, "M5_AT_PHDR"}, 201 {M5_AT_PAGESZ, "M5_AT_PAGESZ"}, 202 {M5_AT_SECURE, "M5_AT_SECURE"}, 203 {M5_AT_RANDOM, "M5_AT_RANDOM"}, 204 {M5_AT_NULL, "M5_AT_NULL"} 205 }; 206 for (const AuxVector<IntType>& aux: auxv) { 207 DPRINTF(Stack, "Wrote aux key %s to address %p\n", 208 aux_keys[aux.getAuxType()], (void*)sp); 209 pushOntoStack((uint8_t*)&aux.getAuxType(), sizeof(IntType)); 210 DPRINTF(Stack, "Wrote aux value %x to address %p\n", 211 aux.getAuxVal(), (void*)sp); 212 pushOntoStack((uint8_t*)&aux.getAuxVal(), sizeof(IntType)); 213 } 214 215 ThreadContext *tc = system->getThreadContext(contextIds[0]); 216 tc->setIntReg(StackPointerReg, memState->getStackMin()); 217 tc->pcState(getStartPC()); 218 219 memState->setStackMin(roundDown(memState->getStackMin(), pageSize)); 220} 221 222RegVal 223RiscvProcess::getSyscallArg(ThreadContext *tc, int &i) 224{ 225 // If a larger index is requested than there are syscall argument 226 // registers, return 0 227 RegVal retval = 0; 228 if (i < SyscallArgumentRegs.size()) 229 retval = tc->readIntReg(SyscallArgumentRegs[i]); 230 i++; 231 return retval; 232} 233 234void 235RiscvProcess::setSyscallArg(ThreadContext *tc, int i, RegVal val) 236{ 237 tc->setIntReg(SyscallArgumentRegs[i], val); 238} 239 240void 241RiscvProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) 242{ 243 if (sysret.successful()) { 244 // no error 245 tc->setIntReg(SyscallPseudoReturnReg, sysret.returnValue()); 246 } else { 247 // got an error, return details 248 tc->setIntReg(SyscallPseudoReturnReg, sysret.errnoValue()); 249 } 250} 251