process.cc revision 13028 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2016 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 *          Ali Saidi
31 *          Korey Sewell
32 *          Alec Roelke
33 */
34#include "arch/riscv/process.hh"
35
36#include <algorithm>
37#include <cstddef>
38#include <iostream>
39#include <iterator>
40#include <map>
41#include <string>
42#include <vector>
43
44#include "arch/riscv/isa.hh"
45#include "arch/riscv/isa_traits.hh"
46#include "arch/riscv/registers.hh"
47#include "base/loader/elf_object.hh"
48#include "base/loader/object_file.hh"
49#include "base/logging.hh"
50#include "base/random.hh"
51#include "cpu/thread_context.hh"
52#include "debug/Stack.hh"
53#include "mem/page_table.hh"
54#include "params/Process.hh"
55#include "sim/aux_vector.hh"
56#include "sim/process.hh"
57#include "sim/process_impl.hh"
58#include "sim/syscall_return.hh"
59#include "sim/system.hh"
60
61using namespace std;
62using namespace RiscvISA;
63
64RiscvProcess::RiscvProcess(ProcessParams *params, ObjectFile *objFile) :
65        Process(params,
66                new EmulationPageTable(params->name, params->pid, PageBytes),
67                objFile)
68{
69    fatal_if(params->useArchPT, "Arch page tables not implemented.");
70    const Addr stack_base = 0x7FFFFFFFFFFFFFFFL;
71    const Addr max_stack_size = 8 * 1024 * 1024;
72    const Addr next_thread_stack_base = stack_base - max_stack_size;
73    const Addr brk_point = roundUp(objFile->bssBase() + objFile->bssSize(),
74            PageBytes);
75    const Addr mmap_end = 0x4000000000000000L;
76    memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
77            next_thread_stack_base, mmap_end);
78}
79
80void
81RiscvProcess::initState()
82{
83    Process::initState();
84
85    argsInit<uint64_t>(PageBytes);
86    for (ContextID ctx: contextIds)
87        system->getThreadContext(ctx)->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
88}
89
90template<class IntType> void
91RiscvProcess::argsInit(int pageSize)
92{
93    const int RandomBytes = 16;
94
95    updateBias();
96    objFile->loadSections(initVirtMem);
97    ElfObject* elfObject = dynamic_cast<ElfObject*>(objFile);
98    memState->setStackMin(memState->getStackBase());
99
100    // Determine stack size and populate auxv
101    Addr stack_top = memState->getStackMin();
102    stack_top -= RandomBytes;
103    for (const string& arg: argv)
104        stack_top -= arg.size() + 1;
105    for (const string& env: envp)
106        stack_top -= env.size() + 1;
107    stack_top &= -sizeof(Addr);
108
109    vector<AuxVector<IntType>> auxv;
110    if (elfObject != nullptr) {
111        auxv.push_back({M5_AT_ENTRY, objFile->entryPoint()});
112        auxv.push_back({M5_AT_PHNUM, elfObject->programHeaderCount()});
113        auxv.push_back({M5_AT_PHENT, elfObject->programHeaderSize()});
114        auxv.push_back({M5_AT_PHDR, elfObject->programHeaderTable()});
115        auxv.push_back({M5_AT_PAGESZ, PageBytes});
116        auxv.push_back({M5_AT_SECURE, 0});
117        auxv.push_back({M5_AT_RANDOM, stack_top});
118        auxv.push_back({M5_AT_NULL, 0});
119    }
120    stack_top -= (1 + argv.size()) * sizeof(Addr) +
121                   (1 + envp.size()) * sizeof(Addr) +
122                   sizeof(Addr) + 2 * sizeof(IntType) * auxv.size();
123    stack_top &= -2*sizeof(Addr);
124    memState->setStackSize(memState->getStackBase() - stack_top);
125    allocateMem(roundDown(stack_top, pageSize),
126            roundUp(memState->getStackSize(), pageSize));
127
128    // Copy random bytes (for AT_RANDOM) to stack
129    memState->setStackMin(memState->getStackMin() - RandomBytes);
130    uint8_t at_random[RandomBytes];
131    generate(begin(at_random), end(at_random),
132             [&]{ return random_mt.random(0, 0xFF); });
133    initVirtMem.writeBlob(memState->getStackMin(), at_random, RandomBytes);
134
135    // Copy argv to stack
136    vector<Addr> argPointers;
137    for (const string& arg: argv) {
138        memState->setStackMin(memState->getStackMin() - (arg.size() + 1));
139        initVirtMem.writeString(memState->getStackMin(), arg.c_str());
140        argPointers.push_back(memState->getStackMin());
141        if (DTRACE(Stack)) {
142            string wrote;
143            initVirtMem.readString(wrote, argPointers.back());
144            DPRINTFN("Wrote arg \"%s\" to address %p\n",
145                    wrote, (void*)memState->getStackMin());
146        }
147    }
148    argPointers.push_back(0);
149
150    // Copy envp to stack
151    vector<Addr> envPointers;
152    for (const string& env: envp) {
153        memState->setStackMin(memState->getStackMin() - (env.size() + 1));
154        initVirtMem.writeString(memState->getStackMin(), env.c_str());
155        envPointers.push_back(memState->getStackMin());
156        DPRINTF(Stack, "Wrote env \"%s\" to address %p\n",
157                env, (void*)memState->getStackMin());
158    }
159    envPointers.push_back(0);
160
161    // Align stack
162    memState->setStackMin(memState->getStackMin() & -sizeof(Addr));
163
164    // Calculate bottom of stack
165    memState->setStackMin(memState->getStackMin() -
166            ((1 + argv.size()) * sizeof(Addr) +
167             (1 + envp.size()) * sizeof(Addr) +
168             sizeof(Addr) + 2 * sizeof(IntType) * auxv.size()));
169    memState->setStackMin(memState->getStackMin() & -2*sizeof(Addr));
170    Addr sp = memState->getStackMin();
171    const auto pushOntoStack =
172        [this, &sp](const uint8_t* data, const size_t size) {
173            initVirtMem.writeBlob(sp, data, size);
174            sp += size;
175        };
176
177    // Push argc and argv pointers onto stack
178    IntType argc = htog((IntType)argv.size());
179    DPRINTF(Stack, "Wrote argc %d to address %p\n",
180            argv.size(), (void*)sp);
181    pushOntoStack((uint8_t*)&argc, sizeof(IntType));
182    for (const Addr& argPointer: argPointers) {
183        DPRINTF(Stack, "Wrote argv pointer %p to address %p\n",
184                (void*)argPointer, (void*)sp);
185        pushOntoStack((uint8_t*)&argPointer, sizeof(Addr));
186    }
187
188    // Push env pointers onto stack
189    for (const Addr& envPointer: envPointers) {
190        DPRINTF(Stack, "Wrote envp pointer %p to address %p\n",
191                (void*)envPointer, (void*)sp);
192        pushOntoStack((uint8_t*)&envPointer, sizeof(Addr));
193    }
194
195    // Push aux vector onto stack
196    std::map<IntType, string> aux_keys = {
197        {M5_AT_ENTRY, "M5_AT_ENTRY"},
198        {M5_AT_PHNUM, "M5_AT_PHNUM"},
199        {M5_AT_PHENT, "M5_AT_PHENT"},
200        {M5_AT_PHDR, "M5_AT_PHDR"},
201        {M5_AT_PAGESZ, "M5_AT_PAGESZ"},
202        {M5_AT_SECURE, "M5_AT_SECURE"},
203        {M5_AT_RANDOM, "M5_AT_RANDOM"},
204        {M5_AT_NULL, "M5_AT_NULL"}
205    };
206    for (const AuxVector<IntType>& aux: auxv) {
207        DPRINTF(Stack, "Wrote aux key %s to address %p\n",
208                aux_keys[aux.getAuxType()], (void*)sp);
209        pushOntoStack((uint8_t*)&aux.getAuxType(), sizeof(IntType));
210        DPRINTF(Stack, "Wrote aux value %x to address %p\n",
211                aux.getAuxVal(), (void*)sp);
212        pushOntoStack((uint8_t*)&aux.getAuxVal(), sizeof(IntType));
213    }
214
215    ThreadContext *tc = system->getThreadContext(contextIds[0]);
216    tc->setIntReg(StackPointerReg, memState->getStackMin());
217    tc->pcState(getStartPC());
218
219    memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
220}
221
222RiscvISA::IntReg
223RiscvProcess::getSyscallArg(ThreadContext *tc, int &i)
224{
225    // If a larger index is requested than there are syscall argument
226    // registers, return 0
227    RiscvISA::IntReg retval = 0;
228    if (i < SyscallArgumentRegs.size())
229        retval = tc->readIntReg(SyscallArgumentRegs[i]);
230    i++;
231    return retval;
232}
233
234void
235RiscvProcess::setSyscallArg(ThreadContext *tc, int i, RiscvISA::IntReg val)
236{
237    tc->setIntReg(SyscallArgumentRegs[i], val);
238}
239
240void
241RiscvProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
242{
243    if (sysret.successful()) {
244        // no error
245        tc->setIntReg(SyscallPseudoReturnReg, sysret.returnValue());
246    } else {
247        // got an error, return details
248        tc->setIntReg(SyscallPseudoReturnReg, sysret.errnoValue());
249    }
250}
251