process.cc revision 12448:b299e560f1d8 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2016 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 *          Ali Saidi
31 *          Korey Sewell
32 *          Alec Roelke
33 */
34#include "arch/riscv/process.hh"
35
36#include <algorithm>
37#include <cstddef>
38#include <iostream>
39#include <iterator>
40#include <map>
41#include <string>
42#include <vector>
43
44#include "arch/riscv/isa_traits.hh"
45#include "base/loader/elf_object.hh"
46#include "base/loader/object_file.hh"
47#include "base/logging.hh"
48#include "base/random.hh"
49#include "cpu/thread_context.hh"
50#include "debug/Stack.hh"
51#include "mem/page_table.hh"
52#include "params/Process.hh"
53#include "sim/aux_vector.hh"
54#include "sim/process.hh"
55#include "sim/process_impl.hh"
56#include "sim/syscall_return.hh"
57#include "sim/system.hh"
58
59using namespace std;
60using namespace RiscvISA;
61
62RiscvProcess::RiscvProcess(ProcessParams *params, ObjectFile *objFile) :
63        Process(params,
64                new EmulationPageTable(params->name, params->pid, PageBytes),
65                objFile)
66{
67    fatal_if(params->useArchPT, "Arch page tables not implemented.");
68    const Addr stack_base = 0x7FFFFFFFFFFFFFFFL;
69    const Addr max_stack_size = 8 * 1024 * 1024;
70    const Addr next_thread_stack_base = stack_base - max_stack_size;
71    const Addr brk_point = roundUp(objFile->bssBase() + objFile->bssSize(),
72            PageBytes);
73    const Addr mmap_end = 0x4000000000000000L;
74    memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
75            next_thread_stack_base, mmap_end);
76}
77
78void
79RiscvProcess::initState()
80{
81    Process::initState();
82
83    argsInit<uint64_t>(PageBytes);
84}
85
86template<class IntType> void
87RiscvProcess::argsInit(int pageSize)
88{
89    const int RandomBytes = 16;
90
91    updateBias();
92    objFile->loadSections(initVirtMem);
93    ElfObject* elfObject = dynamic_cast<ElfObject*>(objFile);
94    memState->setStackMin(memState->getStackBase());
95
96    // Determine stack size and populate auxv
97    Addr stack_top = memState->getStackMin();
98    stack_top -= RandomBytes;
99    for (const string& arg: argv)
100        stack_top -= arg.size() + 1;
101    for (const string& env: envp)
102        stack_top -= env.size() + 1;
103    stack_top &= -sizeof(Addr);
104
105    vector<AuxVector<IntType>> auxv;
106    if (elfObject != nullptr) {
107        auxv.push_back({M5_AT_ENTRY, objFile->entryPoint()});
108        auxv.push_back({M5_AT_PHNUM, elfObject->programHeaderCount()});
109        auxv.push_back({M5_AT_PHENT, elfObject->programHeaderSize()});
110        auxv.push_back({M5_AT_PHDR, elfObject->programHeaderTable()});
111        auxv.push_back({M5_AT_PAGESZ, PageBytes});
112        auxv.push_back({M5_AT_SECURE, 0});
113        auxv.push_back({M5_AT_RANDOM, stack_top});
114        auxv.push_back({M5_AT_NULL, 0});
115    }
116    stack_top -= (1 + argv.size()) * sizeof(Addr) +
117                   (1 + envp.size()) * sizeof(Addr) +
118                   sizeof(Addr) + 2 * sizeof(IntType) * auxv.size();
119    stack_top &= -2*sizeof(Addr);
120    memState->setStackSize(memState->getStackBase() - stack_top);
121    allocateMem(roundDown(stack_top, pageSize),
122            roundUp(memState->getStackSize(), pageSize));
123
124    // Copy random bytes (for AT_RANDOM) to stack
125    memState->setStackMin(memState->getStackMin() - RandomBytes);
126    uint8_t at_random[RandomBytes];
127    generate(begin(at_random), end(at_random),
128             [&]{ return random_mt.random(0, 0xFF); });
129    initVirtMem.writeBlob(memState->getStackMin(), at_random, RandomBytes);
130
131    // Copy argv to stack
132    vector<Addr> argPointers;
133    for (const string& arg: argv) {
134        memState->setStackMin(memState->getStackMin() - (arg.size() + 1));
135        initVirtMem.writeString(memState->getStackMin(), arg.c_str());
136        argPointers.push_back(memState->getStackMin());
137        if (DTRACE(Stack)) {
138            string wrote;
139            initVirtMem.readString(wrote, argPointers.back());
140            DPRINTFN("Wrote arg \"%s\" to address %p\n",
141                    wrote, (void*)memState->getStackMin());
142        }
143    }
144    argPointers.push_back(0);
145
146    // Copy envp to stack
147    vector<Addr> envPointers;
148    for (const string& env: envp) {
149        memState->setStackMin(memState->getStackMin() - (env.size() + 1));
150        initVirtMem.writeString(memState->getStackMin(), env.c_str());
151        envPointers.push_back(memState->getStackMin());
152        DPRINTF(Stack, "Wrote env \"%s\" to address %p\n",
153                env, (void*)memState->getStackMin());
154    }
155    envPointers.push_back(0);
156
157    // Align stack
158    memState->setStackMin(memState->getStackMin() & -sizeof(Addr));
159
160    // Calculate bottom of stack
161    memState->setStackMin(memState->getStackMin() -
162            ((1 + argv.size()) * sizeof(Addr) +
163             (1 + envp.size()) * sizeof(Addr) +
164             sizeof(Addr) + 2 * sizeof(IntType) * auxv.size()));
165    memState->setStackMin(memState->getStackMin() & -2*sizeof(Addr));
166    Addr sp = memState->getStackMin();
167    const auto pushOntoStack =
168        [this, &sp](const uint8_t* data, const size_t size) {
169            initVirtMem.writeBlob(sp, data, size);
170            sp += size;
171        };
172
173    // Push argc and argv pointers onto stack
174    IntType argc = htog((IntType)argv.size());
175    DPRINTF(Stack, "Wrote argc %d to address %p\n",
176            argv.size(), (void*)sp);
177    pushOntoStack((uint8_t*)&argc, sizeof(IntType));
178    for (const Addr& argPointer: argPointers) {
179        DPRINTF(Stack, "Wrote argv pointer %p to address %p\n",
180                (void*)argPointer, (void*)sp);
181        pushOntoStack((uint8_t*)&argPointer, sizeof(Addr));
182    }
183
184    // Push env pointers onto stack
185    for (const Addr& envPointer: envPointers) {
186        DPRINTF(Stack, "Wrote envp pointer %p to address %p\n",
187                (void*)envPointer, (void*)sp);
188        pushOntoStack((uint8_t*)&envPointer, sizeof(Addr));
189    }
190
191    // Push aux vector onto stack
192    std::map<IntType, string> aux_keys = {
193        {M5_AT_ENTRY, "M5_AT_ENTRY"},
194        {M5_AT_PHNUM, "M5_AT_PHNUM"},
195        {M5_AT_PHENT, "M5_AT_PHENT"},
196        {M5_AT_PHDR, "M5_AT_PHDR"},
197        {M5_AT_PAGESZ, "M5_AT_PAGESZ"},
198        {M5_AT_SECURE, "M5_AT_SECURE"},
199        {M5_AT_RANDOM, "M5_AT_RANDOM"},
200        {M5_AT_NULL, "M5_AT_NULL"}
201    };
202    for (const AuxVector<IntType>& aux: auxv) {
203        DPRINTF(Stack, "Wrote aux key %s to address %p\n",
204                aux_keys[aux.a_type], (void*)sp);
205        pushOntoStack((uint8_t*)&aux.a_type, sizeof(IntType));
206        DPRINTF(Stack, "Wrote aux value %x to address %p\n",
207                aux.a_val, (void*)sp);
208        pushOntoStack((uint8_t*)&aux.a_val, sizeof(IntType));
209    }
210
211    ThreadContext *tc = system->getThreadContext(contextIds[0]);
212    tc->setIntReg(StackPointerReg, memState->getStackMin());
213    tc->pcState(getStartPC());
214
215    memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
216}
217
218RiscvISA::IntReg
219RiscvProcess::getSyscallArg(ThreadContext *tc, int &i)
220{
221    // If a larger index is requested than there are syscall argument
222    // registers, return 0
223    RiscvISA::IntReg retval = 0;
224    if (i < SyscallArgumentRegs.size())
225        retval = tc->readIntReg(SyscallArgumentRegs[i]);
226    i++;
227    return retval;
228}
229
230void
231RiscvProcess::setSyscallArg(ThreadContext *tc, int i, RiscvISA::IntReg val)
232{
233    tc->setIntReg(SyscallArgumentRegs[i], val);
234}
235
236void
237RiscvProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
238{
239    if (sysret.successful()) {
240        // no error
241        tc->setIntReg(SyscallPseudoReturnReg, sysret.returnValue());
242    } else {
243        // got an error, return details
244        tc->setIntReg(SyscallPseudoReturnReg, sysret.errnoValue());
245    }
246}
247