process.cc revision 11970:98a9b0f154f6 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2016 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 *          Ali Saidi
31 *          Korey Sewell
32 *          Alec Roelke
33 */
34#include "arch/riscv/process.hh"
35
36#include <algorithm>
37#include <cstddef>
38#include <iostream>
39#include <map>
40#include <string>
41#include <vector>
42
43#include "arch/riscv/isa_traits.hh"
44#include "base/loader/elf_object.hh"
45#include "base/loader/object_file.hh"
46#include "base/misc.hh"
47#include "cpu/thread_context.hh"
48#include "debug/Stack.hh"
49#include "mem/page_table.hh"
50#include "params/Process.hh"
51#include "sim/aux_vector.hh"
52#include "sim/process.hh"
53#include "sim/process_impl.hh"
54#include "sim/syscall_return.hh"
55#include "sim/system.hh"
56
57using namespace std;
58using namespace RiscvISA;
59
60RiscvProcess::RiscvProcess(ProcessParams * params,
61    ObjectFile *objFile) : Process(params, objFile)
62{
63    const Addr stack_base = 0x7FFFFFFFFFFFFFFFL;
64    const Addr max_stack_size = PageBytes * 64;
65    const Addr next_thread_stack_base = stack_base - max_stack_size;
66    const Addr brk_point = roundUp(objFile->bssBase() + objFile->bssSize(),
67            PageBytes);
68    const Addr mmap_end = 0x4000000000000000L;
69    memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
70            next_thread_stack_base, mmap_end);
71}
72
73void
74RiscvProcess::initState()
75{
76    Process::initState();
77
78    argsInit<uint64_t>(PageBytes);
79}
80
81template<class IntType> void
82RiscvProcess::argsInit(int pageSize)
83{
84    updateBias();
85    objFile->loadSections(initVirtMem);
86    ElfObject* elfObject = dynamic_cast<ElfObject*>(objFile);
87    memState->setStackMin(memState->getStackBase());
88
89    // Determine stack size and populate auxv
90    Addr stack_top = memState->getStackMin();
91    for (const string& arg: argv)
92        stack_top -= arg.size() + 1;
93    for (const string& env: envp)
94        stack_top -= env.size() + 1;
95    stack_top &= -sizeof(Addr);
96
97    vector<AuxVector<IntType>> auxv;
98    if (elfObject != nullptr) {
99        auxv.push_back({M5_AT_ENTRY, objFile->entryPoint()});
100        auxv.push_back({M5_AT_PHNUM, elfObject->programHeaderCount()});
101        auxv.push_back({M5_AT_PHENT, elfObject->programHeaderSize()});
102        auxv.push_back({M5_AT_PHDR, elfObject->programHeaderTable()});
103        auxv.push_back({M5_AT_PAGESZ, PageBytes});
104        auxv.push_back({M5_AT_SECURE, 0});
105        auxv.push_back({M5_AT_RANDOM, stack_top});
106        auxv.push_back({M5_AT_NULL, 0});
107    }
108    stack_top -= (1 + argv.size()) * sizeof(Addr) +
109                   (1 + envp.size()) * sizeof(Addr) +
110                   sizeof(Addr) + 2 * sizeof(IntType) * auxv.size();
111    stack_top &= -2*sizeof(Addr);
112    memState->setStackSize(memState->getStackBase() - stack_top);
113    allocateMem(roundDown(stack_top, pageSize),
114            roundUp(memState->getStackSize(), pageSize));
115
116    // Copy argv to stack
117    vector<Addr> argPointers;
118    for (const string& arg: argv) {
119        memState->setStackMin(memState->getStackMin() - (arg.size() + 1));
120        initVirtMem.writeString(memState->getStackMin(), arg.c_str());
121        argPointers.push_back(memState->getStackMin());
122        if (DTRACE(Stack)) {
123            string wrote;
124            initVirtMem.readString(wrote, argPointers.back());
125            DPRINTFN("Wrote arg \"%s\" to address %p\n",
126                    wrote, (void*)memState->getStackMin());
127        }
128    }
129    argPointers.push_back(0);
130
131    // Copy envp to stack
132    vector<Addr> envPointers;
133    for (const string& env: envp) {
134        memState->setStackMin(memState->getStackMin() - (env.size() + 1));
135        initVirtMem.writeString(memState->getStackMin(), env.c_str());
136        envPointers.push_back(memState->getStackMin());
137        DPRINTF(Stack, "Wrote env \"%s\" to address %p\n",
138                env, (void*)memState->getStackMin());
139    }
140    envPointers.push_back(0);
141
142    // Align stack
143    memState->setStackMin(memState->getStackMin() & -sizeof(Addr));
144
145    // Calculate bottom of stack
146    memState->setStackMin(memState->getStackMin() -
147            ((1 + argv.size()) * sizeof(Addr) +
148             (1 + envp.size()) * sizeof(Addr) +
149             sizeof(Addr) + 2 * sizeof(IntType) * auxv.size()));
150    memState->setStackMin(memState->getStackMin() & -2*sizeof(Addr));
151    Addr sp = memState->getStackMin();
152    const auto pushOntoStack =
153        [this, &sp](const uint8_t* data, const size_t size) {
154            initVirtMem.writeBlob(sp, data, size);
155            sp += size;
156        };
157
158    // Push argc and argv pointers onto stack
159    IntType argc = htog((IntType)argv.size());
160    DPRINTF(Stack, "Wrote argc %d to address %p\n",
161            argv.size(), (void*)sp);
162    pushOntoStack((uint8_t*)&argc, sizeof(IntType));
163    for (const Addr& argPointer: argPointers) {
164        DPRINTF(Stack, "Wrote argv pointer %p to address %p\n",
165                (void*)argPointer, (void*)sp);
166        pushOntoStack((uint8_t*)&argPointer, sizeof(Addr));
167    }
168
169    // Push env pointers onto stack
170    for (const Addr& envPointer: envPointers) {
171        DPRINTF(Stack, "Wrote envp pointer %p to address %p\n",
172                (void*)envPointer, (void*)sp);
173        pushOntoStack((uint8_t*)&envPointer, sizeof(Addr));
174    }
175
176    // Push aux vector onto stack
177    std::map<IntType, string> aux_keys = {
178        {M5_AT_ENTRY, "M5_AT_ENTRY"},
179        {M5_AT_PHNUM, "M5_AT_PHNUM"},
180        {M5_AT_PHENT, "M5_AT_PHENT"},
181        {M5_AT_PHDR, "M5_AT_PHDR"},
182        {M5_AT_PAGESZ, "M5_AT_PAGESZ"},
183        {M5_AT_SECURE, "M5_AT_SECURE"},
184        {M5_AT_RANDOM, "M5_AT_RANDOM"},
185        {M5_AT_NULL, "M5_AT_NULL"}
186    };
187    for (const AuxVector<IntType>& aux: auxv) {
188        DPRINTF(Stack, "Wrote aux key %s to address %p\n",
189                aux_keys[aux.a_type], (void*)sp);
190        pushOntoStack((uint8_t*)&aux.a_type, sizeof(IntType));
191        DPRINTF(Stack, "Wrote aux value %x to address %p\n",
192                aux.a_val, (void*)sp);
193        pushOntoStack((uint8_t*)&aux.a_val, sizeof(IntType));
194    }
195
196    ThreadContext *tc = system->getThreadContext(contextIds[0]);
197    tc->setIntReg(StackPointerReg, memState->getStackMin());
198    tc->pcState(getStartPC());
199
200    memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
201}
202
203RiscvISA::IntReg
204RiscvProcess::getSyscallArg(ThreadContext *tc, int &i)
205{
206    // RISC-V only has four system call argument registers by convention, so
207    // if a larger index is requested return 0
208    RiscvISA::IntReg retval = 0;
209    if (i < 4)
210        retval = tc->readIntReg(SyscallArgumentRegs[i]);
211    i++;
212    return retval;
213}
214
215void
216RiscvProcess::setSyscallArg(ThreadContext *tc, int i, RiscvISA::IntReg val)
217{
218    tc->setIntReg(SyscallArgumentRegs[i], val);
219}
220
221void
222RiscvProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
223{
224    if (sysret.successful()) {
225        // no error
226        tc->setIntReg(SyscallPseudoReturnReg, sysret.returnValue());
227    } else {
228        // got an error, return details
229        tc->setIntReg(SyscallPseudoReturnReg, sysret.errnoValue());
230    }
231}
232