process.cc revision 11964 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2016 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 *          Ali Saidi
31 *          Korey Sewell
32 *          Alec Roelke
33 */
34#include "arch/riscv/process.hh"
35
36#include <algorithm>
37#include <cstddef>
38#include <iostream>
39#include <map>
40#include <string>
41#include <vector>
42
43#include "arch/riscv/isa_traits.hh"
44#include "base/loader/elf_object.hh"
45#include "base/loader/object_file.hh"
46#include "base/misc.hh"
47#include "cpu/thread_context.hh"
48#include "debug/Stack.hh"
49#include "mem/page_table.hh"
50#include "params/Process.hh"
51#include "sim/aux_vector.hh"
52#include "sim/process.hh"
53#include "sim/process_impl.hh"
54#include "sim/syscall_return.hh"
55#include "sim/system.hh"
56
57using namespace std;
58using namespace RiscvISA;
59
60RiscvProcess::RiscvProcess(ProcessParams * params,
61    ObjectFile *objFile) : Process(params, objFile)
62{
63    const Addr mem_base = 0x80000000;
64    const Addr stack_base = mem_base;
65    const Addr max_stack_size = PageBytes * 64;
66    const Addr next_thread_stack_base = stack_base - max_stack_size;
67    const Addr brk_point = roundUp(objFile->bssBase() + objFile->bssSize(),
68            PageBytes);
69    const Addr mmap_end = mem_base;
70    memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
71            next_thread_stack_base, mmap_end);
72}
73
74void
75RiscvProcess::initState()
76{
77    Process::initState();
78
79    argsInit<uint64_t>(PageBytes);
80}
81
82template<class IntType> void
83RiscvProcess::argsInit(int pageSize)
84{
85    updateBias();
86    objFile->loadSections(initVirtMem);
87    ElfObject* elfObject = dynamic_cast<ElfObject*>(objFile);
88    memState->setStackMin(memState->getStackBase());
89
90    // Determine stack size and populate auxv
91    Addr stack_top = memState->getStackMin();
92    for (const string& arg: argv)
93        stack_top -= arg.size() + 1;
94    for (const string& env: envp)
95        stack_top -= env.size() + 1;
96    stack_top &= -sizeof(Addr);
97
98    vector<AuxVector<IntType>> auxv;
99    if (elfObject != nullptr) {
100        auxv.push_back({M5_AT_ENTRY, objFile->entryPoint()});
101        auxv.push_back({M5_AT_PHNUM, elfObject->programHeaderCount()});
102        auxv.push_back({M5_AT_PHENT, elfObject->programHeaderSize()});
103        auxv.push_back({M5_AT_PHDR, elfObject->programHeaderTable()});
104        auxv.push_back({M5_AT_PAGESZ, PageBytes});
105        auxv.push_back({M5_AT_SECURE, 0});
106        auxv.push_back({M5_AT_RANDOM, stack_top});
107        auxv.push_back({M5_AT_NULL, 0});
108    }
109    stack_top -= (1 + argv.size()) * sizeof(Addr) +
110                   (1 + envp.size()) * sizeof(Addr) +
111                   sizeof(Addr) + 2 * sizeof(IntType) * auxv.size();
112    stack_top &= -2*sizeof(Addr);
113    memState->setStackSize(memState->getStackBase() - stack_top);
114    allocateMem(roundDown(stack_top, pageSize),
115            roundUp(memState->getStackSize(), pageSize));
116
117    // Copy argv to stack
118    vector<Addr> argPointers;
119    for (const string& arg: argv) {
120        memState->setStackMin(memState->getStackMin() - (arg.size() + 1));
121        initVirtMem.writeString(memState->getStackMin(), arg.c_str());
122        argPointers.push_back(memState->getStackMin());
123        if (DTRACE(Stack)) {
124            string wrote;
125            initVirtMem.readString(wrote, argPointers.back());
126            DPRINTFN("Wrote arg \"%s\" to address %p\n",
127                    wrote, (void*)memState->getStackMin());
128        }
129    }
130    argPointers.push_back(0);
131
132    // Copy envp to stack
133    vector<Addr> envPointers;
134    for (const string& env: envp) {
135        memState->setStackMin(memState->getStackMin() - (env.size() + 1));
136        initVirtMem.writeString(memState->getStackMin(), env.c_str());
137        envPointers.push_back(memState->getStackMin());
138        DPRINTF(Stack, "Wrote env \"%s\" to address %p\n",
139                env, (void*)memState->getStackMin());
140    }
141    envPointers.push_back(0);
142
143    // Align stack
144    memState->setStackMin(memState->getStackMin() & -sizeof(Addr));
145
146    // Calculate bottom of stack
147    memState->setStackMin(memState->getStackMin() -
148            ((1 + argv.size()) * sizeof(Addr) +
149             (1 + envp.size()) * sizeof(Addr) +
150             sizeof(Addr) + 2 * sizeof(IntType) * auxv.size()));
151    memState->setStackMin(memState->getStackMin() & -2*sizeof(Addr));
152    Addr sp = memState->getStackMin();
153    const auto pushOntoStack =
154        [this, &sp](const uint8_t* data, const size_t size) {
155            initVirtMem.writeBlob(sp, data, size);
156            sp += size;
157        };
158
159    // Push argc and argv pointers onto stack
160    IntType argc = htog((IntType)argv.size());
161    DPRINTF(Stack, "Wrote argc %d to address %p\n",
162            argv.size(), (void*)sp);
163    pushOntoStack((uint8_t*)&argc, sizeof(IntType));
164    for (const Addr& argPointer: argPointers) {
165        DPRINTF(Stack, "Wrote argv pointer %p to address %p\n",
166                (void*)argPointer, (void*)sp);
167        pushOntoStack((uint8_t*)&argPointer, sizeof(Addr));
168    }
169
170    // Push env pointers onto stack
171    for (const Addr& envPointer: envPointers) {
172        DPRINTF(Stack, "Wrote envp pointer %p to address %p\n",
173                (void*)envPointer, (void*)sp);
174        pushOntoStack((uint8_t*)&envPointer, sizeof(Addr));
175    }
176
177    // Push aux vector onto stack
178    std::map<IntType, string> aux_keys = {
179        {M5_AT_ENTRY, "M5_AT_ENTRY"},
180        {M5_AT_PHNUM, "M5_AT_PHNUM"},
181        {M5_AT_PHENT, "M5_AT_PHENT"},
182        {M5_AT_PHDR, "M5_AT_PHDR"},
183        {M5_AT_PAGESZ, "M5_AT_PAGESZ"},
184        {M5_AT_SECURE, "M5_AT_SECURE"},
185        {M5_AT_RANDOM, "M5_AT_RANDOM"},
186        {M5_AT_NULL, "M5_AT_NULL"}
187    };
188    for (const AuxVector<IntType>& aux: auxv) {
189        DPRINTF(Stack, "Wrote aux key %s to address %p\n",
190                aux_keys[aux.a_type], (void*)sp);
191        pushOntoStack((uint8_t*)&aux.a_type, sizeof(IntType));
192        DPRINTF(Stack, "Wrote aux value %x to address %p\n",
193                aux.a_val, (void*)sp);
194        pushOntoStack((uint8_t*)&aux.a_val, sizeof(IntType));
195    }
196
197    ThreadContext *tc = system->getThreadContext(contextIds[0]);
198    tc->setIntReg(StackPointerReg, memState->getStackMin());
199    tc->pcState(getStartPC());
200
201    memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
202}
203
204RiscvISA::IntReg
205RiscvProcess::getSyscallArg(ThreadContext *tc, int &i)
206{
207    // RISC-V only has four system call argument registers by convention, so
208    // if a larger index is requested return 0
209    RiscvISA::IntReg retval = 0;
210    if (i < 4)
211        retval = tc->readIntReg(SyscallArgumentRegs[i]);
212    i++;
213    return retval;
214}
215
216void
217RiscvProcess::setSyscallArg(ThreadContext *tc, int i, RiscvISA::IntReg val)
218{
219    tc->setIntReg(SyscallArgumentRegs[i], val);
220}
221
222void
223RiscvProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
224{
225    if (sysret.successful()) {
226        // no error
227        tc->setIntReg(SyscallPseudoReturnReg, sysret.returnValue());
228    } else {
229        // got an error, return details
230        tc->setIntReg(SyscallPseudoReturnReg, sysret.errnoValue());
231    }
232}
233