faults.hh revision 12849
111723Sar4jc@virginia.edu/* 211723Sar4jc@virginia.edu * Copyright (c) 2016 RISC-V Foundation 311723Sar4jc@virginia.edu * Copyright (c) 2016 The University of Virginia 412808Srobert.scheffel1@tu-dresden.de * Copyright (c) 2018 TU Dresden 511723Sar4jc@virginia.edu * All rights reserved. 611723Sar4jc@virginia.edu * 711723Sar4jc@virginia.edu * Redistribution and use in source and binary forms, with or without 811723Sar4jc@virginia.edu * modification, are permitted provided that the following conditions are 911723Sar4jc@virginia.edu * met: redistributions of source code must retain the above copyright 1011723Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer; 1111723Sar4jc@virginia.edu * redistributions in binary form must reproduce the above copyright 1211723Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer in the 1311723Sar4jc@virginia.edu * documentation and/or other materials provided with the distribution; 1411723Sar4jc@virginia.edu * neither the name of the copyright holders nor the names of its 1511723Sar4jc@virginia.edu * contributors may be used to endorse or promote products derived from 1611723Sar4jc@virginia.edu * this software without specific prior written permission. 1711723Sar4jc@virginia.edu * 1811723Sar4jc@virginia.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1911723Sar4jc@virginia.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2011723Sar4jc@virginia.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2111723Sar4jc@virginia.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2211723Sar4jc@virginia.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2311723Sar4jc@virginia.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2411723Sar4jc@virginia.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2511723Sar4jc@virginia.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2611723Sar4jc@virginia.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2711723Sar4jc@virginia.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2811723Sar4jc@virginia.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2911723Sar4jc@virginia.edu * 3011723Sar4jc@virginia.edu * Authors: Alec Roelke 3112808Srobert.scheffel1@tu-dresden.de * Robert Scheffel 3211723Sar4jc@virginia.edu */ 3311723Sar4jc@virginia.edu 3411723Sar4jc@virginia.edu#ifndef __ARCH_RISCV_FAULTS_HH__ 3511723Sar4jc@virginia.edu#define __ARCH_RISCV_FAULTS_HH__ 3611723Sar4jc@virginia.edu 3711723Sar4jc@virginia.edu#include <string> 3811723Sar4jc@virginia.edu 3912848Sar4jc@virginia.edu#include "arch/riscv/registers.hh" 4011723Sar4jc@virginia.edu#include "cpu/thread_context.hh" 4111723Sar4jc@virginia.edu#include "sim/faults.hh" 4211723Sar4jc@virginia.edu 4311723Sar4jc@virginia.edunamespace RiscvISA 4411723Sar4jc@virginia.edu{ 4511723Sar4jc@virginia.edu 4612848Sar4jc@virginia.eduenum FloatException : MiscReg { 4712848Sar4jc@virginia.edu FloatInexact = 0x1, 4812848Sar4jc@virginia.edu FloatUnderflow = 0x2, 4912848Sar4jc@virginia.edu FloatOverflow = 0x4, 5012848Sar4jc@virginia.edu FloatDivZero = 0x8, 5112848Sar4jc@virginia.edu FloatInvalid = 0x10 5212848Sar4jc@virginia.edu}; 5311725Sar4jc@virginia.edu 5412848Sar4jc@virginia.eduenum ExceptionCode : MiscReg { 5511723Sar4jc@virginia.edu INST_ADDR_MISALIGNED = 0, 5611723Sar4jc@virginia.edu INST_ACCESS = 1, 5711723Sar4jc@virginia.edu INST_ILLEGAL = 2, 5811723Sar4jc@virginia.edu BREAKPOINT = 3, 5911723Sar4jc@virginia.edu LOAD_ADDR_MISALIGNED = 4, 6011723Sar4jc@virginia.edu LOAD_ACCESS = 5, 6111723Sar4jc@virginia.edu STORE_ADDR_MISALIGNED = 6, 6211723Sar4jc@virginia.edu AMO_ADDR_MISALIGNED = 6, 6311723Sar4jc@virginia.edu STORE_ACCESS = 7, 6411723Sar4jc@virginia.edu AMO_ACCESS = 7, 6511723Sar4jc@virginia.edu ECALL_USER = 8, 6611723Sar4jc@virginia.edu ECALL_SUPER = 9, 6712848Sar4jc@virginia.edu ECALL_MACHINE = 11, 6812848Sar4jc@virginia.edu INST_PAGE = 12, 6912848Sar4jc@virginia.edu LOAD_PAGE = 13, 7012848Sar4jc@virginia.edu STORE_PAGE = 15, 7112848Sar4jc@virginia.edu AMO_PAGE = 15 7211723Sar4jc@virginia.edu}; 7311723Sar4jc@virginia.edu 7412848Sar4jc@virginia.edu/** 7512848Sar4jc@virginia.edu * These fields are specified in the RISC-V Instruction Set Manual, Volume II, 7612848Sar4jc@virginia.edu * v1.10, accessible at www.riscv.org. in Figure 3.7. The main register that 7712848Sar4jc@virginia.edu * uses these fields is the MSTATUS register, which is shadowed by two others 7812848Sar4jc@virginia.edu * accessible at lower privilege levels (SSTATUS and USTATUS) that can't see 7912848Sar4jc@virginia.edu * the fields for higher privileges. 8012848Sar4jc@virginia.edu */ 8112848Sar4jc@virginia.eduBitUnion64(STATUS) 8212848Sar4jc@virginia.edu Bitfield<63> sd; 8312848Sar4jc@virginia.edu Bitfield<35, 34> sxl; 8412848Sar4jc@virginia.edu Bitfield<33, 32> uxl; 8512848Sar4jc@virginia.edu Bitfield<22> tsr; 8612848Sar4jc@virginia.edu Bitfield<21> tw; 8712848Sar4jc@virginia.edu Bitfield<20> tvm; 8812848Sar4jc@virginia.edu Bitfield<19> mxr; 8912848Sar4jc@virginia.edu Bitfield<18> sum; 9012848Sar4jc@virginia.edu Bitfield<17> mprv; 9112848Sar4jc@virginia.edu Bitfield<16, 15> xs; 9212848Sar4jc@virginia.edu Bitfield<14, 13> fs; 9312848Sar4jc@virginia.edu Bitfield<12, 11> mpp; 9412848Sar4jc@virginia.edu Bitfield<8> spp; 9512848Sar4jc@virginia.edu Bitfield<7> mpie; 9612848Sar4jc@virginia.edu Bitfield<5> spie; 9712848Sar4jc@virginia.edu Bitfield<4> upie; 9812848Sar4jc@virginia.edu Bitfield<3> mie; 9912848Sar4jc@virginia.edu Bitfield<1> sie; 10012848Sar4jc@virginia.edu Bitfield<0> uie; 10112848Sar4jc@virginia.eduEndBitUnion(STATUS) 10212848Sar4jc@virginia.edu 10312848Sar4jc@virginia.edu/** 10412848Sar4jc@virginia.edu * These fields are specified in the RISC-V Instruction Set Manual, Volume II, 10512848Sar4jc@virginia.edu * v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org. Both the MIP 10612848Sar4jc@virginia.edu * and MIE registers have the same fields, so accesses to either should use 10712848Sar4jc@virginia.edu * this bit union. 10812848Sar4jc@virginia.edu */ 10912848Sar4jc@virginia.eduBitUnion64(INTERRUPT) 11012848Sar4jc@virginia.edu Bitfield<11> mei; 11112848Sar4jc@virginia.edu Bitfield<9> sei; 11212848Sar4jc@virginia.edu Bitfield<8> uei; 11312848Sar4jc@virginia.edu Bitfield<7> mti; 11412848Sar4jc@virginia.edu Bitfield<5> sti; 11512848Sar4jc@virginia.edu Bitfield<4> uti; 11612848Sar4jc@virginia.edu Bitfield<3> msi; 11712848Sar4jc@virginia.edu Bitfield<1> ssi; 11812848Sar4jc@virginia.edu Bitfield<0> usi; 11912848Sar4jc@virginia.eduEndBitUnion(INTERRUPT) 12011723Sar4jc@virginia.edu 12111723Sar4jc@virginia.educlass RiscvFault : public FaultBase 12211723Sar4jc@virginia.edu{ 12311723Sar4jc@virginia.edu protected: 12411723Sar4jc@virginia.edu const FaultName _name; 12512848Sar4jc@virginia.edu bool _interrupt; 12611723Sar4jc@virginia.edu const ExceptionCode _code; 12711723Sar4jc@virginia.edu 12812848Sar4jc@virginia.edu RiscvFault(FaultName n, bool i, ExceptionCode c) 12912848Sar4jc@virginia.edu : _name(n), _interrupt(i), _code(c) 13011723Sar4jc@virginia.edu {} 13111723Sar4jc@virginia.edu 13212849Sar4jc@virginia.edu FaultName name() const override { return _name; } 13312848Sar4jc@virginia.edu bool isInterrupt() const { return _interrupt; } 13412848Sar4jc@virginia.edu ExceptionCode exception() const { return _code; } 13512849Sar4jc@virginia.edu virtual MiscReg trap_value() const { return 0; } 13611723Sar4jc@virginia.edu 13712848Sar4jc@virginia.edu virtual void invokeSE(ThreadContext *tc, const StaticInstPtr &inst); 13812848Sar4jc@virginia.edu void invoke(ThreadContext *tc, const StaticInstPtr &inst) override; 13911723Sar4jc@virginia.edu}; 14011723Sar4jc@virginia.edu 14112808Srobert.scheffel1@tu-dresden.declass Reset : public FaultBase 14212808Srobert.scheffel1@tu-dresden.de{ 14312808Srobert.scheffel1@tu-dresden.de 14412808Srobert.scheffel1@tu-dresden.de public: 14512808Srobert.scheffel1@tu-dresden.de Reset() 14612808Srobert.scheffel1@tu-dresden.de : _name("reset") 14712808Srobert.scheffel1@tu-dresden.de {} 14812808Srobert.scheffel1@tu-dresden.de 14912808Srobert.scheffel1@tu-dresden.de FaultName 15012808Srobert.scheffel1@tu-dresden.de name() const override 15112808Srobert.scheffel1@tu-dresden.de { 15212808Srobert.scheffel1@tu-dresden.de return _name; 15312808Srobert.scheffel1@tu-dresden.de } 15412808Srobert.scheffel1@tu-dresden.de 15512808Srobert.scheffel1@tu-dresden.de void 15612808Srobert.scheffel1@tu-dresden.de invoke(ThreadContext *tc, const StaticInstPtr &inst = 15712808Srobert.scheffel1@tu-dresden.de StaticInst::nullStaticInstPtr) override; 15812808Srobert.scheffel1@tu-dresden.de 15912808Srobert.scheffel1@tu-dresden.de private: 16012808Srobert.scheffel1@tu-dresden.de const FaultName _name; 16112808Srobert.scheffel1@tu-dresden.de}; 16211723Sar4jc@virginia.edu 16312849Sar4jc@virginia.educlass InstFault : public RiscvFault 16412849Sar4jc@virginia.edu{ 16512849Sar4jc@virginia.edu protected: 16612849Sar4jc@virginia.edu const ExtMachInst _inst; 16712849Sar4jc@virginia.edu 16812849Sar4jc@virginia.edu public: 16912849Sar4jc@virginia.edu InstFault(FaultName n, const ExtMachInst inst) 17012849Sar4jc@virginia.edu : RiscvFault(n, false, INST_ILLEGAL), _inst(inst) 17112849Sar4jc@virginia.edu {} 17212849Sar4jc@virginia.edu 17312849Sar4jc@virginia.edu MiscReg trap_value() const override { return _inst; } 17412849Sar4jc@virginia.edu}; 17512849Sar4jc@virginia.edu 17612849Sar4jc@virginia.educlass UnknownInstFault : public InstFault 17711723Sar4jc@virginia.edu{ 17811723Sar4jc@virginia.edu public: 17912849Sar4jc@virginia.edu UnknownInstFault(const ExtMachInst inst) 18012849Sar4jc@virginia.edu : InstFault("Unknown instruction", inst) 18111723Sar4jc@virginia.edu {} 18211723Sar4jc@virginia.edu 18312848Sar4jc@virginia.edu void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 18411723Sar4jc@virginia.edu}; 18511723Sar4jc@virginia.edu 18612849Sar4jc@virginia.educlass IllegalInstFault : public InstFault 18712136Sar4jc@virginia.edu{ 18812136Sar4jc@virginia.edu private: 18912136Sar4jc@virginia.edu const std::string reason; 19012848Sar4jc@virginia.edu 19112136Sar4jc@virginia.edu public: 19212849Sar4jc@virginia.edu IllegalInstFault(std::string r, const ExtMachInst inst) 19312849Sar4jc@virginia.edu : InstFault("Illegal instruction", inst) 19412136Sar4jc@virginia.edu {} 19512136Sar4jc@virginia.edu 19612848Sar4jc@virginia.edu void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 19712136Sar4jc@virginia.edu}; 19812136Sar4jc@virginia.edu 19912849Sar4jc@virginia.educlass UnimplementedFault : public InstFault 20011723Sar4jc@virginia.edu{ 20111723Sar4jc@virginia.edu private: 20211723Sar4jc@virginia.edu const std::string instName; 20312848Sar4jc@virginia.edu 20411723Sar4jc@virginia.edu public: 20512849Sar4jc@virginia.edu UnimplementedFault(std::string name, const ExtMachInst inst) 20612849Sar4jc@virginia.edu : InstFault("Unimplemented instruction", inst), 20712848Sar4jc@virginia.edu instName(name) 20811723Sar4jc@virginia.edu {} 20911723Sar4jc@virginia.edu 21012848Sar4jc@virginia.edu void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 21111723Sar4jc@virginia.edu}; 21211723Sar4jc@virginia.edu 21312849Sar4jc@virginia.educlass IllegalFrmFault: public InstFault 21411725Sar4jc@virginia.edu{ 21511725Sar4jc@virginia.edu private: 21611725Sar4jc@virginia.edu const uint8_t frm; 21712848Sar4jc@virginia.edu 21811725Sar4jc@virginia.edu public: 21912849Sar4jc@virginia.edu IllegalFrmFault(uint8_t r, const ExtMachInst inst) 22012849Sar4jc@virginia.edu : InstFault("Illegal floating-point rounding mode", inst), 22112848Sar4jc@virginia.edu frm(r) 22211725Sar4jc@virginia.edu {} 22311725Sar4jc@virginia.edu 22412848Sar4jc@virginia.edu void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 22511725Sar4jc@virginia.edu}; 22611725Sar4jc@virginia.edu 22712849Sar4jc@virginia.educlass AddressFault : public RiscvFault 22812849Sar4jc@virginia.edu{ 22912849Sar4jc@virginia.edu private: 23012849Sar4jc@virginia.edu const Addr _addr; 23112849Sar4jc@virginia.edu 23212849Sar4jc@virginia.edu public: 23312849Sar4jc@virginia.edu AddressFault(const Addr addr, ExceptionCode code) 23412849Sar4jc@virginia.edu : RiscvFault("Address", false, code), _addr(addr) 23512849Sar4jc@virginia.edu {} 23612849Sar4jc@virginia.edu 23712849Sar4jc@virginia.edu MiscReg trap_value() const override { return _addr; } 23812849Sar4jc@virginia.edu}; 23912849Sar4jc@virginia.edu 24011723Sar4jc@virginia.educlass BreakpointFault : public RiscvFault 24111723Sar4jc@virginia.edu{ 24212849Sar4jc@virginia.edu private: 24312849Sar4jc@virginia.edu const PCState pcState; 24412849Sar4jc@virginia.edu 24511723Sar4jc@virginia.edu public: 24612849Sar4jc@virginia.edu BreakpointFault(const PCState &pc) 24712849Sar4jc@virginia.edu : RiscvFault("Breakpoint", false, BREAKPOINT), pcState(pc) 24812849Sar4jc@virginia.edu {} 24912849Sar4jc@virginia.edu 25012849Sar4jc@virginia.edu MiscReg trap_value() const override { return pcState.pc(); } 25112848Sar4jc@virginia.edu void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 25211723Sar4jc@virginia.edu}; 25311723Sar4jc@virginia.edu 25411723Sar4jc@virginia.educlass SyscallFault : public RiscvFault 25511723Sar4jc@virginia.edu{ 25611723Sar4jc@virginia.edu public: 25711723Sar4jc@virginia.edu // TODO: replace ECALL_USER with the appropriate privilege level of the 25811723Sar4jc@virginia.edu // caller 25912848Sar4jc@virginia.edu SyscallFault() : RiscvFault("System call", false, ECALL_USER) {} 26012848Sar4jc@virginia.edu void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 26111723Sar4jc@virginia.edu}; 26211723Sar4jc@virginia.edu 26311723Sar4jc@virginia.edu} // namespace RiscvISA 26411723Sar4jc@virginia.edu 26512849Sar4jc@virginia.edu#endif // __ARCH_RISCV_FAULTS_HH__