registers.hh revision 13556:9f57bb56153a 
1/*
2 * Copyright (c) 2009 The University of Edinburgh
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Timothy M. Jones
29 */
30
31#ifndef __ARCH_POWER_REGISTERS_HH__
32#define __ARCH_POWER_REGISTERS_HH__
33
34#include "arch/generic/vec_reg.hh"
35#include "arch/power/generated/max_inst_regs.hh"
36#include "arch/power/miscregs.hh"
37#include "base/types.hh"
38
39namespace PowerISA {
40
41using PowerISAInst::MaxInstSrcRegs;
42using PowerISAInst::MaxInstDestRegs;
43
44// Power writes a misc register outside of the isa parser, so it can't
45// be detected by it. Manually add it here.
46const int MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1;
47
48typedef RegVal IntReg;
49
50// Floating point register file entry type
51typedef RegVal FloatRegBits;
52typedef FloatRegVal FloatReg;
53typedef RegVal MiscReg;
54
55// dummy typedef since we don't have CC regs
56typedef uint8_t CCReg;
57
58// dummy typedefs since we don't have vector regs
59constexpr unsigned NumVecElemPerVecReg = 2;
60using VecElem = uint32_t;
61using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
62using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
63using VecRegContainer = VecReg::Container;
64// This has to be one to prevent warnings that are treated as errors
65constexpr unsigned NumVecRegs = 1;
66
67// Constants Related to the number of registers
68const int NumIntArchRegs = 32;
69
70// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR
71// and zero register, which doesn't actually exist but needs a number
72const int NumIntSpecialRegs = 9;
73const int NumFloatArchRegs = 32;
74const int NumFloatSpecialRegs = 0;
75const int NumInternalProcRegs = 0;
76
77const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
78const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
79const int NumCCRegs = 0;
80const int NumMiscRegs = NUM_MISCREGS;
81
82// Semantically meaningful register indices
83const int ReturnValueReg = 3;
84const int ArgumentReg0 = 3;
85const int ArgumentReg1 = 4;
86const int ArgumentReg2 = 5;
87const int ArgumentReg3 = 6;
88const int ArgumentReg4 = 7;
89const int FramePointerReg = 31;
90const int StackPointerReg = 1;
91
92// There isn't one in Power, but we need to define one somewhere
93const int ZeroReg = NumIntRegs - 1;
94
95const int SyscallNumReg = 0;
96const int SyscallPseudoReturnReg = 3;
97const int SyscallSuccessReg = 3;
98
99enum MiscIntRegNums {
100    INTREG_CR = NumIntArchRegs,
101    INTREG_XER,
102    INTREG_LR,
103    INTREG_CTR,
104    INTREG_FPSCR,
105    INTREG_RSV,
106    INTREG_RSV_LEN,
107    INTREG_RSV_ADDR
108};
109
110} // namespace PowerISA
111
112#endif // __ARCH_POWER_REGISTERS_HH__
113