registers.hh revision 12104:edd63f9c6184 
1/*
2 * Copyright (c) 2009 The University of Edinburgh
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Timothy M. Jones
29 */
30
31#ifndef __ARCH_POWER_REGISTERS_HH__
32#define __ARCH_POWER_REGISTERS_HH__
33
34#include "arch/power/generated/max_inst_regs.hh"
35#include "arch/power/miscregs.hh"
36
37namespace PowerISA {
38
39using PowerISAInst::MaxInstSrcRegs;
40using PowerISAInst::MaxInstDestRegs;
41
42// Power writes a misc register outside of the isa parser, so it can't
43// be detected by it. Manually add it here.
44const int MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1;
45
46typedef uint64_t IntReg;
47
48// Floating point register file entry type
49typedef uint64_t FloatRegBits;
50typedef double FloatReg;
51typedef uint64_t MiscReg;
52
53// dummy typedef since we don't have CC regs
54typedef uint8_t CCReg;
55
56// Constants Related to the number of registers
57const int NumIntArchRegs = 32;
58
59// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR
60// and zero register, which doesn't actually exist but needs a number
61const int NumIntSpecialRegs = 9;
62const int NumFloatArchRegs = 32;
63const int NumFloatSpecialRegs = 0;
64const int NumInternalProcRegs = 0;
65
66const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
67const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
68const int NumCCRegs = 0;
69const int NumMiscRegs = NUM_MISCREGS;
70
71// Semantically meaningful register indices
72const int ReturnValueReg = 3;
73const int ArgumentReg0 = 3;
74const int ArgumentReg1 = 4;
75const int ArgumentReg2 = 5;
76const int ArgumentReg3 = 6;
77const int ArgumentReg4 = 7;
78const int FramePointerReg = 31;
79const int StackPointerReg = 1;
80
81// There isn't one in Power, but we need to define one somewhere
82const int ZeroReg = NumIntRegs - 1;
83
84const int SyscallNumReg = 0;
85const int SyscallPseudoReturnReg = 3;
86const int SyscallSuccessReg = 3;
87
88typedef union {
89    IntReg   intreg;
90    FloatReg fpreg;
91    MiscReg  ctrlreg;
92} AnyReg;
93
94enum MiscIntRegNums {
95    INTREG_CR = NumIntArchRegs,
96    INTREG_XER,
97    INTREG_LR,
98    INTREG_CTR,
99    INTREG_FPSCR,
100    INTREG_RSV,
101    INTREG_RSV_LEN,
102    INTREG_RSV_ADDR
103};
104
105} // namespace PowerISA
106
107#endif // __ARCH_POWER_REGISTERS_HH__
108