registers.hh revision 10934:5af8f40d8f2c
1/* 2 * Copyright (c) 2009 The University of Edinburgh 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Timothy M. Jones 29 */ 30 31#ifndef __ARCH_POWER_REGISTERS_HH__ 32#define __ARCH_POWER_REGISTERS_HH__ 33 34#include "arch/power/generated/max_inst_regs.hh" 35#include "arch/power/miscregs.hh" 36 37namespace PowerISA { 38 39using PowerISAInst::MaxInstSrcRegs; 40using PowerISAInst::MaxInstDestRegs; 41 42// Power writes a misc register outside of the isa parser, so it can't 43// be detected by it. Manually add it here. 44const int MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1; 45 46typedef uint8_t RegIndex; 47 48typedef uint64_t IntReg; 49 50// Floating point register file entry type 51typedef uint64_t FloatRegBits; 52typedef double FloatReg; 53typedef uint64_t MiscReg; 54 55// dummy typedef since we don't have CC regs 56typedef uint8_t CCReg; 57 58// typedefs for Vector registers 59const int NumVectorRegElements = 0; 60typedef uint64_t VectorRegElement; 61const int VectorRegBytes = NumVectorRegElements * sizeof(VectorRegElement); 62typedef std::array<VectorRegElement, NumVectorRegElements> VectorReg; 63 64// Constants Related to the number of registers 65const int NumIntArchRegs = 32; 66 67// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR 68// and zero register, which doesn't actually exist but needs a number 69const int NumIntSpecialRegs = 9; 70const int NumFloatArchRegs = 32; 71const int NumFloatSpecialRegs = 0; 72const int NumInternalProcRegs = 0; 73 74const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; 75const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs; 76const int NumCCRegs = 0; 77const int NumVectorRegs = 0; 78const int NumMiscRegs = NUM_MISCREGS; 79 80// Semantically meaningful register indices 81const int ReturnValueReg = 3; 82const int ArgumentReg0 = 3; 83const int ArgumentReg1 = 4; 84const int ArgumentReg2 = 5; 85const int ArgumentReg3 = 6; 86const int ArgumentReg4 = 7; 87const int FramePointerReg = 31; 88const int StackPointerReg = 1; 89 90// There isn't one in Power, but we need to define one somewhere 91const int ZeroReg = NumIntRegs - 1; 92 93const int SyscallNumReg = 0; 94const int SyscallPseudoReturnReg = 3; 95const int SyscallSuccessReg = 3; 96 97// These help enumerate all the registers for dependence tracking. 98const int FP_Reg_Base = NumIntRegs; 99const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs; 100const int Vector_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0 101const int Misc_Reg_Base = Vector_Reg_Base + NumVectorRegs; // NumVectorRegs == 0 102const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs; 103 104typedef union { 105 IntReg intreg; 106 FloatReg fpreg; 107 MiscReg ctrlreg; 108} AnyReg; 109 110enum MiscIntRegNums { 111 INTREG_CR = NumIntArchRegs, 112 INTREG_XER, 113 INTREG_LR, 114 INTREG_CTR, 115 INTREG_FPSCR, 116 INTREG_RSV, 117 INTREG_RSV_LEN, 118 INTREG_RSV_ADDR 119}; 120 121} // namespace PowerISA 122 123#endif // __ARCH_POWER_REGISTERS_HH__ 124