registers.hh revision 12109
16691Stjones1@inf.ed.ac.uk/* 26691Stjones1@inf.ed.ac.uk * Copyright (c) 2009 The University of Edinburgh 36691Stjones1@inf.ed.ac.uk * All rights reserved. 46691Stjones1@inf.ed.ac.uk * 56691Stjones1@inf.ed.ac.uk * Redistribution and use in source and binary forms, with or without 66691Stjones1@inf.ed.ac.uk * modification, are permitted provided that the following conditions are 76691Stjones1@inf.ed.ac.uk * met: redistributions of source code must retain the above copyright 86691Stjones1@inf.ed.ac.uk * notice, this list of conditions and the following disclaimer; 96691Stjones1@inf.ed.ac.uk * redistributions in binary form must reproduce the above copyright 106691Stjones1@inf.ed.ac.uk * notice, this list of conditions and the following disclaimer in the 116691Stjones1@inf.ed.ac.uk * documentation and/or other materials provided with the distribution; 126691Stjones1@inf.ed.ac.uk * neither the name of the copyright holders nor the names of its 136691Stjones1@inf.ed.ac.uk * contributors may be used to endorse or promote products derived from 146691Stjones1@inf.ed.ac.uk * this software without specific prior written permission. 156691Stjones1@inf.ed.ac.uk * 166691Stjones1@inf.ed.ac.uk * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176691Stjones1@inf.ed.ac.uk * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186691Stjones1@inf.ed.ac.uk * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196691Stjones1@inf.ed.ac.uk * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206691Stjones1@inf.ed.ac.uk * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216691Stjones1@inf.ed.ac.uk * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226691Stjones1@inf.ed.ac.uk * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236691Stjones1@inf.ed.ac.uk * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246691Stjones1@inf.ed.ac.uk * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256691Stjones1@inf.ed.ac.uk * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266691Stjones1@inf.ed.ac.uk * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276691Stjones1@inf.ed.ac.uk * 286691Stjones1@inf.ed.ac.uk * Authors: Timothy M. Jones 296691Stjones1@inf.ed.ac.uk */ 306691Stjones1@inf.ed.ac.uk 316691Stjones1@inf.ed.ac.uk#ifndef __ARCH_POWER_REGISTERS_HH__ 326691Stjones1@inf.ed.ac.uk#define __ARCH_POWER_REGISTERS_HH__ 336691Stjones1@inf.ed.ac.uk 3412109SRekai.GonzalezAlberquilla@arm.com#include "arch/generic/vec_reg.hh" 358961Sgblack@eecs.umich.edu#include "arch/power/generated/max_inst_regs.hh" 366691Stjones1@inf.ed.ac.uk#include "arch/power/miscregs.hh" 376691Stjones1@inf.ed.ac.uk 386691Stjones1@inf.ed.ac.uknamespace PowerISA { 396691Stjones1@inf.ed.ac.uk 406691Stjones1@inf.ed.ac.ukusing PowerISAInst::MaxInstSrcRegs; 416691Stjones1@inf.ed.ac.ukusing PowerISAInst::MaxInstDestRegs; 429065Sandreas.hansson@arm.com 439065Sandreas.hansson@arm.com// Power writes a misc register outside of the isa parser, so it can't 449065Sandreas.hansson@arm.com// be detected by it. Manually add it here. 459065Sandreas.hansson@arm.comconst int MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1; 466691Stjones1@inf.ed.ac.uk 476691Stjones1@inf.ed.ac.uktypedef uint64_t IntReg; 486691Stjones1@inf.ed.ac.uk 496691Stjones1@inf.ed.ac.uk// Floating point register file entry type 506691Stjones1@inf.ed.ac.uktypedef uint64_t FloatRegBits; 516691Stjones1@inf.ed.ac.uktypedef double FloatReg; 526691Stjones1@inf.ed.ac.uktypedef uint64_t MiscReg; 536691Stjones1@inf.ed.ac.uk 549920Syasuko.eckert@amd.com// dummy typedef since we don't have CC regs 559920Syasuko.eckert@amd.comtypedef uint8_t CCReg; 569920Syasuko.eckert@amd.com 5712109SRekai.GonzalezAlberquilla@arm.com// dummy typedefs since we don't have vector regs 5812109SRekai.GonzalezAlberquilla@arm.comconstexpr unsigned NumVecElemPerVecReg = 2; 5912109SRekai.GonzalezAlberquilla@arm.comusing VecElem = uint32_t; 6012109SRekai.GonzalezAlberquilla@arm.comusing VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; 6112109SRekai.GonzalezAlberquilla@arm.comusing ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; 6212109SRekai.GonzalezAlberquilla@arm.comusing VecRegContainer = VecReg::Container; 6312109SRekai.GonzalezAlberquilla@arm.com// This has to be one to prevent warnings that are treated as errors 6412109SRekai.GonzalezAlberquilla@arm.comconstexpr unsigned NumVecRegs = 1; 6512109SRekai.GonzalezAlberquilla@arm.com 666691Stjones1@inf.ed.ac.uk// Constants Related to the number of registers 676691Stjones1@inf.ed.ac.ukconst int NumIntArchRegs = 32; 686691Stjones1@inf.ed.ac.uk 696691Stjones1@inf.ed.ac.uk// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR 706691Stjones1@inf.ed.ac.uk// and zero register, which doesn't actually exist but needs a number 716691Stjones1@inf.ed.ac.ukconst int NumIntSpecialRegs = 9; 726691Stjones1@inf.ed.ac.ukconst int NumFloatArchRegs = 32; 736691Stjones1@inf.ed.ac.ukconst int NumFloatSpecialRegs = 0; 746691Stjones1@inf.ed.ac.ukconst int NumInternalProcRegs = 0; 756691Stjones1@inf.ed.ac.uk 766691Stjones1@inf.ed.ac.ukconst int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; 776691Stjones1@inf.ed.ac.ukconst int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs; 789920Syasuko.eckert@amd.comconst int NumCCRegs = 0; 796691Stjones1@inf.ed.ac.ukconst int NumMiscRegs = NUM_MISCREGS; 806691Stjones1@inf.ed.ac.uk 816691Stjones1@inf.ed.ac.uk// Semantically meaningful register indices 826691Stjones1@inf.ed.ac.ukconst int ReturnValueReg = 3; 836691Stjones1@inf.ed.ac.ukconst int ArgumentReg0 = 3; 846691Stjones1@inf.ed.ac.ukconst int ArgumentReg1 = 4; 856691Stjones1@inf.ed.ac.ukconst int ArgumentReg2 = 5; 866691Stjones1@inf.ed.ac.ukconst int ArgumentReg3 = 6; 876691Stjones1@inf.ed.ac.ukconst int ArgumentReg4 = 7; 886691Stjones1@inf.ed.ac.ukconst int FramePointerReg = 31; 896691Stjones1@inf.ed.ac.ukconst int StackPointerReg = 1; 906691Stjones1@inf.ed.ac.uk 916691Stjones1@inf.ed.ac.uk// There isn't one in Power, but we need to define one somewhere 926691Stjones1@inf.ed.ac.ukconst int ZeroReg = NumIntRegs - 1; 936691Stjones1@inf.ed.ac.uk 946691Stjones1@inf.ed.ac.ukconst int SyscallNumReg = 0; 956691Stjones1@inf.ed.ac.ukconst int SyscallPseudoReturnReg = 3; 966691Stjones1@inf.ed.ac.ukconst int SyscallSuccessReg = 3; 976691Stjones1@inf.ed.ac.uk 986691Stjones1@inf.ed.ac.uktypedef union { 996691Stjones1@inf.ed.ac.uk IntReg intreg; 1006691Stjones1@inf.ed.ac.uk FloatReg fpreg; 1016691Stjones1@inf.ed.ac.uk MiscReg ctrlreg; 1026691Stjones1@inf.ed.ac.uk} AnyReg; 1036691Stjones1@inf.ed.ac.uk 1046691Stjones1@inf.ed.ac.ukenum MiscIntRegNums { 1056691Stjones1@inf.ed.ac.uk INTREG_CR = NumIntArchRegs, 1066691Stjones1@inf.ed.ac.uk INTREG_XER, 1076691Stjones1@inf.ed.ac.uk INTREG_LR, 1086691Stjones1@inf.ed.ac.uk INTREG_CTR, 1096691Stjones1@inf.ed.ac.uk INTREG_FPSCR, 1106691Stjones1@inf.ed.ac.uk INTREG_RSV, 1116691Stjones1@inf.ed.ac.uk INTREG_RSV_LEN, 1126691Stjones1@inf.ed.ac.uk INTREG_RSV_ADDR 1136691Stjones1@inf.ed.ac.uk}; 1146691Stjones1@inf.ed.ac.uk 1157811Ssteve.reinhardt@amd.com} // namespace PowerISA 1166691Stjones1@inf.ed.ac.uk 1176691Stjones1@inf.ed.ac.uk#endif // __ARCH_POWER_REGISTERS_HH__ 118