pagetable.hh revision 6691
15882Snate@binkert.org/* 25882Snate@binkert.org * Copyright (c) 2002-2005 The Regents of The University of Michigan 35882Snate@binkert.org * Copyright (c) 2007 MIPS Technologies, Inc. 45882Snate@binkert.org * Copyright (c) 2007-2008 The Florida State University 55882Snate@binkert.org * Copyright (c) 2009 The University of Edinburgh 65882Snate@binkert.org * All rights reserved. 75882Snate@binkert.org * 85882Snate@binkert.org * Redistribution and use in source and binary forms, with or without 95882Snate@binkert.org * modification, are permitted provided that the following conditions are 105882Snate@binkert.org * met: redistributions of source code must retain the above copyright 115882Snate@binkert.org * notice, this list of conditions and the following disclaimer; 125882Snate@binkert.org * redistributions in binary form must reproduce the above copyright 135882Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 145882Snate@binkert.org * documentation and/or other materials provided with the distribution; 155882Snate@binkert.org * neither the name of the copyright holders nor the names of its 165882Snate@binkert.org * contributors may be used to endorse or promote products derived from 175882Snate@binkert.org * this software without specific prior written permission. 185882Snate@binkert.org * 195882Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 205882Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 215882Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 225882Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 235882Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 245882Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 255882Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 265882Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 275882Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 285882Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 295882Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 305882Snate@binkert.org * 3111793Sbrandon.potter@amd.com * Authors: Nathan Binkert 3211793Sbrandon.potter@amd.com * Steve Reinhardt 335882Snate@binkert.org * Jaidev Patwardhan 345882Snate@binkert.org * Stephen Hines 355882Snate@binkert.org * Timothy M. Jones 368232Snate@binkert.org */ 378229Snate@binkert.org 388229Snate@binkert.org#ifndef __ARCH_POWER_PAGETABLE_H__ 395882Snate@binkert.org#define __ARCH_POWER_PAGETABLE_H__ 408232Snate@binkert.org 418232Snate@binkert.org#include "arch/power/isa_traits.hh" 428232Snate@binkert.org#include "arch/power/utility.hh" 435882Snate@binkert.org#include "arch/power/vtophys.hh" 448231Snate@binkert.org#include "config/full_system.hh" 458231Snate@binkert.org 468232Snate@binkert.orgnamespace PowerISA { 478232Snate@binkert.org 488232Snate@binkert.orgstruct VAddr 498232Snate@binkert.org{ 508232Snate@binkert.org static const int ImplBits = 43; 515882Snate@binkert.org static const Addr ImplMask = (ULL(1) << ImplBits) - 1; 528231Snate@binkert.org static const Addr UnImplMask = ~ImplMask; 535882Snate@binkert.org 545882Snate@binkert.org Addr addr; 555882Snate@binkert.org 565882Snate@binkert.org VAddr(Addr a) 578231Snate@binkert.org : addr(a) 585882Snate@binkert.org {} 595882Snate@binkert.org 608231Snate@binkert.org operator Addr() const 618232Snate@binkert.org { 628232Snate@binkert.org return addr; 638232Snate@binkert.org } 648232Snate@binkert.org 658232Snate@binkert.org const VAddr 668232Snate@binkert.org &operator=(Addr a) 678232Snate@binkert.org { 688232Snate@binkert.org addr = a; 698232Snate@binkert.org return *this; 708232Snate@binkert.org } 718232Snate@binkert.org 7211153SCurtis.Dunham@arm.com Addr 7311153SCurtis.Dunham@arm.com vpn() const 748232Snate@binkert.org { 758232Snate@binkert.org return (addr & ImplMask) >> PageShift; 768232Snate@binkert.org } 778232Snate@binkert.org 788232Snate@binkert.org Addr 798232Snate@binkert.org page() const 808232Snate@binkert.org { 818232Snate@binkert.org return addr & Page_Mask; 828232Snate@binkert.org } 838232Snate@binkert.org 848232Snate@binkert.org Addr 858232Snate@binkert.org offset() const 868232Snate@binkert.org { 878232Snate@binkert.org return addr & PageOffset; 888232Snate@binkert.org } 898232Snate@binkert.org 908232Snate@binkert.org Addr 918232Snate@binkert.org level3() const 928232Snate@binkert.org { 938232Snate@binkert.org return PowerISA::PteAddr(addr >> PageShift); 948232Snate@binkert.org } 958232Snate@binkert.org 968232Snate@binkert.org Addr 978232Snate@binkert.org level2() const 988232Snate@binkert.org { 998232Snate@binkert.org return PowerISA::PteAddr(addr >> (NPtePageShift + PageShift)); 1008232Snate@binkert.org } 10111153SCurtis.Dunham@arm.com 10211153SCurtis.Dunham@arm.com Addr 10311153SCurtis.Dunham@arm.com level1() const 10411153SCurtis.Dunham@arm.com { 10511153SCurtis.Dunham@arm.com return PowerISA::PteAddr(addr >> (2 * NPtePageShift + PageShift)); 10611153SCurtis.Dunham@arm.com } 10711153SCurtis.Dunham@arm.com}; 10811153SCurtis.Dunham@arm.com 10911153SCurtis.Dunham@arm.com// ITB/DTB page table entry 11011153SCurtis.Dunham@arm.comstruct PTE 11111153SCurtis.Dunham@arm.com{ 11211153SCurtis.Dunham@arm.com // What parts of the VAddr (from bits 28..11) should be used in 11311153SCurtis.Dunham@arm.com // translation (includes Mask and MaskX from PageMask) 11411153SCurtis.Dunham@arm.com Addr Mask; 11511153SCurtis.Dunham@arm.com 11611153SCurtis.Dunham@arm.com // Virtual Page Number (/2) (Includes VPN2 + VPN2X .. bits 31..11 1178232Snate@binkert.org // from EntryHi) 1188232Snate@binkert.org Addr VPN; 11911153SCurtis.Dunham@arm.com 12011153SCurtis.Dunham@arm.com // Address Space ID (8 bits) // Lower 8 bits of EntryHi 1218232Snate@binkert.org uint8_t asid; 1228232Snate@binkert.org 1238232Snate@binkert.org // Global Bit - Obtained by an *AND* of EntryLo0 and EntryLo1 G bit 1248232Snate@binkert.org bool G; 1258232Snate@binkert.org 12611153SCurtis.Dunham@arm.com /* Contents of Entry Lo0 */ 12711153SCurtis.Dunham@arm.com Addr PFN0; // Physical Frame Number - Even 1288232Snate@binkert.org bool D0; // Even entry Dirty Bit 1298232Snate@binkert.org bool V0; // Even entry Valid Bit 1308232Snate@binkert.org uint8_t C0; // Cache Coherency Bits - Even 1318232Snate@binkert.org 1328232Snate@binkert.org /* Contents of Entry Lo1 */ 1338232Snate@binkert.org Addr PFN1; // Physical Frame Number - Odd 1348232Snate@binkert.org bool D1; // Odd entry Dirty Bit 1358232Snate@binkert.org bool V1; // Odd entry Valid Bit 1368232Snate@binkert.org uint8_t C1; // Cache Coherency Bits (3 bits) 1378232Snate@binkert.org 1388232Snate@binkert.org // The next few variables are put in as optimizations to reduce TLB 1398232Snate@binkert.org // lookup overheads. For a given Mask, what is the address shift amount 1408232Snate@binkert.org // and what is the OffsetMask 1418232Snate@binkert.org int AddrShiftAmount; 1428232Snate@binkert.org int OffsetMask; 1438232Snate@binkert.org 1448232Snate@binkert.org bool 1458232Snate@binkert.org Valid() 1468232Snate@binkert.org { 1478232Snate@binkert.org return (V0 | V1); 1488232Snate@binkert.org }; 1498232Snate@binkert.org 1508232Snate@binkert.org void serialize(std::ostream &os); 1518232Snate@binkert.org 1528232Snate@binkert.org void unserialize(Checkpoint *cp, const std::string §ion); 1538699Ssteve.reinhardt@amd.com}; 1548232Snate@binkert.org 1558232Snate@binkert.org} // PowerISA namespace 1568232Snate@binkert.org 1578232Snate@binkert.org#endif // __ARCH_POWER_PAGETABLE_H__ 1588232Snate@binkert.org 1598232Snate@binkert.org