types.hh revision 6329:5d8b91875859
1/* 2 * Copyright (c) 2007 MIPS Technologies, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Korey Sewell 29 */ 30 31#ifndef __ARCH_MIPS_TYPES_HH__ 32#define __ARCH_MIPS_TYPES_HH__ 33 34#include "base/types.hh" 35 36namespace MipsISA 37{ 38 typedef uint32_t MachInst; 39 typedef uint64_t ExtMachInst; 40 41 typedef uint64_t LargestRead; 42 43 //used in FP convert & round function 44 enum ConvertType{ 45 SINGLE_TO_DOUBLE, 46 SINGLE_TO_WORD, 47 SINGLE_TO_LONG, 48 49 DOUBLE_TO_SINGLE, 50 DOUBLE_TO_WORD, 51 DOUBLE_TO_LONG, 52 53 LONG_TO_SINGLE, 54 LONG_TO_DOUBLE, 55 LONG_TO_WORD, 56 LONG_TO_PS, 57 58 WORD_TO_SINGLE, 59 WORD_TO_DOUBLE, 60 WORD_TO_LONG, 61 WORD_TO_PS, 62 63 PL_TO_SINGLE, 64 PU_TO_SINGLE 65 }; 66 67 //used in FP convert & round function 68 enum RoundMode{ 69 RND_ZERO, 70 RND_DOWN, 71 RND_UP, 72 RND_NEAREST 73 }; 74 75struct CoreSpecific { 76 /* Note: It looks like it will be better to allow simulator users 77 to specify the values of individual variables instead of requiring 78 users to define the values of entire registers 79 Especially since a lot of these variables can be created from other 80 user parameters (cache descriptions) 81 -jpp 82 */ 83 // MIPS CP0 State - First individual variables 84 // Page numbers refer to revision 2.50 (July 2005) of the MIPS32 ARM, Volume III (PRA) 85 unsigned CP0_IntCtl_IPTI; // Page 93, IP Timer Interrupt 86 unsigned CP0_IntCtl_IPPCI; // Page 94, IP Performance Counter Interrupt 87 unsigned CP0_SrsCtl_HSS; // Page 95, Highest Implemented Shadow Set 88 unsigned CP0_PRId_CompanyOptions; // Page 105, Manufacture options 89 unsigned CP0_PRId_CompanyID; // Page 105, Company ID - (0-255, 1=>MIPS) 90 unsigned CP0_PRId_ProcessorID; // Page 105 91 unsigned CP0_PRId_Revision; // Page 105 92 unsigned CP0_EBase_CPUNum; // Page 106, CPU Number in a multiprocessor system 93 unsigned CP0_Config_BE; // Page 108, Big/Little Endian mode 94 unsigned CP0_Config_AT; //Page 109 95 unsigned CP0_Config_AR; //Page 109 96 unsigned CP0_Config_MT; //Page 109 97 unsigned CP0_Config_VI; //Page 109 98 unsigned CP0_Config1_M; // Page 110 99 unsigned CP0_Config1_MMU; // Page 110 100 unsigned CP0_Config1_IS; // Page 110 101 unsigned CP0_Config1_IL; // Page 111 102 unsigned CP0_Config1_IA; // Page 111 103 unsigned CP0_Config1_DS; // Page 111 104 unsigned CP0_Config1_DL; // Page 112 105 unsigned CP0_Config1_DA; // Page 112 106 bool CP0_Config1_C2; // Page 112 107 bool CP0_Config1_MD;// Page 112 - Technically not used in MIPS32 108 bool CP0_Config1_PC;// Page 112 109 bool CP0_Config1_WR;// Page 113 110 bool CP0_Config1_CA;// Page 113 111 bool CP0_Config1_EP;// Page 113 112 bool CP0_Config1_FP;// Page 113 113 bool CP0_Config2_M; // Page 114 114 unsigned CP0_Config2_TU;// Page 114 115 unsigned CP0_Config2_TS;// Page 114 116 unsigned CP0_Config2_TL;// Page 115 117 unsigned CP0_Config2_TA;// Page 115 118 unsigned CP0_Config2_SU;// Page 115 119 unsigned CP0_Config2_SS;// Page 115 120 unsigned CP0_Config2_SL;// Page 116 121 unsigned CP0_Config2_SA;// Page 116 122 bool CP0_Config3_M; //// Page 117 123 bool CP0_Config3_DSPP;// Page 117 124 bool CP0_Config3_LPA;// Page 117 125 bool CP0_Config3_VEIC;// Page 118 126 bool CP0_Config3_VInt; // Page 118 127 bool CP0_Config3_SP;// Page 118 128 bool CP0_Config3_MT;// Page 119 129 bool CP0_Config3_SM;// Page 119 130 bool CP0_Config3_TL;// Page 119 131 132 bool CP0_WatchHi_M; // Page 124 133 bool CP0_PerfCtr_M; // Page 130 134 bool CP0_PerfCtr_W; // Page 130 135 136 137 // Then, whole registers 138 unsigned CP0_PRId; 139 unsigned CP0_Config; 140 unsigned CP0_Config1; 141 unsigned CP0_Config2; 142 unsigned CP0_Config3; 143}; 144 145} // namespace MipsISA 146 147#endif 148