1/*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Korey Sewell
29 */
30
31#ifndef __ARCH_MIPS_TYPES_HH__
32#define __ARCH_MIPS_TYPES_HH__
33
34#include "arch/generic/types.hh"
35#include "base/types.hh"
36
37namespace MipsISA
38{
39
40typedef uint32_t MachInst;
41typedef uint64_t ExtMachInst;
42
43typedef GenericISA::DelaySlotPCState<MachInst> PCState;
44
45//used in FP convert & round function
46enum ConvertType{
47    SINGLE_TO_DOUBLE,
48    SINGLE_TO_WORD,
49    SINGLE_TO_LONG,
50
51    DOUBLE_TO_SINGLE,
52    DOUBLE_TO_WORD,
53    DOUBLE_TO_LONG,
54
55    LONG_TO_SINGLE,
56    LONG_TO_DOUBLE,
57    LONG_TO_WORD,
58    LONG_TO_PS,
59
60    WORD_TO_SINGLE,
61    WORD_TO_DOUBLE,
62    WORD_TO_LONG,
63    WORD_TO_PS,
64
65    PL_TO_SINGLE,
66    PU_TO_SINGLE
67};
68
69//used in FP convert & round function
70enum RoundMode{
71    RND_ZERO,
72    RND_DOWN,
73    RND_UP,
74    RND_NEAREST
75};
76
77struct CoreSpecific {
78    CoreSpecific()
79        : CP0_IntCtl_IPTI(0), CP0_IntCtl_IPPCI(0), CP0_SrsCtl_HSS(0),
80          CP0_PRId_CompanyOptions(0), CP0_PRId_CompanyID(0),
81          CP0_PRId_ProcessorID(0), CP0_PRId_Revision(0),
82          CP0_EBase_CPUNum(0), CP0_Config_BE(0), CP0_Config_AT(0),
83          CP0_Config_AR(0), CP0_Config_MT(0), CP0_Config_VI(0),
84          CP0_Config1_M(0), CP0_Config1_MMU(0), CP0_Config1_IS(0),
85          CP0_Config1_IL(0), CP0_Config1_IA(0), CP0_Config1_DS(0),
86          CP0_Config1_DL(0), CP0_Config1_DA(0), CP0_Config1_C2(false),
87          CP0_Config1_MD(false), CP0_Config1_PC(false), CP0_Config1_WR(false),
88          CP0_Config1_CA(false), CP0_Config1_EP(false), CP0_Config1_FP(false),
89          CP0_Config2_M(false), CP0_Config2_TU(0), CP0_Config2_TS(0),
90          CP0_Config2_TL(0), CP0_Config2_TA(0), CP0_Config2_SU(0),
91          CP0_Config2_SS(0), CP0_Config2_SL(0), CP0_Config2_SA(0),
92          CP0_Config3_M(false), CP0_Config3_DSPP(false), CP0_Config3_LPA(false),
93          CP0_Config3_VEIC(false), CP0_Config3_VInt(false),
94          CP0_Config3_SP(false), CP0_Config3_MT(false), CP0_Config3_SM(false),
95          CP0_Config3_TL(false), CP0_WatchHi_M(false), CP0_PerfCtr_M(false),
96          CP0_PerfCtr_W(false), CP0_PRId(0), CP0_Config(0), CP0_Config1(0),
97          CP0_Config2(0), CP0_Config3(0)
98    { }
99
100      // MIPS CP0 State - First individual variables
101      // Page numbers refer to revision 2.50 (July 2005) of the MIPS32 ARM,
102      // Volume III (PRA)
103      unsigned CP0_IntCtl_IPTI; // Page 93, IP Timer Interrupt
104      unsigned CP0_IntCtl_IPPCI; // Page 94, IP Performance Counter Interrupt
105      unsigned CP0_SrsCtl_HSS; // Page 95, Highest Implemented Shadow Set
106      unsigned CP0_PRId_CompanyOptions; // Page 105, Manufacture options
107      unsigned CP0_PRId_CompanyID; // Page 105, Company ID - (0-255, 1=>MIPS)
108      unsigned CP0_PRId_ProcessorID; // Page 105
109      unsigned CP0_PRId_Revision; // Page 105
110      unsigned CP0_EBase_CPUNum; // Page 106, CPU Number in a multiprocessor
111                                 //system
112      unsigned CP0_Config_BE; // Page 108, Big/Little Endian mode
113      unsigned CP0_Config_AT; //Page 109
114      unsigned CP0_Config_AR; //Page 109
115      unsigned CP0_Config_MT; //Page 109
116      unsigned CP0_Config_VI; //Page 109
117      unsigned CP0_Config1_M; // Page 110
118      unsigned CP0_Config1_MMU; // Page 110
119      unsigned CP0_Config1_IS; // Page 110
120      unsigned CP0_Config1_IL; // Page 111
121      unsigned CP0_Config1_IA; // Page 111
122      unsigned CP0_Config1_DS; // Page 111
123      unsigned CP0_Config1_DL; // Page 112
124      unsigned CP0_Config1_DA; // Page 112
125      bool CP0_Config1_C2; // Page 112
126      bool CP0_Config1_MD;// Page 112 - Technically not used in MIPS32
127      bool CP0_Config1_PC;// Page 112
128      bool CP0_Config1_WR;// Page 113
129      bool CP0_Config1_CA;// Page 113
130      bool CP0_Config1_EP;// Page 113
131      bool CP0_Config1_FP;// Page 113
132      bool CP0_Config2_M; // Page 114
133      unsigned CP0_Config2_TU;// Page 114
134      unsigned CP0_Config2_TS;// Page 114
135      unsigned CP0_Config2_TL;// Page 115
136      unsigned CP0_Config2_TA;// Page 115
137      unsigned CP0_Config2_SU;// Page 115
138      unsigned CP0_Config2_SS;// Page 115
139      unsigned CP0_Config2_SL;// Page 116
140      unsigned CP0_Config2_SA;// Page 116
141      bool CP0_Config3_M; //// Page 117
142      bool CP0_Config3_DSPP;// Page 117
143      bool CP0_Config3_LPA;// Page 117
144      bool CP0_Config3_VEIC;// Page 118
145      bool CP0_Config3_VInt; // Page 118
146      bool CP0_Config3_SP;// Page 118
147      bool CP0_Config3_MT;// Page 119
148      bool CP0_Config3_SM;// Page 119
149      bool CP0_Config3_TL;// Page 119
150
151      bool CP0_WatchHi_M; // Page 124
152      bool CP0_PerfCtr_M; // Page 130
153      bool CP0_PerfCtr_W; // Page 130
154
155
156      // Then, whole registers
157      unsigned CP0_PRId;
158      unsigned CP0_Config;
159      unsigned CP0_Config1;
160      unsigned CP0_Config2;
161      unsigned CP0_Config3;
162};
163
164} // namespace MipsISA
165#endif
166