types.hh revision 6314:781969fbeca9 
1/*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Korey Sewell
29 */
30
31#ifndef __ARCH_MIPS_TYPES_HH__
32#define __ARCH_MIPS_TYPES_HH__
33
34#include "base/types.hh"
35
36namespace MipsISA
37{
38    typedef uint32_t MachInst;
39    typedef uint64_t ExtMachInst;
40    typedef uint16_t  RegIndex;
41
42    typedef uint32_t IntReg;
43    typedef uint64_t LargestRead;
44
45
46    // floating point register file entry type
47    typedef uint32_t FloatRegBits;
48    typedef float FloatReg;
49
50    // cop-0/cop-1 system control register
51    typedef uint64_t MiscReg;
52
53    typedef union {
54        IntReg   intreg;
55        FloatReg fpreg;
56        MiscReg  ctrlreg;
57    } AnyReg;
58
59    //used in FP convert & round function
60    enum ConvertType{
61        SINGLE_TO_DOUBLE,
62        SINGLE_TO_WORD,
63        SINGLE_TO_LONG,
64
65        DOUBLE_TO_SINGLE,
66        DOUBLE_TO_WORD,
67        DOUBLE_TO_LONG,
68
69        LONG_TO_SINGLE,
70        LONG_TO_DOUBLE,
71        LONG_TO_WORD,
72        LONG_TO_PS,
73
74        WORD_TO_SINGLE,
75        WORD_TO_DOUBLE,
76        WORD_TO_LONG,
77        WORD_TO_PS,
78
79        PL_TO_SINGLE,
80        PU_TO_SINGLE
81    };
82
83    //used in FP convert & round function
84    enum RoundMode{
85        RND_ZERO,
86        RND_DOWN,
87        RND_UP,
88        RND_NEAREST
89   };
90
91struct CoreSpecific {
92      /* Note: It looks like it will be better to allow simulator users
93         to specify the values of individual variables instead of requiring
94         users to define the values of entire registers
95         Especially since a lot of these variables can be created from other
96         user parameters  (cache descriptions)
97                                               -jpp
98      */
99      // MIPS CP0 State - First individual variables
100      // Page numbers refer to revision 2.50 (July 2005) of the MIPS32 ARM, Volume III (PRA)
101      unsigned CP0_IntCtl_IPTI; // Page 93, IP Timer Interrupt
102      unsigned CP0_IntCtl_IPPCI; // Page 94, IP Performance Counter Interrupt
103      unsigned CP0_SrsCtl_HSS; // Page 95, Highest Implemented Shadow Set
104      unsigned CP0_PRId_CompanyOptions; // Page 105, Manufacture options
105      unsigned CP0_PRId_CompanyID; // Page 105, Company ID - (0-255, 1=>MIPS)
106      unsigned CP0_PRId_ProcessorID; // Page 105
107      unsigned CP0_PRId_Revision; // Page 105
108      unsigned CP0_EBase_CPUNum; // Page 106, CPU Number in a multiprocessor system
109      unsigned CP0_Config_BE; // Page 108, Big/Little Endian mode
110      unsigned CP0_Config_AT; //Page 109
111      unsigned CP0_Config_AR; //Page 109
112      unsigned CP0_Config_MT; //Page 109
113      unsigned CP0_Config_VI; //Page 109
114      unsigned CP0_Config1_M; // Page 110
115      unsigned CP0_Config1_MMU; // Page 110
116      unsigned CP0_Config1_IS; // Page 110
117      unsigned CP0_Config1_IL; // Page 111
118      unsigned CP0_Config1_IA; // Page 111
119      unsigned CP0_Config1_DS; // Page 111
120      unsigned CP0_Config1_DL; // Page 112
121      unsigned CP0_Config1_DA; // Page 112
122      bool CP0_Config1_C2; // Page 112
123      bool CP0_Config1_MD;// Page 112 - Technically not used in MIPS32
124      bool CP0_Config1_PC;// Page 112
125      bool CP0_Config1_WR;// Page 113
126      bool CP0_Config1_CA;// Page 113
127      bool CP0_Config1_EP;// Page 113
128      bool CP0_Config1_FP;// Page 113
129      bool CP0_Config2_M; // Page 114
130      unsigned CP0_Config2_TU;// Page 114
131      unsigned CP0_Config2_TS;// Page 114
132      unsigned CP0_Config2_TL;// Page 115
133      unsigned CP0_Config2_TA;// Page 115
134      unsigned CP0_Config2_SU;// Page 115
135      unsigned CP0_Config2_SS;// Page 115
136      unsigned CP0_Config2_SL;// Page 116
137      unsigned CP0_Config2_SA;// Page 116
138      bool CP0_Config3_M; //// Page 117
139      bool CP0_Config3_DSPP;// Page 117
140      bool CP0_Config3_LPA;// Page 117
141      bool CP0_Config3_VEIC;// Page 118
142      bool CP0_Config3_VInt; // Page 118
143      bool CP0_Config3_SP;// Page 118
144      bool CP0_Config3_MT;// Page 119
145      bool CP0_Config3_SM;// Page 119
146      bool CP0_Config3_TL;// Page 119
147
148      bool CP0_WatchHi_M; // Page 124
149      bool CP0_PerfCtr_M; // Page 130
150      bool CP0_PerfCtr_W; // Page 130
151
152
153      // Then, whole registers
154      unsigned CP0_PRId;
155      unsigned CP0_Config;
156      unsigned CP0_Config1;
157      unsigned CP0_Config2;
158      unsigned CP0_Config3;
159};
160
161} // namespace MipsISA
162
163#endif
164