tlb.cc revision 11523:81332eb10367 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Nathan Binkert
30 *          Steve Reinhardt
31 *          Jaidev Patwardhan
32 *          Zhengxing Li
33 *          Deyuan Guo
34 */
35
36#include <string>
37#include <vector>
38
39#include "arch/mips/faults.hh"
40#include "arch/mips/pagetable.hh"
41#include "arch/mips/pra_constants.hh"
42#include "arch/mips/tlb.hh"
43#include "arch/mips/utility.hh"
44#include "base/inifile.hh"
45#include "base/str.hh"
46#include "base/trace.hh"
47#include "cpu/thread_context.hh"
48#include "debug/MipsPRA.hh"
49#include "debug/TLB.hh"
50#include "mem/page_table.hh"
51#include "params/MipsTLB.hh"
52#include "sim/process.hh"
53
54using namespace std;
55using namespace MipsISA;
56
57///////////////////////////////////////////////////////////////////////
58//
59//  MIPS TLB
60//
61
62TLB::TLB(const Params *p)
63    : BaseTLB(p), size(p->size), nlu(0)
64{
65    table = new PTE[size];
66    memset(table, 0, sizeof(PTE[size]));
67    smallPages = 0;
68}
69
70TLB::~TLB()
71{
72    if (table)
73        delete [] table;
74}
75
76// look up an entry in the TLB
77MipsISA::PTE *
78TLB::lookup(Addr vpn, uint8_t asn) const
79{
80    // assume not found...
81    PTE *retval = NULL;
82    PageTable::const_iterator i = lookupTable.find(vpn);
83    if (i != lookupTable.end()) {
84        while (i->first == vpn) {
85            int index = i->second;
86            PTE *pte = &table[index];
87
88            /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
89            Addr Mask = pte->Mask;
90            Addr InvMask = ~Mask;
91            Addr VPN  = pte->VPN;
92            if (((vpn & InvMask) == (VPN & InvMask)) &&
93                    (pte->G  || (asn == pte->asid))) {
94                // We have a VPN + ASID Match
95                retval = pte;
96                break;
97            }
98            ++i;
99        }
100    }
101
102    DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
103            retval ? "hit" : "miss", retval ? retval->PFN1 : 0);
104    return retval;
105}
106
107MipsISA::PTE*
108TLB::getEntry(unsigned Index) const
109{
110    // Make sure that Index is valid
111    assert(Index<size);
112    return &table[Index];
113}
114
115int
116TLB::probeEntry(Addr vpn, uint8_t asn) const
117{
118    // assume not found...
119    int Ind = -1;
120    PageTable::const_iterator i = lookupTable.find(vpn);
121    if (i != lookupTable.end()) {
122        while (i->first == vpn) {
123            int index = i->second;
124            PTE *pte = &table[index];
125
126            /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
127            Addr Mask = pte->Mask;
128            Addr InvMask = ~Mask;
129            Addr VPN = pte->VPN;
130            if (((vpn & InvMask) == (VPN & InvMask)) &&
131                    (pte->G  || (asn == pte->asid))) {
132                // We have a VPN + ASID Match
133                Ind = index;
134                break;
135            }
136            ++i;
137        }
138    }
139    DPRINTF(MipsPRA,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn,asn,Ind);
140    return Ind;
141}
142
143inline Fault
144TLB::checkCacheability(RequestPtr &req)
145{
146    Addr VAddrUncacheable = 0xA0000000;
147    // In MIPS, cacheability is controlled by certain bits of the virtual
148    // address or by the TLB entry
149    if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
150        // mark request as uncacheable
151        req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
152    }
153    return NoFault;
154}
155
156void
157TLB::insertAt(PTE &pte, unsigned Index, int _smallPages)
158{
159    smallPages = _smallPages;
160    if (Index > size) {
161        warn("Attempted to write at index (%d) beyond TLB size (%d)",
162                Index, size);
163    } else {
164        // Update TLB
165        DPRINTF(TLB, "TLB[%d]: %x %x %x %x\n",
166                Index, pte.Mask << 11,
167                ((pte.VPN << 11) | pte.asid),
168                ((pte.PFN0 << 6) | (pte.C0 << 3) |
169                 (pte.D0 << 2) | (pte.V0 <<1) | pte.G),
170                ((pte.PFN1 <<6) | (pte.C1 << 3) |
171                 (pte.D1 << 2) | (pte.V1 <<1) | pte.G));
172        if (table[Index].V0 || table[Index].V1) {
173            // Previous entry is valid
174            PageTable::iterator i = lookupTable.find(table[Index].VPN);
175            lookupTable.erase(i);
176        }
177        table[Index]=pte;
178        // Update fast lookup table
179        lookupTable.insert(make_pair(table[Index].VPN, Index));
180    }
181}
182
183// insert a new TLB entry
184void
185TLB::insert(Addr addr, PTE &pte)
186{
187    fatal("TLB Insert not yet implemented\n");
188}
189
190void
191TLB::flushAll()
192{
193    DPRINTF(TLB, "flushAll\n");
194    memset(table, 0, sizeof(PTE[size]));
195    lookupTable.clear();
196    nlu = 0;
197}
198
199void
200TLB::serialize(CheckpointOut &cp) const
201{
202    SERIALIZE_SCALAR(size);
203    SERIALIZE_SCALAR(nlu);
204
205    for (int i = 0; i < size; i++) {
206        ScopedCheckpointSection sec(cp, csprintf("PTE%d", i));
207        table[i].serialize(cp);
208    }
209}
210
211void
212TLB::unserialize(CheckpointIn &cp)
213{
214    UNSERIALIZE_SCALAR(size);
215    UNSERIALIZE_SCALAR(nlu);
216
217    for (int i = 0; i < size; i++) {
218        ScopedCheckpointSection sec(cp, csprintf("PTE%d", i));
219        table[i].unserialize(cp);
220        if (table[i].V0 || table[i].V1) {
221            lookupTable.insert(make_pair(table[i].VPN, i));
222        }
223    }
224}
225
226void
227TLB::regStats()
228{
229    BaseTLB::regStats();
230
231    read_hits
232        .name(name() + ".read_hits")
233        .desc("DTB read hits")
234        ;
235
236    read_misses
237        .name(name() + ".read_misses")
238        .desc("DTB read misses")
239        ;
240
241
242    read_accesses
243        .name(name() + ".read_accesses")
244        .desc("DTB read accesses")
245        ;
246
247    write_hits
248        .name(name() + ".write_hits")
249        .desc("DTB write hits")
250        ;
251
252    write_misses
253        .name(name() + ".write_misses")
254        .desc("DTB write misses")
255        ;
256
257
258    write_accesses
259        .name(name() + ".write_accesses")
260        .desc("DTB write accesses")
261        ;
262
263    hits
264        .name(name() + ".hits")
265        .desc("DTB hits")
266        ;
267
268    misses
269        .name(name() + ".misses")
270        .desc("DTB misses")
271        ;
272
273    accesses
274        .name(name() + ".accesses")
275        .desc("DTB accesses")
276        ;
277
278    hits = read_hits + write_hits;
279    misses = read_misses + write_misses;
280    accesses = read_accesses + write_accesses;
281}
282
283Fault
284TLB::translateInst(RequestPtr req, ThreadContext *tc)
285{
286    if (FullSystem)
287        panic("translateInst not implemented in MIPS.\n");
288
289    Process * p = tc->getProcessPtr();
290
291    Fault fault = p->pTable->translate(req);
292    if (fault != NoFault)
293        return fault;
294
295    return NoFault;
296}
297
298Fault
299TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
300{
301    if (FullSystem)
302        panic("translateData not implemented in MIPS.\n");
303
304    Process * p = tc->getProcessPtr();
305
306    Fault fault = p->pTable->translate(req);
307    if (fault != NoFault)
308        return fault;
309
310    return NoFault;
311}
312
313Fault
314TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
315{
316    if (mode == Execute)
317        return translateInst(req, tc);
318    else
319        return translateData(req, tc, mode == Write);
320}
321
322void
323TLB::translateTiming(RequestPtr req, ThreadContext *tc,
324        Translation *translation, Mode mode)
325{
326    assert(translation);
327    translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
328}
329
330Fault
331TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
332{
333    panic("Not implemented\n");
334    return NoFault;
335}
336
337Fault
338TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
339{
340    return NoFault;
341}
342
343
344MipsISA::PTE &
345TLB::index(bool advance)
346{
347    PTE *pte = &table[nlu];
348
349    if (advance)
350        nextnlu();
351
352    return *pte;
353}
354
355MipsISA::TLB *
356MipsTLBParams::create()
357{
358    return new TLB(this);
359}
360