tlb.cc revision 7708
14997Sgblack@eecs.umich.edu/* 25268Sksewell@umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 35254Sksewell@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc. 45254Sksewell@umich.edu * All rights reserved. 54997Sgblack@eecs.umich.edu * 65254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 75254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 85254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 95254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 105254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 115254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 125254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 135254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 145254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 155254Sksewell@umich.edu * this software without specific prior written permission. 164997Sgblack@eecs.umich.edu * 175254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245254Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255254Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265254Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275254Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 284997Sgblack@eecs.umich.edu * 295268Sksewell@umich.edu * Authors: Nathan Binkert 305268Sksewell@umich.edu * Steve Reinhardt 315268Sksewell@umich.edu * Jaidev Patwardhan 324997Sgblack@eecs.umich.edu */ 334997Sgblack@eecs.umich.edu 345222Sksewell@umich.edu#include <string> 355222Sksewell@umich.edu#include <vector> 364997Sgblack@eecs.umich.edu 375222Sksewell@umich.edu#include "arch/mips/pra_constants.hh" 385222Sksewell@umich.edu#include "arch/mips/pagetable.hh" 394997Sgblack@eecs.umich.edu#include "arch/mips/tlb.hh" 405222Sksewell@umich.edu#include "arch/mips/faults.hh" 415222Sksewell@umich.edu#include "arch/mips/utility.hh" 425222Sksewell@umich.edu#include "base/inifile.hh" 435222Sksewell@umich.edu#include "base/str.hh" 445222Sksewell@umich.edu#include "base/trace.hh" 455222Sksewell@umich.edu#include "cpu/thread_context.hh" 465224Sksewell@umich.edu#include "sim/process.hh" 475224Sksewell@umich.edu#include "mem/page_table.hh" 485222Sksewell@umich.edu#include "params/MipsTLB.hh" 494997Sgblack@eecs.umich.edu 505222Sksewell@umich.eduusing namespace std; 515222Sksewell@umich.eduusing namespace MipsISA; 525019Sgblack@eecs.umich.edu 535222Sksewell@umich.edu/////////////////////////////////////////////////////////////////////// 545222Sksewell@umich.edu// 555222Sksewell@umich.edu// MIPS TLB 565222Sksewell@umich.edu// 575019Sgblack@eecs.umich.edu 586329Sgblack@eecs.umich.edustatic inline mode_type 596329Sgblack@eecs.umich.edugetOperatingMode(MiscReg Stat) 606329Sgblack@eecs.umich.edu{ 616378Sgblack@eecs.umich.edu if ((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0) { 626329Sgblack@eecs.umich.edu return mode_kernel; 636378Sgblack@eecs.umich.edu } else if ((Stat & 0x18) == 0x8) { 646329Sgblack@eecs.umich.edu return mode_supervisor; 656378Sgblack@eecs.umich.edu } else if ((Stat & 0x18) == 0x10) { 666329Sgblack@eecs.umich.edu return mode_user; 676329Sgblack@eecs.umich.edu } else { 686329Sgblack@eecs.umich.edu return mode_number; 696329Sgblack@eecs.umich.edu } 706329Sgblack@eecs.umich.edu} 716329Sgblack@eecs.umich.edu 726329Sgblack@eecs.umich.edu 735222Sksewell@umich.eduTLB::TLB(const Params *p) 745358Sgblack@eecs.umich.edu : BaseTLB(p), size(p->size), nlu(0) 755222Sksewell@umich.edu{ 766378Sgblack@eecs.umich.edu table = new PTE[size]; 776378Sgblack@eecs.umich.edu memset(table, 0, sizeof(PTE[size])); 786378Sgblack@eecs.umich.edu smallPages = 0; 795222Sksewell@umich.edu} 805222Sksewell@umich.edu 815222Sksewell@umich.eduTLB::~TLB() 825222Sksewell@umich.edu{ 835222Sksewell@umich.edu if (table) 845222Sksewell@umich.edu delete [] table; 855222Sksewell@umich.edu} 865222Sksewell@umich.edu 875222Sksewell@umich.edu// look up an entry in the TLB 885222Sksewell@umich.eduMipsISA::PTE * 895222Sksewell@umich.eduTLB::lookup(Addr vpn, uint8_t asn) const 905222Sksewell@umich.edu{ 915222Sksewell@umich.edu // assume not found... 926378Sgblack@eecs.umich.edu PTE *retval = NULL; 935222Sksewell@umich.edu PageTable::const_iterator i = lookupTable.find(vpn); 945222Sksewell@umich.edu if (i != lookupTable.end()) { 955222Sksewell@umich.edu while (i->first == vpn) { 965222Sksewell@umich.edu int index = i->second; 976378Sgblack@eecs.umich.edu PTE *pte = &table[index]; 985222Sksewell@umich.edu 995222Sksewell@umich.edu /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */ 1005222Sksewell@umich.edu Addr Mask = pte->Mask; 1015222Sksewell@umich.edu Addr InvMask = ~Mask; 1025222Sksewell@umich.edu Addr VPN = pte->VPN; 1036378Sgblack@eecs.umich.edu if (((vpn & InvMask) == (VPN & InvMask)) && 1046378Sgblack@eecs.umich.edu (pte->G || (asn == pte->asid))) { 1056378Sgblack@eecs.umich.edu // We have a VPN + ASID Match 1065222Sksewell@umich.edu retval = pte; 1075222Sksewell@umich.edu break; 1086378Sgblack@eecs.umich.edu } 1095222Sksewell@umich.edu ++i; 1105222Sksewell@umich.edu } 1115019Sgblack@eecs.umich.edu } 1125019Sgblack@eecs.umich.edu 1135222Sksewell@umich.edu DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 1145222Sksewell@umich.edu retval ? "hit" : "miss", retval ? retval->PFN1 : 0); 1155222Sksewell@umich.edu return retval; 1165222Sksewell@umich.edu} 1175222Sksewell@umich.edu 1186378Sgblack@eecs.umich.eduMipsISA::PTE* 1196378Sgblack@eecs.umich.eduTLB::getEntry(unsigned Index) const 1205222Sksewell@umich.edu{ 1215222Sksewell@umich.edu // Make sure that Index is valid 1225222Sksewell@umich.edu assert(Index<size); 1235222Sksewell@umich.edu return &table[Index]; 1245222Sksewell@umich.edu} 1255222Sksewell@umich.edu 1266378Sgblack@eecs.umich.eduint 1276378Sgblack@eecs.umich.eduTLB::probeEntry(Addr vpn, uint8_t asn) const 1285222Sksewell@umich.edu{ 1295222Sksewell@umich.edu // assume not found... 1306378Sgblack@eecs.umich.edu PTE *retval = NULL; 1316378Sgblack@eecs.umich.edu int Ind = -1; 1325222Sksewell@umich.edu PageTable::const_iterator i = lookupTable.find(vpn); 1335222Sksewell@umich.edu if (i != lookupTable.end()) { 1345222Sksewell@umich.edu while (i->first == vpn) { 1355222Sksewell@umich.edu int index = i->second; 1366378Sgblack@eecs.umich.edu PTE *pte = &table[index]; 1375222Sksewell@umich.edu 1385222Sksewell@umich.edu /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */ 1395222Sksewell@umich.edu Addr Mask = pte->Mask; 1405222Sksewell@umich.edu Addr InvMask = ~Mask; 1416378Sgblack@eecs.umich.edu Addr VPN = pte->VPN; 1426378Sgblack@eecs.umich.edu if (((vpn & InvMask) == (VPN & InvMask)) && 1436378Sgblack@eecs.umich.edu (pte->G || (asn == pte->asid))) { 1446378Sgblack@eecs.umich.edu // We have a VPN + ASID Match 1455222Sksewell@umich.edu retval = pte; 1465222Sksewell@umich.edu Ind = index; 1475222Sksewell@umich.edu break; 1486378Sgblack@eecs.umich.edu } 1495222Sksewell@umich.edu ++i; 1505222Sksewell@umich.edu } 1515222Sksewell@umich.edu } 1525222Sksewell@umich.edu DPRINTF(MipsPRA,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn,asn,Ind); 1535222Sksewell@umich.edu return Ind; 1545222Sksewell@umich.edu} 1556378Sgblack@eecs.umich.edu 1566378Sgblack@eecs.umich.eduinline Fault 1575222Sksewell@umich.eduTLB::checkCacheability(RequestPtr &req) 1585222Sksewell@umich.edu{ 1596378Sgblack@eecs.umich.edu Addr VAddrUncacheable = 0xA0000000; 1606378Sgblack@eecs.umich.edu // In MIPS, cacheability is controlled by certain bits of the virtual 1616378Sgblack@eecs.umich.edu // address or by the TLB entry 1626378Sgblack@eecs.umich.edu if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) { 1636378Sgblack@eecs.umich.edu // mark request as uncacheable 1646378Sgblack@eecs.umich.edu req->setFlags(Request::UNCACHEABLE); 1656378Sgblack@eecs.umich.edu } 1666378Sgblack@eecs.umich.edu return NoFault; 1675222Sksewell@umich.edu} 1686378Sgblack@eecs.umich.edu 1696378Sgblack@eecs.umich.eduvoid 1706378Sgblack@eecs.umich.eduTLB::insertAt(PTE &pte, unsigned Index, int _smallPages) 1715222Sksewell@umich.edu{ 1726378Sgblack@eecs.umich.edu smallPages = _smallPages; 1736378Sgblack@eecs.umich.edu if (Index > size) { 1746378Sgblack@eecs.umich.edu warn("Attempted to write at index (%d) beyond TLB size (%d)", 1756378Sgblack@eecs.umich.edu Index, size); 1766378Sgblack@eecs.umich.edu } else { 1776378Sgblack@eecs.umich.edu // Update TLB 1786378Sgblack@eecs.umich.edu DPRINTF(TLB, "TLB[%d]: %x %x %x %x\n", 1796378Sgblack@eecs.umich.edu Index, pte.Mask << 11, 1806378Sgblack@eecs.umich.edu ((pte.VPN << 11) | pte.asid), 1816378Sgblack@eecs.umich.edu ((pte.PFN0 << 6) | (pte.C0 << 3) | 1826378Sgblack@eecs.umich.edu (pte.D0 << 2) | (pte.V0 <<1) | pte.G), 1836378Sgblack@eecs.umich.edu ((pte.PFN1 <<6) | (pte.C1 << 3) | 1846378Sgblack@eecs.umich.edu (pte.D1 << 2) | (pte.V1 <<1) | pte.G)); 1856378Sgblack@eecs.umich.edu if (table[Index].V0 == true || table[Index].V1 == true) { 1866378Sgblack@eecs.umich.edu // Previous entry is valid 1876378Sgblack@eecs.umich.edu PageTable::iterator i = lookupTable.find(table[Index].VPN); 1886378Sgblack@eecs.umich.edu lookupTable.erase(i); 1896378Sgblack@eecs.umich.edu } 1906378Sgblack@eecs.umich.edu table[Index]=pte; 1916378Sgblack@eecs.umich.edu // Update fast lookup table 1926378Sgblack@eecs.umich.edu lookupTable.insert(make_pair(table[Index].VPN, Index)); 1935222Sksewell@umich.edu } 1945222Sksewell@umich.edu} 1955222Sksewell@umich.edu 1965222Sksewell@umich.edu// insert a new TLB entry 1975222Sksewell@umich.eduvoid 1986378Sgblack@eecs.umich.eduTLB::insert(Addr addr, PTE &pte) 1995222Sksewell@umich.edu{ 2006378Sgblack@eecs.umich.edu fatal("TLB Insert not yet implemented\n"); 2015222Sksewell@umich.edu} 2025222Sksewell@umich.edu 2035222Sksewell@umich.eduvoid 2045222Sksewell@umich.eduTLB::flushAll() 2055222Sksewell@umich.edu{ 2065222Sksewell@umich.edu DPRINTF(TLB, "flushAll\n"); 2076378Sgblack@eecs.umich.edu memset(table, 0, sizeof(PTE[size])); 2085222Sksewell@umich.edu lookupTable.clear(); 2095222Sksewell@umich.edu nlu = 0; 2105222Sksewell@umich.edu} 2115222Sksewell@umich.edu 2125222Sksewell@umich.eduvoid 2135222Sksewell@umich.eduTLB::serialize(ostream &os) 2145222Sksewell@umich.edu{ 2155222Sksewell@umich.edu SERIALIZE_SCALAR(size); 2165222Sksewell@umich.edu SERIALIZE_SCALAR(nlu); 2175222Sksewell@umich.edu 2185222Sksewell@umich.edu for (int i = 0; i < size; i++) { 2195222Sksewell@umich.edu nameOut(os, csprintf("%s.PTE%d", name(), i)); 2205222Sksewell@umich.edu table[i].serialize(os); 2215222Sksewell@umich.edu } 2225222Sksewell@umich.edu} 2235222Sksewell@umich.edu 2245222Sksewell@umich.eduvoid 2255222Sksewell@umich.eduTLB::unserialize(Checkpoint *cp, const string §ion) 2265222Sksewell@umich.edu{ 2275222Sksewell@umich.edu UNSERIALIZE_SCALAR(size); 2285222Sksewell@umich.edu UNSERIALIZE_SCALAR(nlu); 2295222Sksewell@umich.edu 2305222Sksewell@umich.edu for (int i = 0; i < size; i++) { 2315222Sksewell@umich.edu table[i].unserialize(cp, csprintf("%s.PTE%d", section, i)); 2325222Sksewell@umich.edu if (table[i].V0 || table[i].V1) { 2335222Sksewell@umich.edu lookupTable.insert(make_pair(table[i].VPN, i)); 2345222Sksewell@umich.edu } 2355222Sksewell@umich.edu } 2365222Sksewell@umich.edu} 2375222Sksewell@umich.edu 2385222Sksewell@umich.eduvoid 2395222Sksewell@umich.eduTLB::regStats() 2405222Sksewell@umich.edu{ 2415222Sksewell@umich.edu read_hits 2425222Sksewell@umich.edu .name(name() + ".read_hits") 2435222Sksewell@umich.edu .desc("DTB read hits") 2445222Sksewell@umich.edu ; 2455222Sksewell@umich.edu 2465222Sksewell@umich.edu read_misses 2475222Sksewell@umich.edu .name(name() + ".read_misses") 2485222Sksewell@umich.edu .desc("DTB read misses") 2495222Sksewell@umich.edu ; 2505222Sksewell@umich.edu 2515222Sksewell@umich.edu 2525222Sksewell@umich.edu read_accesses 2535222Sksewell@umich.edu .name(name() + ".read_accesses") 2545222Sksewell@umich.edu .desc("DTB read accesses") 2555222Sksewell@umich.edu ; 2565222Sksewell@umich.edu 2575222Sksewell@umich.edu write_hits 2585222Sksewell@umich.edu .name(name() + ".write_hits") 2595222Sksewell@umich.edu .desc("DTB write hits") 2605222Sksewell@umich.edu ; 2615222Sksewell@umich.edu 2625222Sksewell@umich.edu write_misses 2635222Sksewell@umich.edu .name(name() + ".write_misses") 2645222Sksewell@umich.edu .desc("DTB write misses") 2655222Sksewell@umich.edu ; 2665222Sksewell@umich.edu 2675222Sksewell@umich.edu 2685222Sksewell@umich.edu write_accesses 2695222Sksewell@umich.edu .name(name() + ".write_accesses") 2705222Sksewell@umich.edu .desc("DTB write accesses") 2715222Sksewell@umich.edu ; 2725222Sksewell@umich.edu 2735222Sksewell@umich.edu hits 2745222Sksewell@umich.edu .name(name() + ".hits") 2755222Sksewell@umich.edu .desc("DTB hits") 2765222Sksewell@umich.edu ; 2775222Sksewell@umich.edu 2785222Sksewell@umich.edu misses 2795222Sksewell@umich.edu .name(name() + ".misses") 2805222Sksewell@umich.edu .desc("DTB misses") 2815222Sksewell@umich.edu ; 2825222Sksewell@umich.edu 2835222Sksewell@umich.edu accesses 2845222Sksewell@umich.edu .name(name() + ".accesses") 2855222Sksewell@umich.edu .desc("DTB accesses") 2865222Sksewell@umich.edu ; 2875222Sksewell@umich.edu 2885222Sksewell@umich.edu hits = read_hits + write_hits; 2895222Sksewell@umich.edu misses = read_misses + write_misses; 2905222Sksewell@umich.edu accesses = read_accesses + write_accesses; 2915222Sksewell@umich.edu} 2925222Sksewell@umich.edu 2935222Sksewell@umich.eduFault 2946022Sgblack@eecs.umich.eduTLB::translateInst(RequestPtr req, ThreadContext *tc) 2955222Sksewell@umich.edu{ 2965224Sksewell@umich.edu#if !FULL_SYSTEM 2975224Sksewell@umich.edu Process * p = tc->getProcessPtr(); 2985224Sksewell@umich.edu 2995224Sksewell@umich.edu Fault fault = p->pTable->translate(req); 3006378Sgblack@eecs.umich.edu if (fault != NoFault) 3015224Sksewell@umich.edu return fault; 3025224Sksewell@umich.edu 3035224Sksewell@umich.edu return NoFault; 3045224Sksewell@umich.edu#else 3057708Sgblack@eecs.umich.edu Addr vaddr = req->getVaddr(); 3067708Sgblack@eecs.umich.edu 3077708Sgblack@eecs.umich.edu bool misaligned = (req->getSize() - 1) & vaddr; 3087708Sgblack@eecs.umich.edu 3097708Sgblack@eecs.umich.edu if (IsKSeg0(vaddr)) { 3106378Sgblack@eecs.umich.edu // Address will not be translated through TLB, set response, and go! 3117708Sgblack@eecs.umich.edu req->setPaddr(KSeg02Phys(vaddr)); 3126383Sgblack@eecs.umich.edu if (getOperatingMode(tc->readMiscReg(MISCREG_STATUS)) != mode_kernel || 3137708Sgblack@eecs.umich.edu misaligned) { 3146378Sgblack@eecs.umich.edu AddressErrorFault *Flt = new AddressErrorFault(); 3156378Sgblack@eecs.umich.edu /* BadVAddr must be set */ 3167708Sgblack@eecs.umich.edu Flt->badVAddr = vaddr; 3176378Sgblack@eecs.umich.edu return Flt; 3186378Sgblack@eecs.umich.edu } 3197708Sgblack@eecs.umich.edu } else if(IsKSeg1(vaddr)) { 3206378Sgblack@eecs.umich.edu // Address will not be translated through TLB, set response, and go! 3217708Sgblack@eecs.umich.edu req->setPaddr(KSeg02Phys(vaddr)); 3226378Sgblack@eecs.umich.edu } else { 3236378Sgblack@eecs.umich.edu /* 3246378Sgblack@eecs.umich.edu * This is an optimization - smallPages is updated every time a TLB 3256378Sgblack@eecs.umich.edu * operation is performed. That way, we don't need to look at 3266378Sgblack@eecs.umich.edu * Config3 _ SP and PageGrain _ ESP every time we do a TLB lookup 3276378Sgblack@eecs.umich.edu */ 3286378Sgblack@eecs.umich.edu Addr VPN; 3296378Sgblack@eecs.umich.edu if (smallPages == 1) { 3307708Sgblack@eecs.umich.edu VPN = (vaddr >> 11); 3316378Sgblack@eecs.umich.edu } else { 3327708Sgblack@eecs.umich.edu VPN = ((vaddr >> 11) & 0xFFFFFFFC); 3336378Sgblack@eecs.umich.edu } 3346378Sgblack@eecs.umich.edu uint8_t Asid = req->getAsid(); 3357708Sgblack@eecs.umich.edu if (misaligned) { 3366378Sgblack@eecs.umich.edu // Unaligned address! 3375222Sksewell@umich.edu AddressErrorFault *Flt = new AddressErrorFault(); 3385222Sksewell@umich.edu /* BadVAddr must be set */ 3397708Sgblack@eecs.umich.edu Flt->badVAddr = vaddr; 3405222Sksewell@umich.edu return Flt; 3415222Sksewell@umich.edu } 3426378Sgblack@eecs.umich.edu PTE *pte = lookup(VPN,Asid); 3436378Sgblack@eecs.umich.edu if (pte != NULL) { 3446378Sgblack@eecs.umich.edu // Ok, found something 3455222Sksewell@umich.edu /* Check for valid bits */ 3465222Sksewell@umich.edu int EvenOdd; 3475222Sksewell@umich.edu bool Valid; 3487708Sgblack@eecs.umich.edu if ((((vaddr) >> pte->AddrShiftAmount) & 1) == 0) { 3496378Sgblack@eecs.umich.edu // Check even bits 3506378Sgblack@eecs.umich.edu Valid = pte->V0; 3516378Sgblack@eecs.umich.edu EvenOdd = 0; 3525222Sksewell@umich.edu } else { 3536378Sgblack@eecs.umich.edu // Check odd bits 3546378Sgblack@eecs.umich.edu Valid = pte->V1; 3556378Sgblack@eecs.umich.edu EvenOdd = 1; 3565222Sksewell@umich.edu } 3575222Sksewell@umich.edu 3586378Sgblack@eecs.umich.edu if (Valid == false) { 3596378Sgblack@eecs.umich.edu //Invalid entry 3605222Sksewell@umich.edu ItbInvalidFault *Flt = new ItbInvalidFault(); 3615222Sksewell@umich.edu /* EntryHi VPN, ASID fields must be set */ 3626379Sgblack@eecs.umich.edu Flt->entryHiAsid = Asid; 3636379Sgblack@eecs.umich.edu Flt->entryHiVPN2 = (VPN >> 2); 3646379Sgblack@eecs.umich.edu Flt->entryHiVPN2X = (VPN & 0x3); 3655222Sksewell@umich.edu 3665222Sksewell@umich.edu /* BadVAddr must be set */ 3677708Sgblack@eecs.umich.edu Flt->badVAddr = vaddr; 3685222Sksewell@umich.edu 3695222Sksewell@umich.edu /* Context must be set */ 3706379Sgblack@eecs.umich.edu Flt->contextBadVPN2 = (VPN >> 2); 3715222Sksewell@umich.edu return Flt; 3726378Sgblack@eecs.umich.edu } else { 3736378Sgblack@eecs.umich.edu // Ok, this is really a match, set paddr 3745222Sksewell@umich.edu Addr PAddr; 3756378Sgblack@eecs.umich.edu if (EvenOdd == 0) { 3765222Sksewell@umich.edu PAddr = pte->PFN0; 3776378Sgblack@eecs.umich.edu } else { 3785222Sksewell@umich.edu PAddr = pte->PFN1; 3795222Sksewell@umich.edu } 3806378Sgblack@eecs.umich.edu PAddr >>= (pte->AddrShiftAmount - 12); 3815222Sksewell@umich.edu PAddr <<= pte->AddrShiftAmount; 3827708Sgblack@eecs.umich.edu PAddr |= (vaddr & pte->OffsetMask); 3835222Sksewell@umich.edu req->setPaddr(PAddr); 3846378Sgblack@eecs.umich.edu } 3856378Sgblack@eecs.umich.edu } else { 3866378Sgblack@eecs.umich.edu // Didn't find any match, return a TLB Refill Exception 3876383Sgblack@eecs.umich.edu ItbRefillFault *Flt = new ItbRefillFault(); 3886378Sgblack@eecs.umich.edu /* EntryHi VPN, ASID fields must be set */ 3896379Sgblack@eecs.umich.edu Flt->entryHiAsid = Asid; 3906379Sgblack@eecs.umich.edu Flt->entryHiVPN2 = (VPN >> 2); 3916379Sgblack@eecs.umich.edu Flt->entryHiVPN2X = (VPN & 0x3); 3925222Sksewell@umich.edu 3936378Sgblack@eecs.umich.edu /* BadVAddr must be set */ 3947708Sgblack@eecs.umich.edu Flt->badVAddr = vaddr; 3955222Sksewell@umich.edu 3966378Sgblack@eecs.umich.edu /* Context must be set */ 3976379Sgblack@eecs.umich.edu Flt->contextBadVPN2 = (VPN >> 2); 3986378Sgblack@eecs.umich.edu return Flt; 3995222Sksewell@umich.edu } 4005222Sksewell@umich.edu } 4016378Sgblack@eecs.umich.edu return checkCacheability(req); 4025224Sksewell@umich.edu#endif 4035222Sksewell@umich.edu} 4045222Sksewell@umich.edu 4055222Sksewell@umich.eduFault 4066022Sgblack@eecs.umich.eduTLB::translateData(RequestPtr req, ThreadContext *tc, bool write) 4075222Sksewell@umich.edu{ 4085224Sksewell@umich.edu#if !FULL_SYSTEM 4096038Sksewell@umich.edu //@TODO: This should actually use TLB instead of going directly 4106038Sksewell@umich.edu // to the page table in syscall mode. 4116038Sksewell@umich.edu /** 4126038Sksewell@umich.edu * Check for alignment faults 4136038Sksewell@umich.edu */ 4146038Sksewell@umich.edu if (req->getVaddr() & (req->getSize() - 1)) { 4156038Sksewell@umich.edu DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(), 4166038Sksewell@umich.edu req->getSize()); 4176038Sksewell@umich.edu return new AlignmentFault(); 4186038Sksewell@umich.edu } 4196038Sksewell@umich.edu 4206038Sksewell@umich.edu 4215224Sksewell@umich.edu Process * p = tc->getProcessPtr(); 4225224Sksewell@umich.edu 4235224Sksewell@umich.edu Fault fault = p->pTable->translate(req); 4246378Sgblack@eecs.umich.edu if (fault != NoFault) 4255224Sksewell@umich.edu return fault; 4265224Sksewell@umich.edu 4275224Sksewell@umich.edu return NoFault; 4285224Sksewell@umich.edu#else 4297708Sgblack@eecs.umich.edu Addr vaddr = req->getVaddr(); 4307708Sgblack@eecs.umich.edu 4317708Sgblack@eecs.umich.edu bool misaligned = (req->getSize() - 1) & vaddr; 4327708Sgblack@eecs.umich.edu 4337708Sgblack@eecs.umich.edu if (IsKSeg0(vaddr)) { 4346378Sgblack@eecs.umich.edu // Address will not be translated through TLB, set response, and go! 4357708Sgblack@eecs.umich.edu req->setPaddr(KSeg02Phys(vaddr)); 4366383Sgblack@eecs.umich.edu if (getOperatingMode(tc->readMiscReg(MISCREG_STATUS)) != mode_kernel || 4377708Sgblack@eecs.umich.edu misaligned) { 4386378Sgblack@eecs.umich.edu StoreAddressErrorFault *Flt = new StoreAddressErrorFault(); 4396378Sgblack@eecs.umich.edu /* BadVAddr must be set */ 4407708Sgblack@eecs.umich.edu Flt->badVAddr = vaddr; 4416378Sgblack@eecs.umich.edu 4426378Sgblack@eecs.umich.edu return Flt; 4436378Sgblack@eecs.umich.edu } 4447708Sgblack@eecs.umich.edu } else if(IsKSeg1(vaddr)) { 4455222Sksewell@umich.edu // Address will not be translated through TLB, set response, and go! 4467708Sgblack@eecs.umich.edu req->setPaddr(KSeg02Phys(vaddr)); 4476378Sgblack@eecs.umich.edu } else { 4486378Sgblack@eecs.umich.edu /* 4496378Sgblack@eecs.umich.edu * This is an optimization - smallPages is updated every time a TLB 4506378Sgblack@eecs.umich.edu * operation is performed. That way, we don't need to look at 4516378Sgblack@eecs.umich.edu * Config3 _ SP and PageGrain _ ESP every time we do a TLB lookup 4526378Sgblack@eecs.umich.edu */ 4537708Sgblack@eecs.umich.edu Addr VPN = (vaddr >> 11) & 0xFFFFFFFC; 4546378Sgblack@eecs.umich.edu if (smallPages == 1) { 4557708Sgblack@eecs.umich.edu VPN = vaddr >> 11; 4566378Sgblack@eecs.umich.edu } 4576378Sgblack@eecs.umich.edu uint8_t Asid = req->getAsid(); 4586378Sgblack@eecs.umich.edu PTE *pte = lookup(VPN, Asid); 4597708Sgblack@eecs.umich.edu if (misaligned) { 4606378Sgblack@eecs.umich.edu // Unaligned address! 4616378Sgblack@eecs.umich.edu StoreAddressErrorFault *Flt = new StoreAddressErrorFault(); 4626378Sgblack@eecs.umich.edu /* BadVAddr must be set */ 4637708Sgblack@eecs.umich.edu Flt->badVAddr = vaddr; 4646378Sgblack@eecs.umich.edu return Flt; 4656378Sgblack@eecs.umich.edu } 4666378Sgblack@eecs.umich.edu if (pte != NULL) { 4676378Sgblack@eecs.umich.edu // Ok, found something 4686378Sgblack@eecs.umich.edu /* Check for valid bits */ 4696378Sgblack@eecs.umich.edu int EvenOdd; 4706378Sgblack@eecs.umich.edu bool Valid; 4716378Sgblack@eecs.umich.edu bool Dirty; 4727708Sgblack@eecs.umich.edu if ((((vaddr >> pte->AddrShiftAmount) & 1)) == 0) { 4736378Sgblack@eecs.umich.edu // Check even bits 4746378Sgblack@eecs.umich.edu Valid = pte->V0; 4756378Sgblack@eecs.umich.edu Dirty = pte->D0; 4766378Sgblack@eecs.umich.edu EvenOdd = 0; 4776378Sgblack@eecs.umich.edu } else { 4786378Sgblack@eecs.umich.edu // Check odd bits 4796378Sgblack@eecs.umich.edu Valid = pte->V1; 4806378Sgblack@eecs.umich.edu Dirty = pte->D1; 4816378Sgblack@eecs.umich.edu EvenOdd = 1; 4826378Sgblack@eecs.umich.edu } 4835222Sksewell@umich.edu 4846378Sgblack@eecs.umich.edu if (Valid == false) { 4856378Sgblack@eecs.umich.edu //Invalid entry 4866378Sgblack@eecs.umich.edu DtbInvalidFault *Flt = new DtbInvalidFault(); 4876378Sgblack@eecs.umich.edu /* EntryHi VPN, ASID fields must be set */ 4886379Sgblack@eecs.umich.edu Flt->entryHiAsid = Asid; 4896379Sgblack@eecs.umich.edu Flt->entryHiVPN2 = (VPN>>2); 4906379Sgblack@eecs.umich.edu Flt->entryHiVPN2X = (VPN & 0x3); 4915222Sksewell@umich.edu 4926378Sgblack@eecs.umich.edu /* BadVAddr must be set */ 4937708Sgblack@eecs.umich.edu Flt->badVAddr = vaddr; 4945222Sksewell@umich.edu 4956378Sgblack@eecs.umich.edu /* Context must be set */ 4966379Sgblack@eecs.umich.edu Flt->contextBadVPN2 = (VPN >> 2); 4975222Sksewell@umich.edu 4986378Sgblack@eecs.umich.edu return Flt; 4996378Sgblack@eecs.umich.edu } else { 5006378Sgblack@eecs.umich.edu // Ok, this is really a match, set paddr 5016378Sgblack@eecs.umich.edu if (!Dirty) { 5026378Sgblack@eecs.umich.edu TLBModifiedFault *Flt = new TLBModifiedFault(); 5036378Sgblack@eecs.umich.edu /* EntryHi VPN, ASID fields must be set */ 5046379Sgblack@eecs.umich.edu Flt->entryHiAsid = Asid; 5056379Sgblack@eecs.umich.edu Flt->entryHiVPN2 = (VPN >> 2); 5066379Sgblack@eecs.umich.edu Flt->entryHiVPN2X = (VPN & 0x3); 5075222Sksewell@umich.edu 5086378Sgblack@eecs.umich.edu /* BadVAddr must be set */ 5097708Sgblack@eecs.umich.edu Flt->badVAddr = vaddr; 5105222Sksewell@umich.edu 5116378Sgblack@eecs.umich.edu /* Context must be set */ 5126379Sgblack@eecs.umich.edu Flt->contextBadVPN2 = (VPN >> 2); 5136378Sgblack@eecs.umich.edu return Flt; 5146378Sgblack@eecs.umich.edu } 5156378Sgblack@eecs.umich.edu Addr PAddr; 5166378Sgblack@eecs.umich.edu if (EvenOdd == 0) { 5176378Sgblack@eecs.umich.edu PAddr = pte->PFN0; 5186378Sgblack@eecs.umich.edu } else { 5196378Sgblack@eecs.umich.edu PAddr = pte->PFN1; 5206378Sgblack@eecs.umich.edu } 5216378Sgblack@eecs.umich.edu PAddr >>= (pte->AddrShiftAmount - 12); 5226378Sgblack@eecs.umich.edu PAddr <<= pte->AddrShiftAmount; 5237708Sgblack@eecs.umich.edu PAddr |= (vaddr & pte->OffsetMask); 5246378Sgblack@eecs.umich.edu req->setPaddr(PAddr); 5256378Sgblack@eecs.umich.edu } 5266378Sgblack@eecs.umich.edu } else { 5276378Sgblack@eecs.umich.edu // Didn't find any match, return a TLB Refill Exception 5286378Sgblack@eecs.umich.edu DtbRefillFault *Flt = new DtbRefillFault(); 5296378Sgblack@eecs.umich.edu /* EntryHi VPN, ASID fields must be set */ 5306379Sgblack@eecs.umich.edu Flt->entryHiAsid = Asid; 5316379Sgblack@eecs.umich.edu Flt->entryHiVPN2 = (VPN >> 2); 5326379Sgblack@eecs.umich.edu Flt->entryHiVPN2X = (VPN & 0x3); 5335222Sksewell@umich.edu 5346378Sgblack@eecs.umich.edu /* BadVAddr must be set */ 5357708Sgblack@eecs.umich.edu Flt->badVAddr = vaddr; 5365222Sksewell@umich.edu 5376378Sgblack@eecs.umich.edu /* Context must be set */ 5386379Sgblack@eecs.umich.edu Flt->contextBadVPN2 = (VPN >> 2); 5396378Sgblack@eecs.umich.edu return Flt; 5405222Sksewell@umich.edu } 5415222Sksewell@umich.edu } 5425222Sksewell@umich.edu return checkCacheability(req); 5435224Sksewell@umich.edu#endif 5445222Sksewell@umich.edu} 5455222Sksewell@umich.edu 5466022Sgblack@eecs.umich.eduFault 5476023Snate@binkert.orgTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 5486022Sgblack@eecs.umich.edu{ 5496023Snate@binkert.org if (mode == Execute) 5506022Sgblack@eecs.umich.edu return translateInst(req, tc); 5516022Sgblack@eecs.umich.edu else 5526023Snate@binkert.org return translateData(req, tc, mode == Write); 5536022Sgblack@eecs.umich.edu} 5546022Sgblack@eecs.umich.edu 5555894Sgblack@eecs.umich.eduvoid 5566022Sgblack@eecs.umich.eduTLB::translateTiming(RequestPtr req, ThreadContext *tc, 5576023Snate@binkert.org Translation *translation, Mode mode) 5585894Sgblack@eecs.umich.edu{ 5595894Sgblack@eecs.umich.edu assert(translation); 5606023Snate@binkert.org translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 5615894Sgblack@eecs.umich.edu} 5625894Sgblack@eecs.umich.edu 5635222Sksewell@umich.edu 5645222Sksewell@umich.eduMipsISA::PTE & 5655222Sksewell@umich.eduTLB::index(bool advance) 5665222Sksewell@umich.edu{ 5676378Sgblack@eecs.umich.edu PTE *pte = &table[nlu]; 5685222Sksewell@umich.edu 5695222Sksewell@umich.edu if (advance) 5705222Sksewell@umich.edu nextnlu(); 5715222Sksewell@umich.edu 5725222Sksewell@umich.edu return *pte; 5735222Sksewell@umich.edu} 5744997Sgblack@eecs.umich.edu 5756022Sgblack@eecs.umich.eduMipsISA::TLB * 5766022Sgblack@eecs.umich.eduMipsTLBParams::create() 5774997Sgblack@eecs.umich.edu{ 5786378Sgblack@eecs.umich.edu return new TLB(this); 5794997Sgblack@eecs.umich.edu} 580