tlb.cc revision 6379
14997Sgblack@eecs.umich.edu/* 25268Sksewell@umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 35254Sksewell@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc. 45254Sksewell@umich.edu * All rights reserved. 54997Sgblack@eecs.umich.edu * 65254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 75254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 85254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 95254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 105254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 115254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 125254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 135254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 145254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 155254Sksewell@umich.edu * this software without specific prior written permission. 164997Sgblack@eecs.umich.edu * 175254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245254Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255254Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265254Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275254Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 284997Sgblack@eecs.umich.edu * 295268Sksewell@umich.edu * Authors: Nathan Binkert 305268Sksewell@umich.edu * Steve Reinhardt 315268Sksewell@umich.edu * Jaidev Patwardhan 324997Sgblack@eecs.umich.edu */ 334997Sgblack@eecs.umich.edu 345222Sksewell@umich.edu#include <string> 355222Sksewell@umich.edu#include <vector> 364997Sgblack@eecs.umich.edu 375222Sksewell@umich.edu#include "arch/mips/pra_constants.hh" 385222Sksewell@umich.edu#include "arch/mips/pagetable.hh" 394997Sgblack@eecs.umich.edu#include "arch/mips/tlb.hh" 405222Sksewell@umich.edu#include "arch/mips/faults.hh" 415222Sksewell@umich.edu#include "arch/mips/utility.hh" 425222Sksewell@umich.edu#include "base/inifile.hh" 435222Sksewell@umich.edu#include "base/str.hh" 445222Sksewell@umich.edu#include "base/trace.hh" 455222Sksewell@umich.edu#include "cpu/thread_context.hh" 465224Sksewell@umich.edu#include "sim/process.hh" 475224Sksewell@umich.edu#include "mem/page_table.hh" 485222Sksewell@umich.edu#include "params/MipsTLB.hh" 494997Sgblack@eecs.umich.edu 505019Sgblack@eecs.umich.edu 515222Sksewell@umich.eduusing namespace std; 525222Sksewell@umich.eduusing namespace MipsISA; 535019Sgblack@eecs.umich.edu 545222Sksewell@umich.edu/////////////////////////////////////////////////////////////////////// 555222Sksewell@umich.edu// 565222Sksewell@umich.edu// MIPS TLB 575222Sksewell@umich.edu// 585019Sgblack@eecs.umich.edu 596329Sgblack@eecs.umich.edustatic inline mode_type 606329Sgblack@eecs.umich.edugetOperatingMode(MiscReg Stat) 616329Sgblack@eecs.umich.edu{ 626378Sgblack@eecs.umich.edu if ((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0) { 636329Sgblack@eecs.umich.edu return mode_kernel; 646378Sgblack@eecs.umich.edu } else if ((Stat & 0x18) == 0x8) { 656329Sgblack@eecs.umich.edu return mode_supervisor; 666378Sgblack@eecs.umich.edu } else if ((Stat & 0x18) == 0x10) { 676329Sgblack@eecs.umich.edu return mode_user; 686329Sgblack@eecs.umich.edu } else { 696329Sgblack@eecs.umich.edu return mode_number; 706329Sgblack@eecs.umich.edu } 716329Sgblack@eecs.umich.edu} 726329Sgblack@eecs.umich.edu 736329Sgblack@eecs.umich.edu 745222Sksewell@umich.eduTLB::TLB(const Params *p) 755358Sgblack@eecs.umich.edu : BaseTLB(p), size(p->size), nlu(0) 765222Sksewell@umich.edu{ 776378Sgblack@eecs.umich.edu table = new PTE[size]; 786378Sgblack@eecs.umich.edu memset(table, 0, sizeof(PTE[size])); 796378Sgblack@eecs.umich.edu smallPages = 0; 805222Sksewell@umich.edu} 815222Sksewell@umich.edu 825222Sksewell@umich.eduTLB::~TLB() 835222Sksewell@umich.edu{ 845222Sksewell@umich.edu if (table) 855222Sksewell@umich.edu delete [] table; 865222Sksewell@umich.edu} 875222Sksewell@umich.edu 885222Sksewell@umich.edu// look up an entry in the TLB 895222Sksewell@umich.eduMipsISA::PTE * 905222Sksewell@umich.eduTLB::lookup(Addr vpn, uint8_t asn) const 915222Sksewell@umich.edu{ 925222Sksewell@umich.edu // assume not found... 936378Sgblack@eecs.umich.edu PTE *retval = NULL; 945222Sksewell@umich.edu PageTable::const_iterator i = lookupTable.find(vpn); 955222Sksewell@umich.edu if (i != lookupTable.end()) { 965222Sksewell@umich.edu while (i->first == vpn) { 975222Sksewell@umich.edu int index = i->second; 986378Sgblack@eecs.umich.edu PTE *pte = &table[index]; 995222Sksewell@umich.edu 1005222Sksewell@umich.edu /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */ 1015222Sksewell@umich.edu Addr Mask = pte->Mask; 1025222Sksewell@umich.edu Addr InvMask = ~Mask; 1035222Sksewell@umich.edu Addr VPN = pte->VPN; 1046378Sgblack@eecs.umich.edu if (((vpn & InvMask) == (VPN & InvMask)) && 1056378Sgblack@eecs.umich.edu (pte->G || (asn == pte->asid))) { 1066378Sgblack@eecs.umich.edu // We have a VPN + ASID Match 1075222Sksewell@umich.edu retval = pte; 1085222Sksewell@umich.edu break; 1096378Sgblack@eecs.umich.edu } 1105222Sksewell@umich.edu ++i; 1115222Sksewell@umich.edu } 1125019Sgblack@eecs.umich.edu } 1135019Sgblack@eecs.umich.edu 1145222Sksewell@umich.edu DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 1155222Sksewell@umich.edu retval ? "hit" : "miss", retval ? retval->PFN1 : 0); 1165222Sksewell@umich.edu return retval; 1175222Sksewell@umich.edu} 1185222Sksewell@umich.edu 1196378Sgblack@eecs.umich.eduMipsISA::PTE* 1206378Sgblack@eecs.umich.eduTLB::getEntry(unsigned Index) const 1215222Sksewell@umich.edu{ 1225222Sksewell@umich.edu // Make sure that Index is valid 1235222Sksewell@umich.edu assert(Index<size); 1245222Sksewell@umich.edu return &table[Index]; 1255222Sksewell@umich.edu} 1265222Sksewell@umich.edu 1276378Sgblack@eecs.umich.eduint 1286378Sgblack@eecs.umich.eduTLB::probeEntry(Addr vpn, uint8_t asn) const 1295222Sksewell@umich.edu{ 1305222Sksewell@umich.edu // assume not found... 1316378Sgblack@eecs.umich.edu PTE *retval = NULL; 1326378Sgblack@eecs.umich.edu int Ind = -1; 1335222Sksewell@umich.edu PageTable::const_iterator i = lookupTable.find(vpn); 1345222Sksewell@umich.edu if (i != lookupTable.end()) { 1355222Sksewell@umich.edu while (i->first == vpn) { 1365222Sksewell@umich.edu int index = i->second; 1376378Sgblack@eecs.umich.edu PTE *pte = &table[index]; 1385222Sksewell@umich.edu 1395222Sksewell@umich.edu /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */ 1405222Sksewell@umich.edu Addr Mask = pte->Mask; 1415222Sksewell@umich.edu Addr InvMask = ~Mask; 1426378Sgblack@eecs.umich.edu Addr VPN = pte->VPN; 1436378Sgblack@eecs.umich.edu if (((vpn & InvMask) == (VPN & InvMask)) && 1446378Sgblack@eecs.umich.edu (pte->G || (asn == pte->asid))) { 1456378Sgblack@eecs.umich.edu // We have a VPN + ASID Match 1465222Sksewell@umich.edu retval = pte; 1475222Sksewell@umich.edu Ind = index; 1485222Sksewell@umich.edu break; 1496378Sgblack@eecs.umich.edu } 1505222Sksewell@umich.edu ++i; 1515222Sksewell@umich.edu } 1525222Sksewell@umich.edu } 1535222Sksewell@umich.edu DPRINTF(MipsPRA,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn,asn,Ind); 1545222Sksewell@umich.edu return Ind; 1555222Sksewell@umich.edu} 1566378Sgblack@eecs.umich.edu 1576378Sgblack@eecs.umich.eduinline Fault 1585222Sksewell@umich.eduTLB::checkCacheability(RequestPtr &req) 1595222Sksewell@umich.edu{ 1606378Sgblack@eecs.umich.edu Addr VAddrUncacheable = 0xA0000000; 1616378Sgblack@eecs.umich.edu // In MIPS, cacheability is controlled by certain bits of the virtual 1626378Sgblack@eecs.umich.edu // address or by the TLB entry 1636378Sgblack@eecs.umich.edu if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) { 1646378Sgblack@eecs.umich.edu // mark request as uncacheable 1656378Sgblack@eecs.umich.edu req->setFlags(Request::UNCACHEABLE); 1666378Sgblack@eecs.umich.edu } 1676378Sgblack@eecs.umich.edu return NoFault; 1685222Sksewell@umich.edu} 1696378Sgblack@eecs.umich.edu 1706378Sgblack@eecs.umich.eduvoid 1716378Sgblack@eecs.umich.eduTLB::insertAt(PTE &pte, unsigned Index, int _smallPages) 1725222Sksewell@umich.edu{ 1736378Sgblack@eecs.umich.edu smallPages = _smallPages; 1746378Sgblack@eecs.umich.edu if (Index > size) { 1756378Sgblack@eecs.umich.edu warn("Attempted to write at index (%d) beyond TLB size (%d)", 1766378Sgblack@eecs.umich.edu Index, size); 1776378Sgblack@eecs.umich.edu } else { 1786378Sgblack@eecs.umich.edu // Update TLB 1796378Sgblack@eecs.umich.edu DPRINTF(TLB, "TLB[%d]: %x %x %x %x\n", 1806378Sgblack@eecs.umich.edu Index, pte.Mask << 11, 1816378Sgblack@eecs.umich.edu ((pte.VPN << 11) | pte.asid), 1826378Sgblack@eecs.umich.edu ((pte.PFN0 << 6) | (pte.C0 << 3) | 1836378Sgblack@eecs.umich.edu (pte.D0 << 2) | (pte.V0 <<1) | pte.G), 1846378Sgblack@eecs.umich.edu ((pte.PFN1 <<6) | (pte.C1 << 3) | 1856378Sgblack@eecs.umich.edu (pte.D1 << 2) | (pte.V1 <<1) | pte.G)); 1866378Sgblack@eecs.umich.edu if (table[Index].V0 == true || table[Index].V1 == true) { 1876378Sgblack@eecs.umich.edu // Previous entry is valid 1886378Sgblack@eecs.umich.edu PageTable::iterator i = lookupTable.find(table[Index].VPN); 1896378Sgblack@eecs.umich.edu lookupTable.erase(i); 1906378Sgblack@eecs.umich.edu } 1916378Sgblack@eecs.umich.edu table[Index]=pte; 1926378Sgblack@eecs.umich.edu // Update fast lookup table 1936378Sgblack@eecs.umich.edu lookupTable.insert(make_pair(table[Index].VPN, Index)); 1945222Sksewell@umich.edu } 1955222Sksewell@umich.edu} 1965222Sksewell@umich.edu 1975222Sksewell@umich.edu// insert a new TLB entry 1985222Sksewell@umich.eduvoid 1996378Sgblack@eecs.umich.eduTLB::insert(Addr addr, PTE &pte) 2005222Sksewell@umich.edu{ 2016378Sgblack@eecs.umich.edu fatal("TLB Insert not yet implemented\n"); 2025222Sksewell@umich.edu} 2035222Sksewell@umich.edu 2045222Sksewell@umich.eduvoid 2055222Sksewell@umich.eduTLB::flushAll() 2065222Sksewell@umich.edu{ 2075222Sksewell@umich.edu DPRINTF(TLB, "flushAll\n"); 2086378Sgblack@eecs.umich.edu memset(table, 0, sizeof(PTE[size])); 2095222Sksewell@umich.edu lookupTable.clear(); 2105222Sksewell@umich.edu nlu = 0; 2115222Sksewell@umich.edu} 2125222Sksewell@umich.edu 2135222Sksewell@umich.eduvoid 2145222Sksewell@umich.eduTLB::serialize(ostream &os) 2155222Sksewell@umich.edu{ 2165222Sksewell@umich.edu SERIALIZE_SCALAR(size); 2175222Sksewell@umich.edu SERIALIZE_SCALAR(nlu); 2185222Sksewell@umich.edu 2195222Sksewell@umich.edu for (int i = 0; i < size; i++) { 2205222Sksewell@umich.edu nameOut(os, csprintf("%s.PTE%d", name(), i)); 2215222Sksewell@umich.edu table[i].serialize(os); 2225222Sksewell@umich.edu } 2235222Sksewell@umich.edu} 2245222Sksewell@umich.edu 2255222Sksewell@umich.eduvoid 2265222Sksewell@umich.eduTLB::unserialize(Checkpoint *cp, const string §ion) 2275222Sksewell@umich.edu{ 2285222Sksewell@umich.edu UNSERIALIZE_SCALAR(size); 2295222Sksewell@umich.edu UNSERIALIZE_SCALAR(nlu); 2305222Sksewell@umich.edu 2315222Sksewell@umich.edu for (int i = 0; i < size; i++) { 2325222Sksewell@umich.edu table[i].unserialize(cp, csprintf("%s.PTE%d", section, i)); 2335222Sksewell@umich.edu if (table[i].V0 || table[i].V1) { 2345222Sksewell@umich.edu lookupTable.insert(make_pair(table[i].VPN, i)); 2355222Sksewell@umich.edu } 2365222Sksewell@umich.edu } 2375222Sksewell@umich.edu} 2385222Sksewell@umich.edu 2395222Sksewell@umich.eduvoid 2405222Sksewell@umich.eduTLB::regStats() 2415222Sksewell@umich.edu{ 2425222Sksewell@umich.edu read_hits 2435222Sksewell@umich.edu .name(name() + ".read_hits") 2445222Sksewell@umich.edu .desc("DTB read hits") 2455222Sksewell@umich.edu ; 2465222Sksewell@umich.edu 2475222Sksewell@umich.edu read_misses 2485222Sksewell@umich.edu .name(name() + ".read_misses") 2495222Sksewell@umich.edu .desc("DTB read misses") 2505222Sksewell@umich.edu ; 2515222Sksewell@umich.edu 2525222Sksewell@umich.edu 2535222Sksewell@umich.edu read_accesses 2545222Sksewell@umich.edu .name(name() + ".read_accesses") 2555222Sksewell@umich.edu .desc("DTB read accesses") 2565222Sksewell@umich.edu ; 2575222Sksewell@umich.edu 2585222Sksewell@umich.edu write_hits 2595222Sksewell@umich.edu .name(name() + ".write_hits") 2605222Sksewell@umich.edu .desc("DTB write hits") 2615222Sksewell@umich.edu ; 2625222Sksewell@umich.edu 2635222Sksewell@umich.edu write_misses 2645222Sksewell@umich.edu .name(name() + ".write_misses") 2655222Sksewell@umich.edu .desc("DTB write misses") 2665222Sksewell@umich.edu ; 2675222Sksewell@umich.edu 2685222Sksewell@umich.edu 2695222Sksewell@umich.edu write_accesses 2705222Sksewell@umich.edu .name(name() + ".write_accesses") 2715222Sksewell@umich.edu .desc("DTB write accesses") 2725222Sksewell@umich.edu ; 2735222Sksewell@umich.edu 2745222Sksewell@umich.edu hits 2755222Sksewell@umich.edu .name(name() + ".hits") 2765222Sksewell@umich.edu .desc("DTB hits") 2775222Sksewell@umich.edu ; 2785222Sksewell@umich.edu 2795222Sksewell@umich.edu misses 2805222Sksewell@umich.edu .name(name() + ".misses") 2815222Sksewell@umich.edu .desc("DTB misses") 2825222Sksewell@umich.edu ; 2835222Sksewell@umich.edu 2845222Sksewell@umich.edu invalids 2855222Sksewell@umich.edu .name(name() + ".invalids") 2865222Sksewell@umich.edu .desc("DTB access violations") 2875222Sksewell@umich.edu ; 2885222Sksewell@umich.edu 2895222Sksewell@umich.edu accesses 2905222Sksewell@umich.edu .name(name() + ".accesses") 2915222Sksewell@umich.edu .desc("DTB accesses") 2925222Sksewell@umich.edu ; 2935222Sksewell@umich.edu 2945222Sksewell@umich.edu hits = read_hits + write_hits; 2955222Sksewell@umich.edu misses = read_misses + write_misses; 2965222Sksewell@umich.edu accesses = read_accesses + write_accesses; 2975222Sksewell@umich.edu} 2985222Sksewell@umich.edu 2995222Sksewell@umich.eduFault 3006022Sgblack@eecs.umich.eduTLB::translateInst(RequestPtr req, ThreadContext *tc) 3015222Sksewell@umich.edu{ 3025224Sksewell@umich.edu#if !FULL_SYSTEM 3035224Sksewell@umich.edu Process * p = tc->getProcessPtr(); 3045224Sksewell@umich.edu 3055224Sksewell@umich.edu Fault fault = p->pTable->translate(req); 3066378Sgblack@eecs.umich.edu if (fault != NoFault) 3075224Sksewell@umich.edu return fault; 3085224Sksewell@umich.edu 3095224Sksewell@umich.edu return NoFault; 3105224Sksewell@umich.edu#else 3116378Sgblack@eecs.umich.edu if (IsKSeg0(req->getVaddr())) { 3126378Sgblack@eecs.umich.edu // Address will not be translated through TLB, set response, and go! 3136378Sgblack@eecs.umich.edu req->setPaddr(KSeg02Phys(req->getVaddr())); 3146378Sgblack@eecs.umich.edu if (getOperatingMode(tc->readMiscReg(Status)) != mode_kernel || 3156378Sgblack@eecs.umich.edu req->isMisaligned()) { 3166378Sgblack@eecs.umich.edu AddressErrorFault *Flt = new AddressErrorFault(); 3176378Sgblack@eecs.umich.edu /* BadVAddr must be set */ 3186379Sgblack@eecs.umich.edu Flt->badVAddr = req->getVaddr(); 3196378Sgblack@eecs.umich.edu return Flt; 3206378Sgblack@eecs.umich.edu } 3216378Sgblack@eecs.umich.edu } else if(IsKSeg1(req->getVaddr())) { 3226378Sgblack@eecs.umich.edu // Address will not be translated through TLB, set response, and go! 3236378Sgblack@eecs.umich.edu req->setPaddr(KSeg02Phys(req->getVaddr())); 3246378Sgblack@eecs.umich.edu } else { 3256378Sgblack@eecs.umich.edu /* 3266378Sgblack@eecs.umich.edu * This is an optimization - smallPages is updated every time a TLB 3276378Sgblack@eecs.umich.edu * operation is performed. That way, we don't need to look at 3286378Sgblack@eecs.umich.edu * Config3 _ SP and PageGrain _ ESP every time we do a TLB lookup 3296378Sgblack@eecs.umich.edu */ 3306378Sgblack@eecs.umich.edu Addr VPN; 3316378Sgblack@eecs.umich.edu if (smallPages == 1) { 3326378Sgblack@eecs.umich.edu VPN = ((req->getVaddr() >> 11)); 3336378Sgblack@eecs.umich.edu } else { 3346378Sgblack@eecs.umich.edu VPN = ((req->getVaddr() >> 11) & 0xFFFFFFFC); 3356378Sgblack@eecs.umich.edu } 3366378Sgblack@eecs.umich.edu uint8_t Asid = req->getAsid(); 3376378Sgblack@eecs.umich.edu if (req->isMisaligned()) { 3386378Sgblack@eecs.umich.edu // Unaligned address! 3395222Sksewell@umich.edu AddressErrorFault *Flt = new AddressErrorFault(); 3405222Sksewell@umich.edu /* BadVAddr must be set */ 3416379Sgblack@eecs.umich.edu Flt->badVAddr = req->getVaddr(); 3425222Sksewell@umich.edu return Flt; 3435222Sksewell@umich.edu } 3446378Sgblack@eecs.umich.edu PTE *pte = lookup(VPN,Asid); 3456378Sgblack@eecs.umich.edu if (pte != NULL) { 3466378Sgblack@eecs.umich.edu // Ok, found something 3475222Sksewell@umich.edu /* Check for valid bits */ 3485222Sksewell@umich.edu int EvenOdd; 3495222Sksewell@umich.edu bool Valid; 3506378Sgblack@eecs.umich.edu if ((((req->getVaddr()) >> pte->AddrShiftAmount) & 1) == 0) { 3516378Sgblack@eecs.umich.edu // Check even bits 3526378Sgblack@eecs.umich.edu Valid = pte->V0; 3536378Sgblack@eecs.umich.edu EvenOdd = 0; 3545222Sksewell@umich.edu } else { 3556378Sgblack@eecs.umich.edu // Check odd bits 3566378Sgblack@eecs.umich.edu Valid = pte->V1; 3576378Sgblack@eecs.umich.edu EvenOdd = 1; 3585222Sksewell@umich.edu } 3595222Sksewell@umich.edu 3606378Sgblack@eecs.umich.edu if (Valid == false) { 3616378Sgblack@eecs.umich.edu //Invalid entry 3625222Sksewell@umich.edu ItbInvalidFault *Flt = new ItbInvalidFault(); 3635222Sksewell@umich.edu /* EntryHi VPN, ASID fields must be set */ 3646379Sgblack@eecs.umich.edu Flt->entryHiAsid = Asid; 3656379Sgblack@eecs.umich.edu Flt->entryHiVPN2 = (VPN >> 2); 3666379Sgblack@eecs.umich.edu Flt->entryHiVPN2X = (VPN & 0x3); 3675222Sksewell@umich.edu 3685222Sksewell@umich.edu /* BadVAddr must be set */ 3696379Sgblack@eecs.umich.edu Flt->badVAddr = req->getVaddr(); 3705222Sksewell@umich.edu 3715222Sksewell@umich.edu /* Context must be set */ 3726379Sgblack@eecs.umich.edu Flt->contextBadVPN2 = (VPN >> 2); 3735222Sksewell@umich.edu return Flt; 3746378Sgblack@eecs.umich.edu } else { 3756378Sgblack@eecs.umich.edu // Ok, this is really a match, set paddr 3765222Sksewell@umich.edu Addr PAddr; 3776378Sgblack@eecs.umich.edu if (EvenOdd == 0) { 3785222Sksewell@umich.edu PAddr = pte->PFN0; 3796378Sgblack@eecs.umich.edu } else { 3805222Sksewell@umich.edu PAddr = pte->PFN1; 3815222Sksewell@umich.edu } 3826378Sgblack@eecs.umich.edu PAddr >>= (pte->AddrShiftAmount - 12); 3835222Sksewell@umich.edu PAddr <<= pte->AddrShiftAmount; 3845222Sksewell@umich.edu PAddr |= ((req->getVaddr()) & pte->OffsetMask); 3855222Sksewell@umich.edu req->setPaddr(PAddr); 3866378Sgblack@eecs.umich.edu } 3876378Sgblack@eecs.umich.edu } else { 3886378Sgblack@eecs.umich.edu // Didn't find any match, return a TLB Refill Exception 3896378Sgblack@eecs.umich.edu ItbRefillFault *Flt=new ItbRefillFault(); 3906378Sgblack@eecs.umich.edu /* EntryHi VPN, ASID fields must be set */ 3916379Sgblack@eecs.umich.edu Flt->entryHiAsid = Asid; 3926379Sgblack@eecs.umich.edu Flt->entryHiVPN2 = (VPN >> 2); 3936379Sgblack@eecs.umich.edu Flt->entryHiVPN2X = (VPN & 0x3); 3945222Sksewell@umich.edu 3956378Sgblack@eecs.umich.edu /* BadVAddr must be set */ 3966379Sgblack@eecs.umich.edu Flt->badVAddr = req->getVaddr(); 3975222Sksewell@umich.edu 3986378Sgblack@eecs.umich.edu /* Context must be set */ 3996379Sgblack@eecs.umich.edu Flt->contextBadVPN2 = (VPN >> 2); 4006378Sgblack@eecs.umich.edu return Flt; 4015222Sksewell@umich.edu } 4025222Sksewell@umich.edu } 4036378Sgblack@eecs.umich.edu return checkCacheability(req); 4045224Sksewell@umich.edu#endif 4055222Sksewell@umich.edu} 4065222Sksewell@umich.edu 4075222Sksewell@umich.eduFault 4086022Sgblack@eecs.umich.eduTLB::translateData(RequestPtr req, ThreadContext *tc, bool write) 4095222Sksewell@umich.edu{ 4105224Sksewell@umich.edu#if !FULL_SYSTEM 4116038Sksewell@umich.edu //@TODO: This should actually use TLB instead of going directly 4126038Sksewell@umich.edu // to the page table in syscall mode. 4136038Sksewell@umich.edu /** 4146038Sksewell@umich.edu * Check for alignment faults 4156038Sksewell@umich.edu */ 4166038Sksewell@umich.edu if (req->getVaddr() & (req->getSize() - 1)) { 4176038Sksewell@umich.edu DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(), 4186038Sksewell@umich.edu req->getSize()); 4196038Sksewell@umich.edu return new AlignmentFault(); 4206038Sksewell@umich.edu } 4216038Sksewell@umich.edu 4226038Sksewell@umich.edu 4235224Sksewell@umich.edu Process * p = tc->getProcessPtr(); 4245224Sksewell@umich.edu 4255224Sksewell@umich.edu Fault fault = p->pTable->translate(req); 4266378Sgblack@eecs.umich.edu if (fault != NoFault) 4275224Sksewell@umich.edu return fault; 4285224Sksewell@umich.edu 4295224Sksewell@umich.edu return NoFault; 4305224Sksewell@umich.edu#else 4316378Sgblack@eecs.umich.edu if (IsKSeg0(req->getVaddr())) { 4326378Sgblack@eecs.umich.edu // Address will not be translated through TLB, set response, and go! 4336378Sgblack@eecs.umich.edu req->setPaddr(KSeg02Phys(req->getVaddr())); 4346378Sgblack@eecs.umich.edu if (getOperatingMode(tc->readMiscReg(Status)) != mode_kernel || 4356378Sgblack@eecs.umich.edu req->isMisaligned()) { 4366378Sgblack@eecs.umich.edu StoreAddressErrorFault *Flt = new StoreAddressErrorFault(); 4376378Sgblack@eecs.umich.edu /* BadVAddr must be set */ 4386379Sgblack@eecs.umich.edu Flt->badVAddr = req->getVaddr(); 4396378Sgblack@eecs.umich.edu 4406378Sgblack@eecs.umich.edu return Flt; 4416378Sgblack@eecs.umich.edu } 4426378Sgblack@eecs.umich.edu } else if(IsKSeg1(req->getVaddr())) { 4435222Sksewell@umich.edu // Address will not be translated through TLB, set response, and go! 4446378Sgblack@eecs.umich.edu req->setPaddr(KSeg02Phys(req->getVaddr())); 4456378Sgblack@eecs.umich.edu } else { 4466378Sgblack@eecs.umich.edu /* 4476378Sgblack@eecs.umich.edu * This is an optimization - smallPages is updated every time a TLB 4486378Sgblack@eecs.umich.edu * operation is performed. That way, we don't need to look at 4496378Sgblack@eecs.umich.edu * Config3 _ SP and PageGrain _ ESP every time we do a TLB lookup 4506378Sgblack@eecs.umich.edu */ 4516378Sgblack@eecs.umich.edu Addr VPN = ((req->getVaddr() >> 11) & 0xFFFFFFFC); 4526378Sgblack@eecs.umich.edu if (smallPages == 1) { 4536378Sgblack@eecs.umich.edu VPN = ((req->getVaddr() >> 11)); 4546378Sgblack@eecs.umich.edu } 4556378Sgblack@eecs.umich.edu uint8_t Asid = req->getAsid(); 4566378Sgblack@eecs.umich.edu PTE *pte = lookup(VPN, Asid); 4576378Sgblack@eecs.umich.edu if (req->isMisaligned()) { 4586378Sgblack@eecs.umich.edu // Unaligned address! 4596378Sgblack@eecs.umich.edu StoreAddressErrorFault *Flt = new StoreAddressErrorFault(); 4606378Sgblack@eecs.umich.edu /* BadVAddr must be set */ 4616379Sgblack@eecs.umich.edu Flt->badVAddr = req->getVaddr(); 4626378Sgblack@eecs.umich.edu return Flt; 4636378Sgblack@eecs.umich.edu } 4646378Sgblack@eecs.umich.edu if (pte != NULL) { 4656378Sgblack@eecs.umich.edu // Ok, found something 4666378Sgblack@eecs.umich.edu /* Check for valid bits */ 4676378Sgblack@eecs.umich.edu int EvenOdd; 4686378Sgblack@eecs.umich.edu bool Valid; 4696378Sgblack@eecs.umich.edu bool Dirty; 4706378Sgblack@eecs.umich.edu if (((((req->getVaddr()) >> pte->AddrShiftAmount) & 1)) == 0) { 4716378Sgblack@eecs.umich.edu // Check even bits 4726378Sgblack@eecs.umich.edu Valid = pte->V0; 4736378Sgblack@eecs.umich.edu Dirty = pte->D0; 4746378Sgblack@eecs.umich.edu EvenOdd = 0; 4756378Sgblack@eecs.umich.edu } else { 4766378Sgblack@eecs.umich.edu // Check odd bits 4776378Sgblack@eecs.umich.edu Valid = pte->V1; 4786378Sgblack@eecs.umich.edu Dirty = pte->D1; 4796378Sgblack@eecs.umich.edu EvenOdd = 1; 4806378Sgblack@eecs.umich.edu } 4815222Sksewell@umich.edu 4826378Sgblack@eecs.umich.edu if (Valid == false) { 4836378Sgblack@eecs.umich.edu //Invalid entry 4846378Sgblack@eecs.umich.edu DtbInvalidFault *Flt = new DtbInvalidFault(); 4856378Sgblack@eecs.umich.edu /* EntryHi VPN, ASID fields must be set */ 4866379Sgblack@eecs.umich.edu Flt->entryHiAsid = Asid; 4876379Sgblack@eecs.umich.edu Flt->entryHiVPN2 = (VPN>>2); 4886379Sgblack@eecs.umich.edu Flt->entryHiVPN2X = (VPN & 0x3); 4895222Sksewell@umich.edu 4906378Sgblack@eecs.umich.edu /* BadVAddr must be set */ 4916379Sgblack@eecs.umich.edu Flt->badVAddr = req->getVaddr(); 4925222Sksewell@umich.edu 4936378Sgblack@eecs.umich.edu /* Context must be set */ 4946379Sgblack@eecs.umich.edu Flt->contextBadVPN2 = (VPN >> 2); 4955222Sksewell@umich.edu 4966378Sgblack@eecs.umich.edu return Flt; 4976378Sgblack@eecs.umich.edu } else { 4986378Sgblack@eecs.umich.edu // Ok, this is really a match, set paddr 4996378Sgblack@eecs.umich.edu if (!Dirty) { 5006378Sgblack@eecs.umich.edu TLBModifiedFault *Flt = new TLBModifiedFault(); 5016378Sgblack@eecs.umich.edu /* EntryHi VPN, ASID fields must be set */ 5026379Sgblack@eecs.umich.edu Flt->entryHiAsid = Asid; 5036379Sgblack@eecs.umich.edu Flt->entryHiVPN2 = (VPN >> 2); 5046379Sgblack@eecs.umich.edu Flt->entryHiVPN2X = (VPN & 0x3); 5055222Sksewell@umich.edu 5066378Sgblack@eecs.umich.edu /* BadVAddr must be set */ 5076379Sgblack@eecs.umich.edu Flt->badVAddr = req->getVaddr(); 5085222Sksewell@umich.edu 5096378Sgblack@eecs.umich.edu /* Context must be set */ 5106379Sgblack@eecs.umich.edu Flt->contextBadVPN2 = (VPN >> 2); 5116378Sgblack@eecs.umich.edu return Flt; 5126378Sgblack@eecs.umich.edu } 5136378Sgblack@eecs.umich.edu Addr PAddr; 5146378Sgblack@eecs.umich.edu if (EvenOdd == 0) { 5156378Sgblack@eecs.umich.edu PAddr = pte->PFN0; 5166378Sgblack@eecs.umich.edu } else { 5176378Sgblack@eecs.umich.edu PAddr = pte->PFN1; 5186378Sgblack@eecs.umich.edu } 5196378Sgblack@eecs.umich.edu PAddr >>= (pte->AddrShiftAmount - 12); 5206378Sgblack@eecs.umich.edu PAddr <<= pte->AddrShiftAmount; 5216378Sgblack@eecs.umich.edu PAddr |= ((req->getVaddr()) & pte->OffsetMask); 5226378Sgblack@eecs.umich.edu req->setPaddr(PAddr); 5236378Sgblack@eecs.umich.edu } 5246378Sgblack@eecs.umich.edu } else { 5256378Sgblack@eecs.umich.edu // Didn't find any match, return a TLB Refill Exception 5266378Sgblack@eecs.umich.edu DtbRefillFault *Flt = new DtbRefillFault(); 5276378Sgblack@eecs.umich.edu /* EntryHi VPN, ASID fields must be set */ 5286379Sgblack@eecs.umich.edu Flt->entryHiAsid = Asid; 5296379Sgblack@eecs.umich.edu Flt->entryHiVPN2 = (VPN >> 2); 5306379Sgblack@eecs.umich.edu Flt->entryHiVPN2X = (VPN & 0x3); 5315222Sksewell@umich.edu 5326378Sgblack@eecs.umich.edu /* BadVAddr must be set */ 5336379Sgblack@eecs.umich.edu Flt->badVAddr = req->getVaddr(); 5345222Sksewell@umich.edu 5356378Sgblack@eecs.umich.edu /* Context must be set */ 5366379Sgblack@eecs.umich.edu Flt->contextBadVPN2 = (VPN >> 2); 5376378Sgblack@eecs.umich.edu return Flt; 5385222Sksewell@umich.edu } 5395222Sksewell@umich.edu } 5405222Sksewell@umich.edu return checkCacheability(req); 5415224Sksewell@umich.edu#endif 5425222Sksewell@umich.edu} 5435222Sksewell@umich.edu 5446022Sgblack@eecs.umich.eduFault 5456023Snate@binkert.orgTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 5466022Sgblack@eecs.umich.edu{ 5476023Snate@binkert.org if (mode == Execute) 5486022Sgblack@eecs.umich.edu return translateInst(req, tc); 5496022Sgblack@eecs.umich.edu else 5506023Snate@binkert.org return translateData(req, tc, mode == Write); 5516022Sgblack@eecs.umich.edu} 5526022Sgblack@eecs.umich.edu 5535894Sgblack@eecs.umich.eduvoid 5546022Sgblack@eecs.umich.eduTLB::translateTiming(RequestPtr req, ThreadContext *tc, 5556023Snate@binkert.org Translation *translation, Mode mode) 5565894Sgblack@eecs.umich.edu{ 5575894Sgblack@eecs.umich.edu assert(translation); 5586023Snate@binkert.org translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 5595894Sgblack@eecs.umich.edu} 5605894Sgblack@eecs.umich.edu 5615222Sksewell@umich.edu 5625222Sksewell@umich.eduMipsISA::PTE & 5635222Sksewell@umich.eduTLB::index(bool advance) 5645222Sksewell@umich.edu{ 5656378Sgblack@eecs.umich.edu PTE *pte = &table[nlu]; 5665222Sksewell@umich.edu 5675222Sksewell@umich.edu if (advance) 5685222Sksewell@umich.edu nextnlu(); 5695222Sksewell@umich.edu 5705222Sksewell@umich.edu return *pte; 5715222Sksewell@umich.edu} 5724997Sgblack@eecs.umich.edu 5736022Sgblack@eecs.umich.eduMipsISA::TLB * 5746022Sgblack@eecs.umich.eduMipsTLBParams::create() 5754997Sgblack@eecs.umich.edu{ 5766378Sgblack@eecs.umich.edu return new TLB(this); 5774997Sgblack@eecs.umich.edu} 578