tlb.cc revision 6329
14997Sgblack@eecs.umich.edu/* 25268Sksewell@umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 35254Sksewell@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc. 45254Sksewell@umich.edu * All rights reserved. 54997Sgblack@eecs.umich.edu * 65254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 75254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 85254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 95254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 105254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 115254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 125254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 135254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 145254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 155254Sksewell@umich.edu * this software without specific prior written permission. 164997Sgblack@eecs.umich.edu * 175254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245254Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255254Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265254Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275254Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 284997Sgblack@eecs.umich.edu * 295268Sksewell@umich.edu * Authors: Nathan Binkert 305268Sksewell@umich.edu * Steve Reinhardt 315268Sksewell@umich.edu * Jaidev Patwardhan 324997Sgblack@eecs.umich.edu */ 334997Sgblack@eecs.umich.edu 345222Sksewell@umich.edu#include <string> 355222Sksewell@umich.edu#include <vector> 364997Sgblack@eecs.umich.edu 375222Sksewell@umich.edu#include "arch/mips/pra_constants.hh" 385222Sksewell@umich.edu#include "arch/mips/pagetable.hh" 394997Sgblack@eecs.umich.edu#include "arch/mips/tlb.hh" 405222Sksewell@umich.edu#include "arch/mips/faults.hh" 415222Sksewell@umich.edu#include "arch/mips/utility.hh" 425222Sksewell@umich.edu#include "base/inifile.hh" 435222Sksewell@umich.edu#include "base/str.hh" 445222Sksewell@umich.edu#include "base/trace.hh" 455222Sksewell@umich.edu#include "cpu/thread_context.hh" 465224Sksewell@umich.edu#include "sim/process.hh" 475224Sksewell@umich.edu#include "mem/page_table.hh" 485222Sksewell@umich.edu#include "params/MipsTLB.hh" 494997Sgblack@eecs.umich.edu 505019Sgblack@eecs.umich.edu 515222Sksewell@umich.eduusing namespace std; 525222Sksewell@umich.eduusing namespace MipsISA; 535019Sgblack@eecs.umich.edu 545222Sksewell@umich.edu/////////////////////////////////////////////////////////////////////// 555222Sksewell@umich.edu// 565222Sksewell@umich.edu// MIPS TLB 575222Sksewell@umich.edu// 585019Sgblack@eecs.umich.edu 595543Ssaidi@eecs.umich.edu#define MODE2MASK(X) (1 << (X)) 605222Sksewell@umich.edu 616329Sgblack@eecs.umich.edustatic inline mode_type 626329Sgblack@eecs.umich.edugetOperatingMode(MiscReg Stat) 636329Sgblack@eecs.umich.edu{ 646329Sgblack@eecs.umich.edu if((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0) { 656329Sgblack@eecs.umich.edu return mode_kernel; 666329Sgblack@eecs.umich.edu } else if((Stat & 0x18) == 0x8) { 676329Sgblack@eecs.umich.edu return mode_supervisor; 686329Sgblack@eecs.umich.edu } else if((Stat & 0x18) == 0x10) { 696329Sgblack@eecs.umich.edu return mode_user; 706329Sgblack@eecs.umich.edu } else { 716329Sgblack@eecs.umich.edu return mode_number; 726329Sgblack@eecs.umich.edu } 736329Sgblack@eecs.umich.edu} 746329Sgblack@eecs.umich.edu 756329Sgblack@eecs.umich.edu 765222Sksewell@umich.eduTLB::TLB(const Params *p) 775358Sgblack@eecs.umich.edu : BaseTLB(p), size(p->size), nlu(0) 785222Sksewell@umich.edu{ 795222Sksewell@umich.edu table = new MipsISA::PTE[size]; 805222Sksewell@umich.edu memset(table, 0, sizeof(MipsISA::PTE[size])); 815222Sksewell@umich.edu smallPages=0; 825222Sksewell@umich.edu} 835222Sksewell@umich.edu 845222Sksewell@umich.eduTLB::~TLB() 855222Sksewell@umich.edu{ 865222Sksewell@umich.edu if (table) 875222Sksewell@umich.edu delete [] table; 885222Sksewell@umich.edu} 895222Sksewell@umich.edu 905222Sksewell@umich.edu// look up an entry in the TLB 915222Sksewell@umich.eduMipsISA::PTE * 925222Sksewell@umich.eduTLB::lookup(Addr vpn, uint8_t asn) const 935222Sksewell@umich.edu{ 945222Sksewell@umich.edu // assume not found... 955222Sksewell@umich.edu MipsISA::PTE *retval = NULL; 965222Sksewell@umich.edu PageTable::const_iterator i = lookupTable.find(vpn); 975222Sksewell@umich.edu if (i != lookupTable.end()) { 985222Sksewell@umich.edu while (i->first == vpn) { 995222Sksewell@umich.edu int index = i->second; 1005222Sksewell@umich.edu MipsISA::PTE *pte = &table[index]; 1015222Sksewell@umich.edu 1025222Sksewell@umich.edu /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */ 1035222Sksewell@umich.edu Addr Mask = pte->Mask; 1045222Sksewell@umich.edu Addr InvMask = ~Mask; 1055222Sksewell@umich.edu Addr VPN = pte->VPN; 1065543Ssaidi@eecs.umich.edu // warn("Valid: %d - %d\n",pte->V0,pte->V1); 1075222Sksewell@umich.edu if(((vpn & InvMask) == (VPN & InvMask)) && (pte->G || (asn == pte->asid))) 1085222Sksewell@umich.edu { // We have a VPN + ASID Match 1095222Sksewell@umich.edu retval = pte; 1105222Sksewell@umich.edu break; 1115222Sksewell@umich.edu } 1125222Sksewell@umich.edu ++i; 1135222Sksewell@umich.edu } 1145019Sgblack@eecs.umich.edu } 1155019Sgblack@eecs.umich.edu 1165222Sksewell@umich.edu DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 1175222Sksewell@umich.edu retval ? "hit" : "miss", retval ? retval->PFN1 : 0); 1185222Sksewell@umich.edu return retval; 1195222Sksewell@umich.edu} 1205222Sksewell@umich.edu 1215222Sksewell@umich.eduMipsISA::PTE* TLB::getEntry(unsigned Index) const 1225222Sksewell@umich.edu{ 1235222Sksewell@umich.edu // Make sure that Index is valid 1245222Sksewell@umich.edu assert(Index<size); 1255222Sksewell@umich.edu return &table[Index]; 1265222Sksewell@umich.edu} 1275222Sksewell@umich.edu 1285222Sksewell@umich.eduint TLB::probeEntry(Addr vpn,uint8_t asn) const 1295222Sksewell@umich.edu{ 1305222Sksewell@umich.edu // assume not found... 1315222Sksewell@umich.edu MipsISA::PTE *retval = NULL; 1325222Sksewell@umich.edu int Ind=-1; 1335222Sksewell@umich.edu PageTable::const_iterator i = lookupTable.find(vpn); 1345222Sksewell@umich.edu if (i != lookupTable.end()) { 1355222Sksewell@umich.edu while (i->first == vpn) { 1365222Sksewell@umich.edu int index = i->second; 1375222Sksewell@umich.edu MipsISA::PTE *pte = &table[index]; 1385222Sksewell@umich.edu 1395222Sksewell@umich.edu /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */ 1405222Sksewell@umich.edu Addr Mask = pte->Mask; 1415222Sksewell@umich.edu Addr InvMask = ~Mask; 1425222Sksewell@umich.edu Addr VPN = pte->VPN; 1435222Sksewell@umich.edu if(((vpn & InvMask) == (VPN & InvMask)) && (pte->G || (asn == pte->asid))) 1445222Sksewell@umich.edu { // We have a VPN + ASID Match 1455222Sksewell@umich.edu retval = pte; 1465222Sksewell@umich.edu Ind = index; 1475222Sksewell@umich.edu break; 1485222Sksewell@umich.edu } 1495222Sksewell@umich.edu 1505222Sksewell@umich.edu ++i; 1515222Sksewell@umich.edu } 1525222Sksewell@umich.edu } 1535222Sksewell@umich.edu DPRINTF(MipsPRA,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn,asn,Ind); 1545222Sksewell@umich.edu return Ind; 1555222Sksewell@umich.edu} 1565222Sksewell@umich.eduFault inline 1575222Sksewell@umich.eduTLB::checkCacheability(RequestPtr &req) 1585222Sksewell@umich.edu{ 1595222Sksewell@umich.edu Addr VAddrUncacheable = 0xA0000000; 1605222Sksewell@umich.edu // In MIPS, cacheability is controlled by certain bits of the virtual address 1615222Sksewell@umich.edu // or by the TLB entry 1625222Sksewell@umich.edu if((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) { 1635222Sksewell@umich.edu // mark request as uncacheable 1645736Snate@binkert.org req->setFlags(Request::UNCACHEABLE); 1655222Sksewell@umich.edu } 1665222Sksewell@umich.edu return NoFault; 1675222Sksewell@umich.edu} 1685222Sksewell@umich.eduvoid TLB::insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages) 1695222Sksewell@umich.edu{ 1705222Sksewell@umich.edu smallPages=_smallPages; 1715222Sksewell@umich.edu if(Index > size){ 1725222Sksewell@umich.edu warn("Attempted to write at index (%d) beyond TLB size (%d)",Index,size); 1735222Sksewell@umich.edu } else { 1745222Sksewell@umich.edu // Update TLB 1755222Sksewell@umich.edu DPRINTF(TLB,"TLB[%d]: %x %x %x %x\n",Index,pte.Mask<<11,((pte.VPN << 11) | pte.asid),((pte.PFN0 <<6) | (pte.C0 << 3) | (pte.D0 << 2) | (pte.V0 <<1) | pte.G), 1765222Sksewell@umich.edu ((pte.PFN1 <<6) | (pte.C1 << 3) | (pte.D1 << 2) | (pte.V1 <<1) | pte.G)); 1775222Sksewell@umich.edu if(table[Index].V0 == true || table[Index].V1 == true){ // Previous entry is valid 1785222Sksewell@umich.edu PageTable::iterator i = lookupTable.find(table[Index].VPN); 1795222Sksewell@umich.edu lookupTable.erase(i); 1805222Sksewell@umich.edu } 1815222Sksewell@umich.edu table[Index]=pte; 1825222Sksewell@umich.edu // Update fast lookup table 1835222Sksewell@umich.edu lookupTable.insert(make_pair(table[Index].VPN, Index)); 1845222Sksewell@umich.edu // int TestIndex=probeEntry(pte.VPN,pte.asid); 1855222Sksewell@umich.edu // warn("Inserted at: %d, Found at: %d (%x)\n",Index,TestIndex,pte.Mask); 1865222Sksewell@umich.edu } 1875222Sksewell@umich.edu 1885222Sksewell@umich.edu} 1895222Sksewell@umich.edu 1905222Sksewell@umich.edu// insert a new TLB entry 1915222Sksewell@umich.eduvoid 1925222Sksewell@umich.eduTLB::insert(Addr addr, MipsISA::PTE &pte) 1935222Sksewell@umich.edu{ 1945222Sksewell@umich.edu fatal("TLB Insert not yet implemented\n"); 1955222Sksewell@umich.edu 1965222Sksewell@umich.edu 1975222Sksewell@umich.edu /* MipsISA::VAddr vaddr = addr; 1985222Sksewell@umich.edu if (table[nlu].valid) { 1995222Sksewell@umich.edu Addr oldvpn = table[nlu].tag; 2005222Sksewell@umich.edu PageTable::iterator i = lookupTable.find(oldvpn); 2015222Sksewell@umich.edu 2025222Sksewell@umich.edu if (i == lookupTable.end()) 2035222Sksewell@umich.edu panic("TLB entry not found in lookupTable"); 2045222Sksewell@umich.edu 2055222Sksewell@umich.edu int index; 2065222Sksewell@umich.edu while ((index = i->second) != nlu) { 2075222Sksewell@umich.edu if (table[index].tag != oldvpn) 2085222Sksewell@umich.edu panic("TLB entry not found in lookupTable"); 2095222Sksewell@umich.edu 2105222Sksewell@umich.edu ++i; 2115222Sksewell@umich.edu } 2125222Sksewell@umich.edu 2135222Sksewell@umich.edu DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn); 2145222Sksewell@umich.edu 2155222Sksewell@umich.edu lookupTable.erase(i); 2165014Sgblack@eecs.umich.edu } 2175014Sgblack@eecs.umich.edu 2185222Sksewell@umich.edu DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn); 2195222Sksewell@umich.edu 2205222Sksewell@umich.edu table[nlu] = pte; 2215222Sksewell@umich.edu table[nlu].tag = vaddr.vpn(); 2225222Sksewell@umich.edu table[nlu].valid = true; 2235222Sksewell@umich.edu 2245222Sksewell@umich.edu lookupTable.insert(make_pair(vaddr.vpn(), nlu)); 2255222Sksewell@umich.edu nextnlu(); 2265222Sksewell@umich.edu */ 2275222Sksewell@umich.edu} 2285222Sksewell@umich.edu 2295222Sksewell@umich.eduvoid 2305222Sksewell@umich.eduTLB::flushAll() 2315222Sksewell@umich.edu{ 2325222Sksewell@umich.edu DPRINTF(TLB, "flushAll\n"); 2335222Sksewell@umich.edu memset(table, 0, sizeof(MipsISA::PTE[size])); 2345222Sksewell@umich.edu lookupTable.clear(); 2355222Sksewell@umich.edu nlu = 0; 2365222Sksewell@umich.edu} 2375222Sksewell@umich.edu 2385222Sksewell@umich.eduvoid 2395222Sksewell@umich.eduTLB::serialize(ostream &os) 2405222Sksewell@umich.edu{ 2415222Sksewell@umich.edu SERIALIZE_SCALAR(size); 2425222Sksewell@umich.edu SERIALIZE_SCALAR(nlu); 2435222Sksewell@umich.edu 2445222Sksewell@umich.edu for (int i = 0; i < size; i++) { 2455222Sksewell@umich.edu nameOut(os, csprintf("%s.PTE%d", name(), i)); 2465222Sksewell@umich.edu table[i].serialize(os); 2475222Sksewell@umich.edu } 2485222Sksewell@umich.edu} 2495222Sksewell@umich.edu 2505222Sksewell@umich.eduvoid 2515222Sksewell@umich.eduTLB::unserialize(Checkpoint *cp, const string §ion) 2525222Sksewell@umich.edu{ 2535222Sksewell@umich.edu UNSERIALIZE_SCALAR(size); 2545222Sksewell@umich.edu UNSERIALIZE_SCALAR(nlu); 2555222Sksewell@umich.edu 2565222Sksewell@umich.edu for (int i = 0; i < size; i++) { 2575222Sksewell@umich.edu table[i].unserialize(cp, csprintf("%s.PTE%d", section, i)); 2585222Sksewell@umich.edu if (table[i].V0 || table[i].V1) { 2595222Sksewell@umich.edu lookupTable.insert(make_pair(table[i].VPN, i)); 2605222Sksewell@umich.edu } 2615222Sksewell@umich.edu } 2625222Sksewell@umich.edu} 2635222Sksewell@umich.edu 2645222Sksewell@umich.eduvoid 2655222Sksewell@umich.eduTLB::regStats() 2665222Sksewell@umich.edu{ 2675222Sksewell@umich.edu read_hits 2685222Sksewell@umich.edu .name(name() + ".read_hits") 2695222Sksewell@umich.edu .desc("DTB read hits") 2705222Sksewell@umich.edu ; 2715222Sksewell@umich.edu 2725222Sksewell@umich.edu read_misses 2735222Sksewell@umich.edu .name(name() + ".read_misses") 2745222Sksewell@umich.edu .desc("DTB read misses") 2755222Sksewell@umich.edu ; 2765222Sksewell@umich.edu 2775222Sksewell@umich.edu 2785222Sksewell@umich.edu read_accesses 2795222Sksewell@umich.edu .name(name() + ".read_accesses") 2805222Sksewell@umich.edu .desc("DTB read accesses") 2815222Sksewell@umich.edu ; 2825222Sksewell@umich.edu 2835222Sksewell@umich.edu write_hits 2845222Sksewell@umich.edu .name(name() + ".write_hits") 2855222Sksewell@umich.edu .desc("DTB write hits") 2865222Sksewell@umich.edu ; 2875222Sksewell@umich.edu 2885222Sksewell@umich.edu write_misses 2895222Sksewell@umich.edu .name(name() + ".write_misses") 2905222Sksewell@umich.edu .desc("DTB write misses") 2915222Sksewell@umich.edu ; 2925222Sksewell@umich.edu 2935222Sksewell@umich.edu 2945222Sksewell@umich.edu write_accesses 2955222Sksewell@umich.edu .name(name() + ".write_accesses") 2965222Sksewell@umich.edu .desc("DTB write accesses") 2975222Sksewell@umich.edu ; 2985222Sksewell@umich.edu 2995222Sksewell@umich.edu hits 3005222Sksewell@umich.edu .name(name() + ".hits") 3015222Sksewell@umich.edu .desc("DTB hits") 3025222Sksewell@umich.edu ; 3035222Sksewell@umich.edu 3045222Sksewell@umich.edu misses 3055222Sksewell@umich.edu .name(name() + ".misses") 3065222Sksewell@umich.edu .desc("DTB misses") 3075222Sksewell@umich.edu ; 3085222Sksewell@umich.edu 3095222Sksewell@umich.edu invalids 3105222Sksewell@umich.edu .name(name() + ".invalids") 3115222Sksewell@umich.edu .desc("DTB access violations") 3125222Sksewell@umich.edu ; 3135222Sksewell@umich.edu 3145222Sksewell@umich.edu accesses 3155222Sksewell@umich.edu .name(name() + ".accesses") 3165222Sksewell@umich.edu .desc("DTB accesses") 3175222Sksewell@umich.edu ; 3185222Sksewell@umich.edu 3195222Sksewell@umich.edu hits = read_hits + write_hits; 3205222Sksewell@umich.edu misses = read_misses + write_misses; 3215222Sksewell@umich.edu accesses = read_accesses + write_accesses; 3225222Sksewell@umich.edu} 3235222Sksewell@umich.edu 3245222Sksewell@umich.eduFault 3256022Sgblack@eecs.umich.eduTLB::translateInst(RequestPtr req, ThreadContext *tc) 3265222Sksewell@umich.edu{ 3275224Sksewell@umich.edu#if !FULL_SYSTEM 3285224Sksewell@umich.edu Process * p = tc->getProcessPtr(); 3295224Sksewell@umich.edu 3305224Sksewell@umich.edu Fault fault = p->pTable->translate(req); 3315224Sksewell@umich.edu if(fault != NoFault) 3325224Sksewell@umich.edu return fault; 3335224Sksewell@umich.edu 3345224Sksewell@umich.edu return NoFault; 3355224Sksewell@umich.edu#else 3365222Sksewell@umich.edu if(MipsISA::IsKSeg0(req->getVaddr())) 3375014Sgblack@eecs.umich.edu { 3385222Sksewell@umich.edu // Address will not be translated through TLB, set response, and go! 3395222Sksewell@umich.edu req->setPaddr(MipsISA::KSeg02Phys(req->getVaddr())); 3405222Sksewell@umich.edu if(MipsISA::getOperatingMode(tc->readMiscReg(MipsISA::Status)) != mode_kernel || req->isMisaligned()) 3415222Sksewell@umich.edu { 3425222Sksewell@umich.edu AddressErrorFault *Flt = new AddressErrorFault(); 3435222Sksewell@umich.edu /* BadVAddr must be set */ 3445222Sksewell@umich.edu Flt->BadVAddr = req->getVaddr(); 3455222Sksewell@umich.edu return Flt; 3465222Sksewell@umich.edu } 3475014Sgblack@eecs.umich.edu } 3485222Sksewell@umich.edu else if(MipsISA::IsKSeg1(req->getVaddr())) 3495222Sksewell@umich.edu { 3505222Sksewell@umich.edu // Address will not be translated through TLB, set response, and go! 3515222Sksewell@umich.edu req->setPaddr(MipsISA::KSeg02Phys(req->getVaddr())); 3525222Sksewell@umich.edu } 3535222Sksewell@umich.edu else 3545222Sksewell@umich.edu { 3555222Sksewell@umich.edu /* This is an optimization - smallPages is updated every time a TLB operation is performed 3565222Sksewell@umich.edu That way, we don't need to look at Config3 _ SP and PageGrain _ ESP every time we 3575222Sksewell@umich.edu do a TLB lookup */ 3585222Sksewell@umich.edu Addr VPN; 3595222Sksewell@umich.edu if(smallPages==1){ 3605222Sksewell@umich.edu VPN=((req->getVaddr() >> 11)); 3615222Sksewell@umich.edu } else { 3625222Sksewell@umich.edu VPN=((req->getVaddr() >> 11) & 0xFFFFFFFC); 3635222Sksewell@umich.edu } 3645222Sksewell@umich.edu uint8_t Asid = req->getAsid(); 3655222Sksewell@umich.edu if(req->isMisaligned()){ // Unaligned address! 3665222Sksewell@umich.edu AddressErrorFault *Flt = new AddressErrorFault(); 3675222Sksewell@umich.edu /* BadVAddr must be set */ 3685222Sksewell@umich.edu Flt->BadVAddr = req->getVaddr(); 3695222Sksewell@umich.edu return Flt; 3705222Sksewell@umich.edu } 3715222Sksewell@umich.edu MipsISA::PTE *pte = lookup(VPN,Asid); 3725222Sksewell@umich.edu if(pte != NULL) 3735222Sksewell@umich.edu {// Ok, found something 3745222Sksewell@umich.edu /* Check for valid bits */ 3755222Sksewell@umich.edu int EvenOdd; 3765222Sksewell@umich.edu bool Valid; 3775222Sksewell@umich.edu if((((req->getVaddr()) >> pte->AddrShiftAmount) & 1) ==0){ 3785222Sksewell@umich.edu // Check even bits 3795222Sksewell@umich.edu Valid = pte->V0; 3805222Sksewell@umich.edu EvenOdd = 0; 3815222Sksewell@umich.edu } else { 3825222Sksewell@umich.edu // Check odd bits 3835222Sksewell@umich.edu Valid = pte->V1; 3845222Sksewell@umich.edu EvenOdd = 1; 3855222Sksewell@umich.edu } 3865222Sksewell@umich.edu 3875222Sksewell@umich.edu if(Valid == false) 3885222Sksewell@umich.edu {//Invalid entry 3895222Sksewell@umich.edu ItbInvalidFault *Flt = new ItbInvalidFault(); 3905222Sksewell@umich.edu /* EntryHi VPN, ASID fields must be set */ 3915222Sksewell@umich.edu Flt->EntryHi_Asid = Asid; 3925222Sksewell@umich.edu Flt->EntryHi_VPN2 = (VPN>>2); 3935222Sksewell@umich.edu Flt->EntryHi_VPN2X = (VPN & 0x3); 3945222Sksewell@umich.edu 3955222Sksewell@umich.edu /* BadVAddr must be set */ 3965222Sksewell@umich.edu Flt->BadVAddr = req->getVaddr(); 3975222Sksewell@umich.edu 3985222Sksewell@umich.edu /* Context must be set */ 3995222Sksewell@umich.edu Flt->Context_BadVPN2 = (VPN >> 2); 4005222Sksewell@umich.edu return Flt; 4015222Sksewell@umich.edu } 4025222Sksewell@umich.edu else 4035222Sksewell@umich.edu {// Ok, this is really a match, set paddr 4045543Ssaidi@eecs.umich.edu // hits++; 4055222Sksewell@umich.edu Addr PAddr; 4065222Sksewell@umich.edu if(EvenOdd == 0){ 4075222Sksewell@umich.edu PAddr = pte->PFN0; 4085222Sksewell@umich.edu }else{ 4095222Sksewell@umich.edu PAddr = pte->PFN1; 4105222Sksewell@umich.edu } 4115222Sksewell@umich.edu PAddr >>= (pte->AddrShiftAmount-12); 4125222Sksewell@umich.edu PAddr <<= pte->AddrShiftAmount; 4135222Sksewell@umich.edu PAddr |= ((req->getVaddr()) & pte->OffsetMask); 4145222Sksewell@umich.edu req->setPaddr(PAddr); 4155222Sksewell@umich.edu 4165222Sksewell@umich.edu 4175222Sksewell@umich.edu } 4185222Sksewell@umich.edu } 4195222Sksewell@umich.edu else 4205222Sksewell@umich.edu { // Didn't find any match, return a TLB Refill Exception 4215543Ssaidi@eecs.umich.edu // misses++; 4225222Sksewell@umich.edu ItbRefillFault *Flt=new ItbRefillFault(); 4235222Sksewell@umich.edu /* EntryHi VPN, ASID fields must be set */ 4245222Sksewell@umich.edu Flt->EntryHi_Asid = Asid; 4255222Sksewell@umich.edu Flt->EntryHi_VPN2 = (VPN>>2); 4265222Sksewell@umich.edu Flt->EntryHi_VPN2X = (VPN & 0x3); 4275222Sksewell@umich.edu 4285222Sksewell@umich.edu 4295222Sksewell@umich.edu /* BadVAddr must be set */ 4305222Sksewell@umich.edu Flt->BadVAddr = req->getVaddr(); 4315222Sksewell@umich.edu 4325222Sksewell@umich.edu /* Context must be set */ 4335222Sksewell@umich.edu Flt->Context_BadVPN2 = (VPN >> 2); 4345222Sksewell@umich.edu return Flt; 4355222Sksewell@umich.edu } 4365222Sksewell@umich.edu } 4375222Sksewell@umich.edu return checkCacheability(req); 4385224Sksewell@umich.edu#endif 4395222Sksewell@umich.edu} 4405222Sksewell@umich.edu 4415222Sksewell@umich.eduFault 4426022Sgblack@eecs.umich.eduTLB::translateData(RequestPtr req, ThreadContext *tc, bool write) 4435222Sksewell@umich.edu{ 4445224Sksewell@umich.edu#if !FULL_SYSTEM 4456038Sksewell@umich.edu //@TODO: This should actually use TLB instead of going directly 4466038Sksewell@umich.edu // to the page table in syscall mode. 4476038Sksewell@umich.edu /** 4486038Sksewell@umich.edu * Check for alignment faults 4496038Sksewell@umich.edu */ 4506038Sksewell@umich.edu if (req->getVaddr() & (req->getSize() - 1)) { 4516038Sksewell@umich.edu DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(), 4526038Sksewell@umich.edu req->getSize()); 4536038Sksewell@umich.edu return new AlignmentFault(); 4546038Sksewell@umich.edu } 4556038Sksewell@umich.edu 4566038Sksewell@umich.edu 4575224Sksewell@umich.edu Process * p = tc->getProcessPtr(); 4585224Sksewell@umich.edu 4595224Sksewell@umich.edu Fault fault = p->pTable->translate(req); 4605224Sksewell@umich.edu if(fault != NoFault) 4615224Sksewell@umich.edu return fault; 4625224Sksewell@umich.edu 4635224Sksewell@umich.edu return NoFault; 4645224Sksewell@umich.edu#else 4655222Sksewell@umich.edu if(MipsISA::IsKSeg0(req->getVaddr())) 4665222Sksewell@umich.edu { 4675222Sksewell@umich.edu // Address will not be translated through TLB, set response, and go! 4685222Sksewell@umich.edu req->setPaddr(MipsISA::KSeg02Phys(req->getVaddr())); 4695222Sksewell@umich.edu if(MipsISA::getOperatingMode(tc->readMiscReg(MipsISA::Status)) != mode_kernel || req->isMisaligned()) 4705222Sksewell@umich.edu { 4715222Sksewell@umich.edu StoreAddressErrorFault *Flt = new StoreAddressErrorFault(); 4725222Sksewell@umich.edu /* BadVAddr must be set */ 4735222Sksewell@umich.edu Flt->BadVAddr = req->getVaddr(); 4745222Sksewell@umich.edu 4755222Sksewell@umich.edu return Flt; 4765222Sksewell@umich.edu } 4775222Sksewell@umich.edu } 4785222Sksewell@umich.edu else if(MipsISA::IsKSeg1(req->getVaddr())) 4795222Sksewell@umich.edu { 4805222Sksewell@umich.edu // Address will not be translated through TLB, set response, and go! 4815222Sksewell@umich.edu req->setPaddr(MipsISA::KSeg02Phys(req->getVaddr())); 4825222Sksewell@umich.edu } 4835222Sksewell@umich.edu else 4845222Sksewell@umich.edu { 4855222Sksewell@umich.edu /* This is an optimization - smallPages is updated every time a TLB operation is performed 4865222Sksewell@umich.edu That way, we don't need to look at Config3 _ SP and PageGrain _ ESP every time we 4875222Sksewell@umich.edu do a TLB lookup */ 4885222Sksewell@umich.edu Addr VPN=((req->getVaddr() >> 11) & 0xFFFFFFFC); 4895222Sksewell@umich.edu if(smallPages==1){ 4905222Sksewell@umich.edu VPN=((req->getVaddr() >> 11)); 4915222Sksewell@umich.edu } 4925222Sksewell@umich.edu uint8_t Asid = req->getAsid(); 4935222Sksewell@umich.edu MipsISA::PTE *pte = lookup(VPN,Asid); 4945222Sksewell@umich.edu if(req->isMisaligned()){ // Unaligned address! 4955222Sksewell@umich.edu StoreAddressErrorFault *Flt = new StoreAddressErrorFault(); 4965222Sksewell@umich.edu /* BadVAddr must be set */ 4975222Sksewell@umich.edu Flt->BadVAddr = req->getVaddr(); 4985222Sksewell@umich.edu return Flt; 4995222Sksewell@umich.edu } 5005222Sksewell@umich.edu if(pte != NULL) 5015222Sksewell@umich.edu {// Ok, found something 5025222Sksewell@umich.edu /* Check for valid bits */ 5035222Sksewell@umich.edu int EvenOdd; 5045222Sksewell@umich.edu bool Valid; 5055222Sksewell@umich.edu bool Dirty; 5065222Sksewell@umich.edu if(((((req->getVaddr()) >> pte->AddrShiftAmount) & 1)) ==0){ 5075222Sksewell@umich.edu // Check even bits 5085222Sksewell@umich.edu Valid = pte->V0; 5095222Sksewell@umich.edu Dirty = pte->D0; 5105222Sksewell@umich.edu EvenOdd = 0; 5115222Sksewell@umich.edu 5125222Sksewell@umich.edu } else { 5135222Sksewell@umich.edu // Check odd bits 5145222Sksewell@umich.edu Valid = pte->V1; 5155222Sksewell@umich.edu Dirty = pte->D1; 5165222Sksewell@umich.edu EvenOdd = 1; 5175222Sksewell@umich.edu } 5185222Sksewell@umich.edu 5195222Sksewell@umich.edu if(Valid == false) 5205222Sksewell@umich.edu {//Invalid entry 5215543Ssaidi@eecs.umich.edu // invalids++; 5225222Sksewell@umich.edu DtbInvalidFault *Flt = new DtbInvalidFault(); 5235222Sksewell@umich.edu /* EntryHi VPN, ASID fields must be set */ 5245222Sksewell@umich.edu Flt->EntryHi_Asid = Asid; 5255222Sksewell@umich.edu Flt->EntryHi_VPN2 = (VPN>>2); 5265222Sksewell@umich.edu Flt->EntryHi_VPN2X = (VPN & 0x3); 5275222Sksewell@umich.edu 5285222Sksewell@umich.edu 5295222Sksewell@umich.edu /* BadVAddr must be set */ 5305222Sksewell@umich.edu Flt->BadVAddr = req->getVaddr(); 5315222Sksewell@umich.edu 5325222Sksewell@umich.edu /* Context must be set */ 5335222Sksewell@umich.edu Flt->Context_BadVPN2 = (VPN >> 2); 5345222Sksewell@umich.edu 5355222Sksewell@umich.edu return Flt; 5365222Sksewell@umich.edu } 5375222Sksewell@umich.edu else 5385222Sksewell@umich.edu {// Ok, this is really a match, set paddr 5395543Ssaidi@eecs.umich.edu // hits++; 5405222Sksewell@umich.edu if(!Dirty) 5415222Sksewell@umich.edu { 5425222Sksewell@umich.edu TLBModifiedFault *Flt = new TLBModifiedFault(); 5435222Sksewell@umich.edu /* EntryHi VPN, ASID fields must be set */ 5445222Sksewell@umich.edu Flt->EntryHi_Asid = Asid; 5455222Sksewell@umich.edu Flt->EntryHi_VPN2 = (VPN>>2); 5465222Sksewell@umich.edu Flt->EntryHi_VPN2X = (VPN & 0x3); 5475222Sksewell@umich.edu 5485222Sksewell@umich.edu 5495222Sksewell@umich.edu /* BadVAddr must be set */ 5505222Sksewell@umich.edu Flt->BadVAddr = req->getVaddr(); 5515222Sksewell@umich.edu 5525222Sksewell@umich.edu /* Context must be set */ 5535222Sksewell@umich.edu Flt->Context_BadVPN2 = (VPN >> 2); 5545222Sksewell@umich.edu return Flt; 5555222Sksewell@umich.edu 5565222Sksewell@umich.edu } 5575222Sksewell@umich.edu Addr PAddr; 5585222Sksewell@umich.edu if(EvenOdd == 0){ 5595222Sksewell@umich.edu PAddr = pte->PFN0; 5605222Sksewell@umich.edu }else{ 5615222Sksewell@umich.edu PAddr = pte->PFN1; 5625222Sksewell@umich.edu } 5635222Sksewell@umich.edu PAddr >>= (pte->AddrShiftAmount-12); 5645222Sksewell@umich.edu PAddr <<= pte->AddrShiftAmount; 5655222Sksewell@umich.edu PAddr |= ((req->getVaddr()) & pte->OffsetMask); 5665222Sksewell@umich.edu req->setPaddr(PAddr); 5675222Sksewell@umich.edu } 5685222Sksewell@umich.edu } 5695222Sksewell@umich.edu else 5705222Sksewell@umich.edu { // Didn't find any match, return a TLB Refill Exception 5715543Ssaidi@eecs.umich.edu // misses++; 5725222Sksewell@umich.edu DtbRefillFault *Flt=new DtbRefillFault(); 5735222Sksewell@umich.edu /* EntryHi VPN, ASID fields must be set */ 5745222Sksewell@umich.edu Flt->EntryHi_Asid = Asid; 5755222Sksewell@umich.edu Flt->EntryHi_VPN2 = (VPN>>2); 5765222Sksewell@umich.edu Flt->EntryHi_VPN2X = (VPN & 0x3); 5775222Sksewell@umich.edu 5785222Sksewell@umich.edu 5795222Sksewell@umich.edu /* BadVAddr must be set */ 5805222Sksewell@umich.edu Flt->BadVAddr = req->getVaddr(); 5815222Sksewell@umich.edu 5825222Sksewell@umich.edu /* Context must be set */ 5835222Sksewell@umich.edu Flt->Context_BadVPN2 = (VPN >> 2); 5845222Sksewell@umich.edu return Flt; 5855222Sksewell@umich.edu } 5865222Sksewell@umich.edu } 5875222Sksewell@umich.edu return checkCacheability(req); 5885224Sksewell@umich.edu#endif 5895222Sksewell@umich.edu} 5905222Sksewell@umich.edu 5916022Sgblack@eecs.umich.eduFault 5926023Snate@binkert.orgTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 5936022Sgblack@eecs.umich.edu{ 5946023Snate@binkert.org if (mode == Execute) 5956022Sgblack@eecs.umich.edu return translateInst(req, tc); 5966022Sgblack@eecs.umich.edu else 5976023Snate@binkert.org return translateData(req, tc, mode == Write); 5986022Sgblack@eecs.umich.edu} 5996022Sgblack@eecs.umich.edu 6005894Sgblack@eecs.umich.eduvoid 6016022Sgblack@eecs.umich.eduTLB::translateTiming(RequestPtr req, ThreadContext *tc, 6026023Snate@binkert.org Translation *translation, Mode mode) 6035894Sgblack@eecs.umich.edu{ 6045894Sgblack@eecs.umich.edu assert(translation); 6056023Snate@binkert.org translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 6065894Sgblack@eecs.umich.edu} 6075894Sgblack@eecs.umich.edu 6085222Sksewell@umich.edu 6095222Sksewell@umich.eduMipsISA::PTE & 6105222Sksewell@umich.eduTLB::index(bool advance) 6115222Sksewell@umich.edu{ 6125222Sksewell@umich.edu MipsISA::PTE *pte = &table[nlu]; 6135222Sksewell@umich.edu 6145222Sksewell@umich.edu if (advance) 6155222Sksewell@umich.edu nextnlu(); 6165222Sksewell@umich.edu 6175222Sksewell@umich.edu return *pte; 6185222Sksewell@umich.edu} 6194997Sgblack@eecs.umich.edu 6206022Sgblack@eecs.umich.eduMipsISA::TLB * 6216022Sgblack@eecs.umich.eduMipsTLBParams::create() 6224997Sgblack@eecs.umich.edu{ 6236022Sgblack@eecs.umich.edu return new MipsISA::TLB(this); 6244997Sgblack@eecs.umich.edu} 625