mt.hh revision 12334
14661Sksewell@umich.edu/* 25268Sksewell@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc. 35268Sksewell@umich.edu * All rights reserved. 44661Sksewell@umich.edu * 55268Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 65268Sksewell@umich.edu * modification, are permitted provided that the following conditions are 75268Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 85268Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 95268Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 105268Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 115268Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 125268Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 135268Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 145268Sksewell@umich.edu * this software without specific prior written permission. 154661Sksewell@umich.edu * 165268Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175268Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185268Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195268Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205268Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215268Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225268Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235268Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245268Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255268Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265268Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275222Sksewell@umich.edu * 285254Sksewell@umich.edu * Authors: Korey Sewell 294661Sksewell@umich.edu */ 304661Sksewell@umich.edu 314661Sksewell@umich.edu#ifndef __ARCH_MIPS_MT_HH__ 324661Sksewell@umich.edu#define __ARCH_MIPS_MT_HH__ 334661Sksewell@umich.edu 344661Sksewell@umich.edu/** 354661Sksewell@umich.edu * @file 364661Sksewell@umich.edu * 374661Sksewell@umich.edu * ISA-specific helper functions for multithreaded execution. 384661Sksewell@umich.edu */ 394661Sksewell@umich.edu 408229Snate@binkert.org#include <iostream> 418229Snate@binkert.org 424661Sksewell@umich.edu#include "arch/mips/faults.hh" 436329Sgblack@eecs.umich.edu#include "arch/mips/isa_traits.hh" 444661Sksewell@umich.edu#include "arch/mips/mt_constants.hh" 456376Sgblack@eecs.umich.edu#include "arch/mips/pra_constants.hh" 466329Sgblack@eecs.umich.edu#include "arch/mips/registers.hh" 474661Sksewell@umich.edu#include "base/bitfield.hh" 4812334Sgabeblack@google.com#include "base/logging.hh" 494661Sksewell@umich.edu#include "base/trace.hh" 504661Sksewell@umich.edu 514661Sksewell@umich.edunamespace MipsISA 524661Sksewell@umich.edu{ 534661Sksewell@umich.edu 544661Sksewell@umich.edutemplate <class TC> 554661Sksewell@umich.eduinline unsigned 564661Sksewell@umich.edugetVirtProcNum(TC *tc) 574661Sksewell@umich.edu{ 586383Sgblack@eecs.umich.edu TCBindReg tcbind = tc->readMiscRegNoEffect(MISCREG_TC_BIND); 596376Sgblack@eecs.umich.edu return tcbind.curVPE; 604661Sksewell@umich.edu} 614661Sksewell@umich.edu 624661Sksewell@umich.edutemplate <class TC> 634661Sksewell@umich.eduinline unsigned 644661Sksewell@umich.edugetTargetThread(TC *tc) 654661Sksewell@umich.edu{ 666383Sgblack@eecs.umich.edu VPEControlReg vpeCtrl = tc->readMiscRegNoEffect(MISCREG_VPE_CONTROL); 676376Sgblack@eecs.umich.edu return vpeCtrl.targTC; 684661Sksewell@umich.edu} 694661Sksewell@umich.edu 704661Sksewell@umich.edutemplate <class TC> 714661Sksewell@umich.eduinline void 724661Sksewell@umich.eduhaltThread(TC *tc) 734661Sksewell@umich.edu{ 744661Sksewell@umich.edu if (tc->status() == TC::Active) { 754661Sksewell@umich.edu tc->halt(); 764661Sksewell@umich.edu 774661Sksewell@umich.edu // Save last known PC in TCRestart 786378Sgblack@eecs.umich.edu // @TODO: Needs to check if this is a branch and if so, 796378Sgblack@eecs.umich.edu // take previous instruction 807720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 817720Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TC_RESTART, pc.npc()); 824661Sksewell@umich.edu 836378Sgblack@eecs.umich.edu warn("%i: Halting thread %i in %s @ PC %x, setting restart PC to %x", 847823Ssteve.reinhardt@amd.com curTick(), tc->threadId(), tc->getCpuPtr()->name(), 857720Sgblack@eecs.umich.edu pc.pc(), pc.npc()); 864661Sksewell@umich.edu } 874661Sksewell@umich.edu} 884661Sksewell@umich.edu 894661Sksewell@umich.edutemplate <class TC> 904661Sksewell@umich.eduinline void 914661Sksewell@umich.edurestoreThread(TC *tc) 924661Sksewell@umich.edu{ 934661Sksewell@umich.edu if (tc->status() != TC::Active) { 944661Sksewell@umich.edu // Restore PC from TCRestart 957720Sgblack@eecs.umich.edu Addr restartPC = tc->readMiscRegNoEffect(MISCREG_TC_RESTART); 964661Sksewell@umich.edu 974661Sksewell@umich.edu // TODO: SET PC WITH AN EVENT INSTEAD OF INSTANTANEOUSLY 987720Sgblack@eecs.umich.edu tc->pcState(restartPC); 9910407Smitch.hayenga@arm.com tc->activate(); 1004661Sksewell@umich.edu 1016378Sgblack@eecs.umich.edu warn("%i: Restoring thread %i in %s @ PC %x", 1027823Ssteve.reinhardt@amd.com curTick(), tc->threadId(), tc->getCpuPtr()->name(), restartPC); 1034661Sksewell@umich.edu } 1044661Sksewell@umich.edu} 1054661Sksewell@umich.edu 1064661Sksewell@umich.edutemplate <class TC> 1074661Sksewell@umich.eduvoid 1084661Sksewell@umich.eduforkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt) 1094661Sksewell@umich.edu{ 1106383Sgblack@eecs.umich.edu MVPConf0Reg mvpConf = tc->readMiscRegNoEffect(MISCREG_MVP_CONF0); 1116376Sgblack@eecs.umich.edu int num_threads = mvpConf.ptc + 1; 1124661Sksewell@umich.edu 1134661Sksewell@umich.edu int success = 0; 1146221Snate@binkert.org for (ThreadID tid = 0; tid < num_threads && success == 0; tid++) { 1156376Sgblack@eecs.umich.edu TCBindReg tidTCBind = 11612104Snathanael.premillieu@arm.com tc->readRegOtherThread(RegId(MiscRegClass, MISCREG_TC_BIND), tid); 1176383Sgblack@eecs.umich.edu TCBindReg tcBind = tc->readMiscRegNoEffect(MISCREG_TC_BIND); 1184661Sksewell@umich.edu 1196424Snate@binkert.org if (tidTCBind.curVPE == tcBind.curVPE) { 1204661Sksewell@umich.edu 1216376Sgblack@eecs.umich.edu TCStatusReg tidTCStatus = 12212104Snathanael.premillieu@arm.com tc->readRegOtherThread(RegId(MiscRegClass, MISCREG_TC_STATUS), 12312104Snathanael.premillieu@arm.com tid); 1244661Sksewell@umich.edu 1256376Sgblack@eecs.umich.edu TCHaltReg tidTCHalt = 12612104Snathanael.premillieu@arm.com tc->readRegOtherThread(RegId(MiscRegClass, MISCREG_TC_HALT), 12712104Snathanael.premillieu@arm.com tid); 1284661Sksewell@umich.edu 1296376Sgblack@eecs.umich.edu if (tidTCStatus.da == 1 && tidTCHalt.h == 0 && 1306376Sgblack@eecs.umich.edu tidTCStatus.a == 0 && success == 0) { 1314661Sksewell@umich.edu 13212104Snathanael.premillieu@arm.com tc->setRegOtherThread(RegId(MiscRegClass, MISCREG_TC_RESTART), 13312104Snathanael.premillieu@arm.com Rs, tid); 13412104Snathanael.premillieu@arm.com tc->setRegOtherThread(RegId(IntRegClass, Rd_bits), Rt, tid); 1354661Sksewell@umich.edu 1366383Sgblack@eecs.umich.edu StatusReg status = tc->readMiscReg(MISCREG_STATUS); 1376383Sgblack@eecs.umich.edu TCStatusReg tcStatus = tc->readMiscReg(MISCREG_TC_STATUS); 1384661Sksewell@umich.edu 1394661Sksewell@umich.edu // Set Run-State to Running 1406376Sgblack@eecs.umich.edu tidTCStatus.rnst = 0; 1414661Sksewell@umich.edu // Set Delay-Slot to 0 1426376Sgblack@eecs.umich.edu tidTCStatus.tds = 0; 1434661Sksewell@umich.edu // Set Dirty TC to 1 1446376Sgblack@eecs.umich.edu tidTCStatus.dt = 1; 1454661Sksewell@umich.edu // Set Activated to 1 1466376Sgblack@eecs.umich.edu tidTCStatus.a = 1; 1474661Sksewell@umich.edu // Set status to previous thread's status 1486376Sgblack@eecs.umich.edu tidTCStatus.tksu = status.ksu; 1494661Sksewell@umich.edu // Set ASID to previous thread's state 1506376Sgblack@eecs.umich.edu tidTCStatus.asid = tcStatus.asid; 1514661Sksewell@umich.edu 1524661Sksewell@umich.edu // Write Status Register 15312104Snathanael.premillieu@arm.com tc->setRegOtherThread(RegId(MiscRegClass, MISCREG_TC_STATUS), 1546376Sgblack@eecs.umich.edu tidTCStatus, tid); 1554661Sksewell@umich.edu 1564661Sksewell@umich.edu // Mark As Successful Fork 1574661Sksewell@umich.edu success = 1; 1584661Sksewell@umich.edu } 1594661Sksewell@umich.edu } else { 1605991Ssteve.reinhardt@amd.com std::cerr << "Bad VPEs" << std::endl; 1614661Sksewell@umich.edu } 1624661Sksewell@umich.edu } 1634661Sksewell@umich.edu 1644661Sksewell@umich.edu if (success == 0) { 1656383Sgblack@eecs.umich.edu VPEControlReg vpeControl = 1666383Sgblack@eecs.umich.edu tc->readMiscRegNoEffect(MISCREG_VPE_CONTROL); 1676376Sgblack@eecs.umich.edu vpeControl.excpt = 1; 1686383Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_VPE_CONTROL, vpeControl); 16910474Sandreas.hansson@arm.com fault = std::make_shared<ThreadFault>(); 1704661Sksewell@umich.edu } 1714661Sksewell@umich.edu} 1724661Sksewell@umich.edu 1734661Sksewell@umich.edu 1744661Sksewell@umich.edutemplate <class TC> 1754661Sksewell@umich.eduint 1764661Sksewell@umich.eduyieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask) 1774661Sksewell@umich.edu{ 1784661Sksewell@umich.edu if (src_reg == 0) { 1796383Sgblack@eecs.umich.edu MVPConf0Reg mvpConf0 = tc->readMiscRegNoEffect(MISCREG_MVP_CONF0); 1806376Sgblack@eecs.umich.edu ThreadID num_threads = mvpConf0.ptc + 1; 1814661Sksewell@umich.edu 1824661Sksewell@umich.edu int ok = 0; 1834661Sksewell@umich.edu 1844661Sksewell@umich.edu // Get Current VPE & TC numbers from calling thread 1856383Sgblack@eecs.umich.edu TCBindReg tcBind = tc->readMiscRegNoEffect(MISCREG_TC_BIND); 1864661Sksewell@umich.edu 1876221Snate@binkert.org for (ThreadID tid = 0; tid < num_threads; tid++) { 1886376Sgblack@eecs.umich.edu TCStatusReg tidTCStatus = 18912104Snathanael.premillieu@arm.com tc->readRegOtherThread(RegId(MiscRegClass, MISCREG_TC_STATUS), 1906383Sgblack@eecs.umich.edu tid); 1916376Sgblack@eecs.umich.edu TCHaltReg tidTCHalt = 19212104Snathanael.premillieu@arm.com tc->readRegOtherThread(RegId(MiscRegClass, MISCREG_TC_HALT), 1936383Sgblack@eecs.umich.edu tid); 1946376Sgblack@eecs.umich.edu TCBindReg tidTCBind = 19512104Snathanael.premillieu@arm.com tc->readRegOtherThread(RegId(MiscRegClass, MISCREG_TC_BIND), 1966383Sgblack@eecs.umich.edu tid); 1974661Sksewell@umich.edu 1986376Sgblack@eecs.umich.edu if (tidTCBind.curVPE == tcBind.curVPE && 1996376Sgblack@eecs.umich.edu tidTCBind.curTC == tcBind.curTC && 2006376Sgblack@eecs.umich.edu tidTCStatus.da == 1 && 2016376Sgblack@eecs.umich.edu tidTCHalt.h == 0 && 2026376Sgblack@eecs.umich.edu tidTCStatus.a == 1) { 2034661Sksewell@umich.edu ok = 1; 2044661Sksewell@umich.edu } 2054661Sksewell@umich.edu } 2064661Sksewell@umich.edu 2074661Sksewell@umich.edu if (ok == 1) { 2086383Sgblack@eecs.umich.edu TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS); 2096376Sgblack@eecs.umich.edu tcStatus.a = 0; 2106383Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TC_STATUS, tcStatus); 2116376Sgblack@eecs.umich.edu warn("%i: Deactivating Hardware Thread Context #%i", 2127823Ssteve.reinhardt@amd.com curTick(), tc->threadId()); 2134661Sksewell@umich.edu } 2144661Sksewell@umich.edu } else if (src_reg > 0) { 2155561Snate@binkert.org if (src_reg && !yield_mask != 0) { 2166383Sgblack@eecs.umich.edu VPEControlReg vpeControl = tc->readMiscReg(MISCREG_VPE_CONTROL); 2176376Sgblack@eecs.umich.edu vpeControl.excpt = 2; 2186383Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_VPE_CONTROL, vpeControl); 21910474Sandreas.hansson@arm.com fault = std::make_shared<ThreadFault>(); 2204661Sksewell@umich.edu } else { 2214661Sksewell@umich.edu } 2224661Sksewell@umich.edu } else if (src_reg != -2) { 2236383Sgblack@eecs.umich.edu TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS); 2246383Sgblack@eecs.umich.edu VPEControlReg vpeControl = 2256383Sgblack@eecs.umich.edu tc->readMiscRegNoEffect(MISCREG_VPE_CONTROL); 2264661Sksewell@umich.edu 2276376Sgblack@eecs.umich.edu if (vpeControl.ysi == 1 && tcStatus.dt == 1 ) { 2286376Sgblack@eecs.umich.edu vpeControl.excpt = 4; 22910474Sandreas.hansson@arm.com fault = std::make_shared<ThreadFault>(); 2304661Sksewell@umich.edu } else { 2314661Sksewell@umich.edu } 2324661Sksewell@umich.edu } 2334661Sksewell@umich.edu 2344661Sksewell@umich.edu return src_reg & yield_mask; 2354661Sksewell@umich.edu} 2364661Sksewell@umich.edu 2374661Sksewell@umich.edu 2384661Sksewell@umich.edu// TC will usually be a object derived from ThreadContext 2394661Sksewell@umich.edu// (src/cpu/thread_context.hh) 2404661Sksewell@umich.edutemplate <class TC> 2414661Sksewell@umich.eduinline void 2424661Sksewell@umich.eduupdateStatusView(TC *tc) 2434661Sksewell@umich.edu{ 2444661Sksewell@umich.edu // TCStatus' register view must be the same as 2454661Sksewell@umich.edu // Status register view for CU, MX, KSU bits 2466383Sgblack@eecs.umich.edu TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS); 2476383Sgblack@eecs.umich.edu StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS); 2484661Sksewell@umich.edu 2496376Sgblack@eecs.umich.edu status.cu = tcStatus.tcu; 2506376Sgblack@eecs.umich.edu status.mx = tcStatus.tmx; 2516376Sgblack@eecs.umich.edu status.ksu = tcStatus.tksu; 2524661Sksewell@umich.edu 2536383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_STATUS, status); 2544661Sksewell@umich.edu} 2554661Sksewell@umich.edu 2564661Sksewell@umich.edu// TC will usually be a object derived from ThreadContext 2574661Sksewell@umich.edu// (src/cpu/thread_context.hh) 2584661Sksewell@umich.edutemplate <class TC> 2594661Sksewell@umich.eduinline void 2604661Sksewell@umich.eduupdateTCStatusView(TC *tc) 2614661Sksewell@umich.edu{ 2624661Sksewell@umich.edu // TCStatus' register view must be the same as 2634661Sksewell@umich.edu // Status register view for CU, MX, KSU bits 2646383Sgblack@eecs.umich.edu TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS); 2656383Sgblack@eecs.umich.edu StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS); 2664661Sksewell@umich.edu 2676376Sgblack@eecs.umich.edu tcStatus.tcu = status.cu; 2686376Sgblack@eecs.umich.edu tcStatus.tmx = status.mx; 2696376Sgblack@eecs.umich.edu tcStatus.tksu = status.ksu; 2704661Sksewell@umich.edu 2716383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus); 2724661Sksewell@umich.edu} 2734661Sksewell@umich.edu 2744661Sksewell@umich.edu} // namespace MipsISA 2754661Sksewell@umich.edu 2764661Sksewell@umich.edu 2774661Sksewell@umich.edu#endif 278