locked_mem.hh revision 6378
14166Sgblack@eecs.umich.edu/* 24166Sgblack@eecs.umich.edu * Copyright (c) 2006-2007 The Regents of The University of Michigan 34166Sgblack@eecs.umich.edu * All rights reserved. 44166Sgblack@eecs.umich.edu * 54166Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 64166Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 74166Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 84166Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 94166Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 104166Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 114166Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 124166Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 134166Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 144166Sgblack@eecs.umich.edu * this software without specific prior written permission. 154166Sgblack@eecs.umich.edu * 164166Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174166Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184166Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194166Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204166Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214166Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224166Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234166Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244166Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254166Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264166Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274166Sgblack@eecs.umich.edu * 284166Sgblack@eecs.umich.edu * Authors: Steve Reinhardt 294166Sgblack@eecs.umich.edu */ 304166Sgblack@eecs.umich.edu 314166Sgblack@eecs.umich.edu#ifndef __ARCH_MIPS_LOCKED_MEM_HH__ 324166Sgblack@eecs.umich.edu#define __ARCH_MIPS_LOCKED_MEM_HH__ 334166Sgblack@eecs.umich.edu 344166Sgblack@eecs.umich.edu/** 354166Sgblack@eecs.umich.edu * @file 364166Sgblack@eecs.umich.edu * 374166Sgblack@eecs.umich.edu * ISA-specific helper functions for locked memory accesses. 384166Sgblack@eecs.umich.edu */ 394166Sgblack@eecs.umich.edu 404166Sgblack@eecs.umich.edu#include "arch/registers.hh" 414166Sgblack@eecs.umich.edu#include "base/misc.hh" 424166Sgblack@eecs.umich.edu#include "base/trace.hh" 434166Sgblack@eecs.umich.edu#include "mem/request.hh" 444166Sgblack@eecs.umich.edu 454166Sgblack@eecs.umich.edu 464166Sgblack@eecs.umich.edunamespace MipsISA 474166Sgblack@eecs.umich.edu{ 484166Sgblack@eecs.umich.edu 494166Sgblack@eecs.umich.edutemplate <class XC> 504166Sgblack@eecs.umich.eduinline void 514166Sgblack@eecs.umich.eduhandleLockedRead(XC *xc, Request *req) 524166Sgblack@eecs.umich.edu{ 534166Sgblack@eecs.umich.edu xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf); 544166Sgblack@eecs.umich.edu xc->setMiscRegNoEffect(LLFlag, true); 554166Sgblack@eecs.umich.edu DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link" 564166Sgblack@eecs.umich.edu " Address set to %x.\n", 574166Sgblack@eecs.umich.edu req->threadId(), req->getPaddr() & ~0xf); 584166Sgblack@eecs.umich.edu} 594166Sgblack@eecs.umich.edu 604166Sgblack@eecs.umich.edutemplate <class XC> 614166Sgblack@eecs.umich.eduinline bool 624166Sgblack@eecs.umich.eduhandleLockedWrite(XC *xc, Request *req) 634166Sgblack@eecs.umich.edu{ 644166Sgblack@eecs.umich.edu if (req->isUncacheable()) { 654166Sgblack@eecs.umich.edu // Funky Turbolaser mailbox access...don't update 664166Sgblack@eecs.umich.edu // result register (see stq_c in decoder.isa) 674166Sgblack@eecs.umich.edu req->setExtraData(2); 684166Sgblack@eecs.umich.edu } else { 694166Sgblack@eecs.umich.edu // standard store conditional 704166Sgblack@eecs.umich.edu bool lock_flag = xc->readMiscRegNoEffect(LLFlag); 714166Sgblack@eecs.umich.edu Addr lock_addr = xc->readMiscRegNoEffect(LLAddr); 724166Sgblack@eecs.umich.edu 734166Sgblack@eecs.umich.edu if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) { 744166Sgblack@eecs.umich.edu // Lock flag not set or addr mismatch in CPU; 754166Sgblack@eecs.umich.edu // don't even bother sending to memory system 764166Sgblack@eecs.umich.edu req->setExtraData(0); 774166Sgblack@eecs.umich.edu xc->setMiscRegNoEffect(LLFlag, false); 784166Sgblack@eecs.umich.edu 794166Sgblack@eecs.umich.edu // the rest of this code is not architectural; 804166Sgblack@eecs.umich.edu // it's just a debugging aid to help detect 814166Sgblack@eecs.umich.edu // livelock by warning on long sequences of failed 824166Sgblack@eecs.umich.edu // store conditionals 834166Sgblack@eecs.umich.edu int stCondFailures = xc->readStCondFailures(); 844166Sgblack@eecs.umich.edu stCondFailures++; 854166Sgblack@eecs.umich.edu xc->setStCondFailures(stCondFailures); 864166Sgblack@eecs.umich.edu if (stCondFailures % 10 == 0) { 874166Sgblack@eecs.umich.edu warn("%i: context %d: %d consecutive " 884166Sgblack@eecs.umich.edu "store conditional failures\n", 894166Sgblack@eecs.umich.edu curTick, xc->contextId(), stCondFailures); 904166Sgblack@eecs.umich.edu } 914166Sgblack@eecs.umich.edu 924166Sgblack@eecs.umich.edu if (stCondFailures == 5000) { 934166Sgblack@eecs.umich.edu panic("Max (5000) Store Conditional Fails Reached. " 944166Sgblack@eecs.umich.edu "Check Code For Deadlock.\n"); 954166Sgblack@eecs.umich.edu } 964166Sgblack@eecs.umich.edu 974166Sgblack@eecs.umich.edu if (!lock_flag){ 984434Ssaidi@eecs.umich.edu DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, " 994166Sgblack@eecs.umich.edu "Store Conditional Failed.\n", 1004166Sgblack@eecs.umich.edu req->threadId()); 1014166Sgblack@eecs.umich.edu } else if ((req->getPaddr() & ~0xf) != lock_addr) { 1024166Sgblack@eecs.umich.edu DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, " 1034166Sgblack@eecs.umich.edu "Store Conditional Failed.\n", 1044166Sgblack@eecs.umich.edu req->threadId()); 1054166Sgblack@eecs.umich.edu } 1064166Sgblack@eecs.umich.edu // store conditional failed already, so don't issue it to mem 1074166Sgblack@eecs.umich.edu return false; 1084166Sgblack@eecs.umich.edu } 1094166Sgblack@eecs.umich.edu } 1104166Sgblack@eecs.umich.edu 1114166Sgblack@eecs.umich.edu return true; 1124166Sgblack@eecs.umich.edu} 1134166Sgblack@eecs.umich.edu 1144166Sgblack@eecs.umich.edu} // namespace MipsISA 1154166Sgblack@eecs.umich.edu 1164166Sgblack@eecs.umich.edu#endif 1174166Sgblack@eecs.umich.edu