locked_mem.hh revision 6378
1/* 2 * Copyright (c) 2006-2007 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#ifndef __ARCH_MIPS_LOCKED_MEM_HH__ 32#define __ARCH_MIPS_LOCKED_MEM_HH__ 33 34/** 35 * @file 36 * 37 * ISA-specific helper functions for locked memory accesses. 38 */ 39 40#include "arch/registers.hh" 41#include "base/misc.hh" 42#include "base/trace.hh" 43#include "mem/request.hh" 44 45 46namespace MipsISA 47{ 48 49template <class XC> 50inline void 51handleLockedRead(XC *xc, Request *req) 52{ 53 xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf); 54 xc->setMiscRegNoEffect(LLFlag, true); 55 DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link" 56 " Address set to %x.\n", 57 req->threadId(), req->getPaddr() & ~0xf); 58} 59 60template <class XC> 61inline bool 62handleLockedWrite(XC *xc, Request *req) 63{ 64 if (req->isUncacheable()) { 65 // Funky Turbolaser mailbox access...don't update 66 // result register (see stq_c in decoder.isa) 67 req->setExtraData(2); 68 } else { 69 // standard store conditional 70 bool lock_flag = xc->readMiscRegNoEffect(LLFlag); 71 Addr lock_addr = xc->readMiscRegNoEffect(LLAddr); 72 73 if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) { 74 // Lock flag not set or addr mismatch in CPU; 75 // don't even bother sending to memory system 76 req->setExtraData(0); 77 xc->setMiscRegNoEffect(LLFlag, false); 78 79 // the rest of this code is not architectural; 80 // it's just a debugging aid to help detect 81 // livelock by warning on long sequences of failed 82 // store conditionals 83 int stCondFailures = xc->readStCondFailures(); 84 stCondFailures++; 85 xc->setStCondFailures(stCondFailures); 86 if (stCondFailures % 10 == 0) { 87 warn("%i: context %d: %d consecutive " 88 "store conditional failures\n", 89 curTick, xc->contextId(), stCondFailures); 90 } 91 92 if (stCondFailures == 5000) { 93 panic("Max (5000) Store Conditional Fails Reached. " 94 "Check Code For Deadlock.\n"); 95 } 96 97 if (!lock_flag){ 98 DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, " 99 "Store Conditional Failed.\n", 100 req->threadId()); 101 } else if ((req->getPaddr() & ~0xf) != lock_addr) { 102 DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, " 103 "Store Conditional Failed.\n", 104 req->threadId()); 105 } 106 // store conditional failed already, so don't issue it to mem 107 return false; 108 } 109 } 110 111 return true; 112} 113 114} // namespace MipsISA 115 116#endif 117