int.isa revision 2495
12SN/A// -*- mode:c++ -*- 21762SN/A 32SN/A//////////////////////////////////////////////////////////////////// 42SN/A// 52SN/A// Integer operate instructions 62SN/A// 72SN/A 82SN/A//Outputs to decoder.hh 92SN/Aoutput header {{ 102SN/A#include <iostream> 112SN/A using namespace std; 122SN/A /** 132SN/A * Base class for integer operations. 142SN/A */ 152SN/A class IntOp : public MipsStaticInst 162SN/A { 172SN/A protected: 182SN/A 192SN/A /// Constructor 202SN/A IntOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 212SN/A MipsStaticInst(mnem, _machInst, __opClass) 222SN/A { 232SN/A } 242SN/A 252SN/A std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 262SN/A }; 272665Ssaidi@eecs.umich.edu 282665Ssaidi@eecs.umich.edu class IntImmOp : public MipsStaticInst 292665Ssaidi@eecs.umich.edu { 302SN/A protected: 312SN/A 322SN/A int16_t imm; 332SN/A int32_t sextImm; 342SN/A uint32_t zextImm; 352SN/A 362SN/A /// Constructor 372432SN/A IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 381147SN/A MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM), 393453Sgblack@eecs.umich.edu sextImm(INTIMM),zextImm(0x0000FFFF & INTIMM) 402984Sgblack@eecs.umich.edu { 412984Sgblack@eecs.umich.edu //If Bit 15 is 1 then Sign Extend 421147SN/A int32_t temp = sextImm & 0x00008000; 432517SN/A if (temp > 0 && mnemonic != "lui") { 442984Sgblack@eecs.umich.edu sextImm |= 0xFFFF0000; 4556SN/A } 462SN/A } 472680Sktlim@umich.edu 482SN/A std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 493453Sgblack@eecs.umich.edu 502SN/A 513453Sgblack@eecs.umich.edu }; 522SN/A 533453Sgblack@eecs.umich.edu}}; 543453Sgblack@eecs.umich.edu 553453Sgblack@eecs.umich.edu//Outputs to decoder.cc 563453Sgblack@eecs.umich.eduoutput decoder {{ 573453Sgblack@eecs.umich.edu std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 582SN/A { 593453Sgblack@eecs.umich.edu std::stringstream ss; 603453Sgblack@eecs.umich.edu 613453Sgblack@eecs.umich.edu ccprintf(ss, "%-10s ", mnemonic); 622SN/A 633453Sgblack@eecs.umich.edu // just print the first dest... if there's a second one, 643453Sgblack@eecs.umich.edu // it's generally implicit 652SN/A if (_numDestRegs > 0) { 663453Sgblack@eecs.umich.edu printReg(ss, _destRegIdx[0]); 673453Sgblack@eecs.umich.edu } 683453Sgblack@eecs.umich.edu 692SN/A ss << ","; 703453Sgblack@eecs.umich.edu 712SN/A // just print the first two source regs... if there's 723453Sgblack@eecs.umich.edu // a third one, it's a read-modify-write dest (Rc), 733453Sgblack@eecs.umich.edu // e.g. for CMOVxx 742SN/A if (_numSrcRegs > 0) { 753453Sgblack@eecs.umich.edu printReg(ss, _srcRegIdx[0]); 763453Sgblack@eecs.umich.edu } 773453Sgblack@eecs.umich.edu 782SN/A if (_numSrcRegs > 1) { 793453Sgblack@eecs.umich.edu ss << ","; 803453Sgblack@eecs.umich.edu printReg(ss, _srcRegIdx[1]); 813453Sgblack@eecs.umich.edu } 823453Sgblack@eecs.umich.edu 833453Sgblack@eecs.umich.edu return ss.str(); 843453Sgblack@eecs.umich.edu } 852SN/A 863453Sgblack@eecs.umich.edu std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 872SN/A { 883453Sgblack@eecs.umich.edu std::stringstream ss; 893453Sgblack@eecs.umich.edu 903453Sgblack@eecs.umich.edu ccprintf(ss, "%-10s ", mnemonic); 913453Sgblack@eecs.umich.edu 922SN/A if (_numDestRegs > 0) { 933453Sgblack@eecs.umich.edu printReg(ss, _destRegIdx[0]); 943453Sgblack@eecs.umich.edu } 953453Sgblack@eecs.umich.edu 963453Sgblack@eecs.umich.edu ss << ","; 973453Sgblack@eecs.umich.edu 983453Sgblack@eecs.umich.edu if (_numSrcRegs > 0) { 993453Sgblack@eecs.umich.edu printReg(ss, _srcRegIdx[0]); 1002SN/A ss << ","; 1013453Sgblack@eecs.umich.edu } 1023453Sgblack@eecs.umich.edu 1033453Sgblack@eecs.umich.edu if( mnemonic == "lui") 1042SN/A ccprintf(ss, "%08p ", sextImm); 1053453Sgblack@eecs.umich.edu else 1063453Sgblack@eecs.umich.edu ss << (int) sextImm; 1072SN/A 1083453Sgblack@eecs.umich.edu return ss.str(); 1093453Sgblack@eecs.umich.edu } 1103453Sgblack@eecs.umich.edu 1113453Sgblack@eecs.umich.edu}}; 1123453Sgblack@eecs.umich.edu 1133453Sgblack@eecs.umich.edu//Used by decoder.isa 1143453Sgblack@eecs.umich.edudef format IntOp(code, *opt_flags) {{ 1153453Sgblack@eecs.umich.edu orig_code = code 1163453Sgblack@eecs.umich.edu cblk = CodeBlock(code) 1173453Sgblack@eecs.umich.edu 1183453Sgblack@eecs.umich.edu # Figure out if we are creating a IntImmOp or a IntOp 1193453Sgblack@eecs.umich.edu # by looking at the instruction name 1203453Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags) 1213453Sgblack@eecs.umich.edu strlen = len(name) 1223453Sgblack@eecs.umich.edu if name[strlen-1] == 'i' or name[strlen-2:] == 'iu': 1232SN/A iop = InstObjParams(name, Name, 'IntImmOp', cblk, opt_flags) 1243453Sgblack@eecs.umich.edu 1253453Sgblack@eecs.umich.edu header_output = BasicDeclare.subst(iop) 1263453Sgblack@eecs.umich.edu decoder_output = BasicConstructor.subst(iop) 1273453Sgblack@eecs.umich.edu decode_block = OperateNopCheckDecode.subst(iop) 1283453Sgblack@eecs.umich.edu exec_output = BasicExecute.subst(iop) 1293453Sgblack@eecs.umich.edu}}; 1303453Sgblack@eecs.umich.edu 1312SN/A 1322SN/A 133