int.isa revision 2495
111507SCurtis.Dunham@arm.com// -*- mode:c++ -*- 211507SCurtis.Dunham@arm.com 311860Sandreas.hansson@arm.com//////////////////////////////////////////////////////////////////// 411860Sandreas.hansson@arm.com// 511860Sandreas.hansson@arm.com// Integer operate instructions 611507SCurtis.Dunham@arm.com// 711860Sandreas.hansson@arm.com 811860Sandreas.hansson@arm.com//Outputs to decoder.hh 911860Sandreas.hansson@arm.comoutput header {{ 1011860Sandreas.hansson@arm.com#include <iostream> 1111860Sandreas.hansson@arm.com using namespace std; 1211507SCurtis.Dunham@arm.com /** 1311507SCurtis.Dunham@arm.com * Base class for integer operations. 1411507SCurtis.Dunham@arm.com */ 1511507SCurtis.Dunham@arm.com class IntOp : public MipsStaticInst 1611860Sandreas.hansson@arm.com { 1711570SCurtis.Dunham@arm.com protected: 1811507SCurtis.Dunham@arm.com 1911570SCurtis.Dunham@arm.com /// Constructor 2011570SCurtis.Dunham@arm.com IntOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 2111570SCurtis.Dunham@arm.com MipsStaticInst(mnem, _machInst, __opClass) 2211570SCurtis.Dunham@arm.com { 2311507SCurtis.Dunham@arm.com } 2411570SCurtis.Dunham@arm.com 2511860Sandreas.hansson@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 2611860Sandreas.hansson@arm.com }; 2711860Sandreas.hansson@arm.com 2811860Sandreas.hansson@arm.com class IntImmOp : public MipsStaticInst 2911860Sandreas.hansson@arm.com { 3011860Sandreas.hansson@arm.com protected: 3111860Sandreas.hansson@arm.com 3211860Sandreas.hansson@arm.com int16_t imm; 3311570SCurtis.Dunham@arm.com int32_t sextImm; 3411507SCurtis.Dunham@arm.com uint32_t zextImm; 3511570SCurtis.Dunham@arm.com 3611507SCurtis.Dunham@arm.com /// Constructor 3711570SCurtis.Dunham@arm.com IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 3811507SCurtis.Dunham@arm.com MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM), 3911507SCurtis.Dunham@arm.com sextImm(INTIMM),zextImm(0x0000FFFF & INTIMM) 4011570SCurtis.Dunham@arm.com { 4111507SCurtis.Dunham@arm.com //If Bit 15 is 1 then Sign Extend 4211507SCurtis.Dunham@arm.com int32_t temp = sextImm & 0x00008000; 4311507SCurtis.Dunham@arm.com if (temp > 0 && mnemonic != "lui") { 4411507SCurtis.Dunham@arm.com sextImm |= 0xFFFF0000; 4511507SCurtis.Dunham@arm.com } 4611507SCurtis.Dunham@arm.com } 4711507SCurtis.Dunham@arm.com 4811507SCurtis.Dunham@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 4911507SCurtis.Dunham@arm.com 5011507SCurtis.Dunham@arm.com 5111507SCurtis.Dunham@arm.com }; 5211507SCurtis.Dunham@arm.com 5311507SCurtis.Dunham@arm.com}}; 5411507SCurtis.Dunham@arm.com 5511570SCurtis.Dunham@arm.com//Outputs to decoder.cc 5611507SCurtis.Dunham@arm.comoutput decoder {{ 5711507SCurtis.Dunham@arm.com std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 5811507SCurtis.Dunham@arm.com { 5911507SCurtis.Dunham@arm.com std::stringstream ss; 6011570SCurtis.Dunham@arm.com 6111507SCurtis.Dunham@arm.com ccprintf(ss, "%-10s ", mnemonic); 6211507SCurtis.Dunham@arm.com 6311507SCurtis.Dunham@arm.com // just print the first dest... if there's a second one, 6411507SCurtis.Dunham@arm.com // it's generally implicit 6511507SCurtis.Dunham@arm.com if (_numDestRegs > 0) { 6611507SCurtis.Dunham@arm.com printReg(ss, _destRegIdx[0]); 6711507SCurtis.Dunham@arm.com } 6811507SCurtis.Dunham@arm.com 6911507SCurtis.Dunham@arm.com ss << ","; 7011507SCurtis.Dunham@arm.com 7111507SCurtis.Dunham@arm.com // just print the first two source regs... if there's 7211507SCurtis.Dunham@arm.com // a third one, it's a read-modify-write dest (Rc), 7311507SCurtis.Dunham@arm.com // e.g. for CMOVxx 7411507SCurtis.Dunham@arm.com if (_numSrcRegs > 0) { 7511507SCurtis.Dunham@arm.com printReg(ss, _srcRegIdx[0]); 7611507SCurtis.Dunham@arm.com } 7711507SCurtis.Dunham@arm.com 7811507SCurtis.Dunham@arm.com if (_numSrcRegs > 1) { 7911860Sandreas.hansson@arm.com ss << ","; 8011507SCurtis.Dunham@arm.com printReg(ss, _srcRegIdx[1]); 8111507SCurtis.Dunham@arm.com } 8211507SCurtis.Dunham@arm.com 8311507SCurtis.Dunham@arm.com return ss.str(); 8411507SCurtis.Dunham@arm.com } 8511507SCurtis.Dunham@arm.com 8611570SCurtis.Dunham@arm.com std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 8711507SCurtis.Dunham@arm.com { 8811507SCurtis.Dunham@arm.com std::stringstream ss; 8911507SCurtis.Dunham@arm.com 9011507SCurtis.Dunham@arm.com ccprintf(ss, "%-10s ", mnemonic); 9111507SCurtis.Dunham@arm.com 9211507SCurtis.Dunham@arm.com if (_numDestRegs > 0) { 9311507SCurtis.Dunham@arm.com printReg(ss, _destRegIdx[0]); 9411860Sandreas.hansson@arm.com } 9511860Sandreas.hansson@arm.com 9611680SCurtis.Dunham@arm.com ss << ","; 9711507SCurtis.Dunham@arm.com 9811507SCurtis.Dunham@arm.com if (_numSrcRegs > 0) { 9911507SCurtis.Dunham@arm.com printReg(ss, _srcRegIdx[0]); 10011507SCurtis.Dunham@arm.com ss << ","; 10111507SCurtis.Dunham@arm.com } 10211507SCurtis.Dunham@arm.com 10311507SCurtis.Dunham@arm.com if( mnemonic == "lui") 10411507SCurtis.Dunham@arm.com ccprintf(ss, "%08p ", sextImm); 10511507SCurtis.Dunham@arm.com else 10611507SCurtis.Dunham@arm.com ss << (int) sextImm; 10711507SCurtis.Dunham@arm.com 10811507SCurtis.Dunham@arm.com return ss.str(); 10911507SCurtis.Dunham@arm.com } 11011507SCurtis.Dunham@arm.com 11111507SCurtis.Dunham@arm.com}}; 11211507SCurtis.Dunham@arm.com 11311507SCurtis.Dunham@arm.com//Used by decoder.isa 11411507SCurtis.Dunham@arm.comdef format IntOp(code, *opt_flags) {{ 11511507SCurtis.Dunham@arm.com orig_code = code 11611507SCurtis.Dunham@arm.com cblk = CodeBlock(code) 11711507SCurtis.Dunham@arm.com 11811507SCurtis.Dunham@arm.com # Figure out if we are creating a IntImmOp or a IntOp 11911507SCurtis.Dunham@arm.com # by looking at the instruction name 12011507SCurtis.Dunham@arm.com iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags) 12111507SCurtis.Dunham@arm.com strlen = len(name) 12211507SCurtis.Dunham@arm.com if name[strlen-1] == 'i' or name[strlen-2:] == 'iu': 12311507SCurtis.Dunham@arm.com iop = InstObjParams(name, Name, 'IntImmOp', cblk, opt_flags) 12411507SCurtis.Dunham@arm.com 12511507SCurtis.Dunham@arm.com header_output = BasicDeclare.subst(iop) 12611507SCurtis.Dunham@arm.com decoder_output = BasicConstructor.subst(iop) 12711507SCurtis.Dunham@arm.com decode_block = OperateNopCheckDecode.subst(iop) 12811507SCurtis.Dunham@arm.com exec_output = BasicExecute.subst(iop) 12911507SCurtis.Dunham@arm.com}}; 13011507SCurtis.Dunham@arm.com 13111507SCurtis.Dunham@arm.com 13211507SCurtis.Dunham@arm.com 13311507SCurtis.Dunham@arm.com