fp.isa revision 5268:5bfc53fe60e7
1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Korey Sewell 30 31//////////////////////////////////////////////////////////////////// 32// 33// Floating Point operate instructions 34// 35 36output header {{ 37 /** 38 * Base class for FP operations. 39 */ 40 class FPOp : public MipsStaticInst 41 { 42 protected: 43 44 /// Constructor 45 FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) 46 { 47 } 48 49 //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 50 51 //needs function to check for fpEnable or not 52 }; 53 54 class FPCompareOp : public FPOp 55 { 56 protected: 57 FPCompareOp(const char *mnem, MachInst _machInst, OpClass __opClass) : FPOp(mnem, _machInst, __opClass) 58 { 59 } 60 61 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 62 63 }; 64}}; 65 66output decoder {{ 67 std::string FPCompareOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 68 { 69 std::stringstream ss; 70 71 ccprintf(ss, "%-10s ", mnemonic); 72 73 ccprintf(ss,"%d",CC); 74 75 if(_numSrcRegs > 0) { 76 ss << ", "; 77 printReg(ss, _srcRegIdx[0]); 78 } 79 80 if(_numSrcRegs > 1) { 81 ss << ", "; 82 printReg(ss, _srcRegIdx[1]); 83 } 84 85 return ss.str(); 86 } 87}}; 88 89output exec {{ 90 inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) 91 { 92 //@TODO: Implement correct CP0 checks to see if the CP1 93 // unit is enable or not 94 if (!isCoprocessorEnabled(xc, 1)) 95 return new CoprocessorUnusableFault(1); 96 97 return NoFault; 98 } 99 100 //If any operand is Nan return the appropriate QNaN 101 template <class T> 102 bool 103 fpNanOperands(FPOp *inst, %(CPU_exec_context)s *xc, const T &src_type, 104 Trace::InstRecord *traceData) 105 { 106 uint64_t mips_nan = 0; 107 T src_op = 0; 108 int size = sizeof(src_op) * 8; 109 110 for (int i = 0; i < inst->numSrcRegs(); i++) { 111 uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0, size); 112 113 if (isNan(&src_bits, size) ) { 114 if (isSnan(&src_bits, size)) { 115 switch (size) 116 { 117 case 32: mips_nan = MIPS32_QNAN; break; 118 case 64: mips_nan = MIPS64_QNAN; break; 119 default: panic("Unsupported Floating Point Size (%d)", size); 120 } 121 } else { 122 mips_nan = src_bits; 123 } 124 125 xc->setFloatRegOperandBits(inst, 0, mips_nan, size); 126 if (traceData) { traceData->setData(mips_nan); } 127 return true; 128 } 129 } 130 return false; 131 } 132 133 template <class T> 134 bool 135 fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *cpu, const T dest_val, 136 Trace::InstRecord *traceData) 137 { 138 uint64_t mips_nan = 0; 139 T src_op = dest_val; 140 int size = sizeof(src_op) * 8; 141 142 if (isNan(&src_op, size)) { 143 switch (size) 144 { 145 case 32: mips_nan = MIPS32_QNAN; break; 146 case 64: mips_nan = MIPS64_QNAN; break; 147 default: panic("Unsupported Floating Point Size (%d)", size); 148 } 149 150 //Set value to QNAN 151 cpu->setFloatRegOperandBits(inst, 0, mips_nan, size); 152 153 //Read FCSR from FloatRegFile 154 uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR); 155 156 uint32_t new_fcsr = genInvalidVector(fcsr_bits); 157 158 //Write FCSR from FloatRegFile 159 cpu->tcBase()->setFloatRegBits(FCSR, new_fcsr); 160 161 if (traceData) { traceData->setData(mips_nan); } 162 return true; 163 } 164 165 return false; 166 } 167 168 void 169 fpResetCauseBits(%(CPU_exec_context)s *cpu) 170 { 171 //Read FCSR from FloatRegFile 172 uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FCSR); 173 174 // TODO: Use utility function here 175 fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0); 176 177 //Write FCSR from FloatRegFile 178 cpu->tcBase()->setFloatRegBits(FCSR, fcsr); 179 } 180}}; 181 182def template FloatingPointExecute {{ 183 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 184 { 185 Fault fault = NoFault; 186 187 %(fp_enable_check)s; 188 189 190 //When is the right time to reset cause bits? 191 //start of every instruction or every cycle? 192#if FULL_SYSTEM 193 fpResetCauseBits(xc); 194#endif 195 %(op_decl)s; 196 %(op_rd)s; 197 198 //Check if any FP operand is a NaN value 199 if (!fpNanOperands((FPOp*)this, xc, Fd, traceData)) { 200 %(code)s; 201 202 //Change this code for Full-System/Sycall Emulation 203 //separation 204 //---- 205 //Should Full System-Mode throw a fault here? 206 //---- 207 //Check for IEEE 754 FP Exceptions 208 //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData); 209 if ( 210#if FULL_SYSTEM 211 !fpInvalidOp((FPOp*)this, xc, Fd, traceData) && 212#endif 213 fault == NoFault) 214 { 215 %(op_wb)s; 216 } 217 } 218 219 return fault; 220 } 221}}; 222 223// Primary format for float point operate instructions: 224def format FloatOp(code, *flags) {{ 225 iop = InstObjParams(name, Name, 'FPOp', code, flags) 226 header_output = BasicDeclare.subst(iop) 227 decoder_output = BasicConstructor.subst(iop) 228 decode_block = BasicDecode.subst(iop) 229 exec_output = FloatingPointExecute.subst(iop) 230}}; 231 232def format FloatCompareOp(cond_code, *flags) {{ 233 import sys 234 235 code = 'bool cond;\n' 236 if '.sf' in cond_code or 'SinglePrecision' in flags: 237 if 'QnanException' in flags: 238 code += 'if (isQnan(&Fs.sf, 32) || isQnan(&Ft.sf, 32)) {\n' 239 code += '\tFCSR = genInvalidVector(FCSR);\n' 240 code += '\treturn NoFault;' 241 code += '}\n else ' 242 code += 'if (isNan(&Fs.sf, 32) || isNan(&Ft.sf, 32)) {\n' 243 elif '.df' in cond_code or 'DoublePrecision' in flags: 244 if 'QnanException' in flags: 245 code += 'if (isQnan(&Fs.df, 64) || isQnan(&Ft.df, 64)) {\n' 246 code += '\tFCSR = genInvalidVector(FCSR);\n' 247 code += '\treturn NoFault;' 248 code += '}\n else ' 249 code += 'if (isNan(&Fs.df, 64) || isNan(&Ft.df, 64)) {\n' 250 else: 251 sys.exit('Decoder Failed: Can\'t Determine Operand Type\n') 252 253 if 'UnorderedTrue' in flags: 254 code += 'cond = 1;\n' 255 elif 'UnorderedFalse' in flags: 256 code += 'cond = 0;\n' 257 else: 258 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n') 259 260 code += '} else {\n' 261 code += cond_code + '}' 262 code += 'FCSR = genCCVector(FCSR, CC, cond);\n' 263 264 iop = InstObjParams(name, Name, 'FPCompareOp', code) 265 header_output = BasicDeclare.subst(iop) 266 decoder_output = BasicConstructor.subst(iop) 267 decode_block = BasicDecode.subst(iop) 268 exec_output = BasicExecute.subst(iop) 269}}; 270 271def format FloatConvertOp(code, *flags) {{ 272 import sys 273 274 #Determine Source Type 275 convert = 'fpConvert(' 276 if '.sf' in code: 277 code = 'float ' + code + '\n' 278 convert += 'SINGLE_TO_' 279 elif '.df' in code: 280 code = 'double ' + code + '\n' 281 convert += 'DOUBLE_TO_' 282 elif '.uw' in code: 283 code = 'uint32_t ' + code + '\n' 284 convert += 'WORD_TO_' 285 elif '.ud' in code: 286 code = 'uint64_t ' + code + '\n' 287 convert += 'LONG_TO_' 288 else: 289 sys.exit("Error Determining Source Type for Conversion") 290 291 #Determine Destination Type 292 if 'ToSingle' in flags: 293 code += 'Fd.uw = ' + convert + 'SINGLE, ' 294 elif 'ToDouble' in flags: 295 code += 'Fd.ud = ' + convert + 'DOUBLE, ' 296 elif 'ToWord' in flags: 297 code += 'Fd.uw = ' + convert + 'WORD, ' 298 elif 'ToLong' in flags: 299 code += 'Fd.ud = ' + convert + 'LONG, ' 300 else: 301 sys.exit("Error Determining Destination Type for Conversion") 302 303 #Figure out how to round value 304 if 'Ceil' in flags: 305 code += 'ceil(val)); ' 306 elif 'Floor' in flags: 307 code += 'floor(val)); ' 308 elif 'Round' in flags: 309 code += 'roundFP(val, 0)); ' 310 elif 'Trunc' in flags: 311 code += 'truncFP(val));' 312 else: 313 code += 'val); ' 314 315 iop = InstObjParams(name, Name, 'FPOp', code) 316 header_output = BasicDeclare.subst(iop) 317 decoder_output = BasicConstructor.subst(iop) 318 decode_block = BasicDecode.subst(iop) 319 exec_output = BasicExecute.subst(iop) 320}}; 321 322def format FloatAccOp(code, *flags) {{ 323 iop = InstObjParams(name, Name, 'FPOp', code, flags) 324 header_output = BasicDeclare.subst(iop) 325 decoder_output = BasicConstructor.subst(iop) 326 decode_block = BasicDecode.subst(iop) 327 exec_output = BasicExecute.subst(iop) 328}}; 329 330// Primary format for float64 operate instructions: 331def format Float64Op(code, *flags) {{ 332 iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags) 333 header_output = BasicDeclare.subst(iop) 334 decoder_output = BasicConstructor.subst(iop) 335 decode_block = BasicDecode.subst(iop) 336 exec_output = BasicExecute.subst(iop) 337}}; 338 339def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{ 340 import sys 341 342 code = 'bool cond1, cond2;\n' 343 code += 'bool code_block1, code_block2;\n' 344 code += 'code_block1 = code_block2 = true;\n' 345 346 if 'QnanException' in flags: 347 code += 'if (isQnan(&Fs1.sf, 32) || isQnan(&Ft1.sf, 32)) {\n' 348 code += '\tFCSR = genInvalidVector(FCSR);\n' 349 code += 'code_block1 = false;' 350 code += '}\n' 351 code += 'if (isQnan(&Fs2.sf, 32) || isQnan(&Ft2.sf, 32)) {\n' 352 code += '\tFCSR = genInvalidVector(FCSR);\n' 353 code += 'code_block2 = false;' 354 code += '}\n' 355 356 code += 'if (code_block1) {' 357 code += '\tif (isNan(&Fs1.sf, 32) || isNan(&Ft1.sf, 32)) {\n' 358 if 'UnorderedTrue' in flags: 359 code += 'cond1 = 1;\n' 360 elif 'UnorderedFalse' in flags: 361 code += 'cond1 = 0;\n' 362 else: 363 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n') 364 code += '} else {\n' 365 code += cond_code1 366 code += 'FCSR = genCCVector(FCSR, CC, cond1);}\n}\n' 367 368 code += 'if (code_block2) {' 369 code += '\tif (isNan(&Fs2.sf, 32) || isNan(&Ft2.sf, 32)) {\n' 370 if 'UnorderedTrue' in flags: 371 code += 'cond2 = 1;\n' 372 elif 'UnorderedFalse' in flags: 373 code += 'cond2 = 0;\n' 374 else: 375 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n') 376 code += '} else {\n' 377 code += cond_code2 378 code += 'FCSR = genCCVector(FCSR, CC, cond2);}\n}' 379 380 iop = InstObjParams(name, Name, 'FPCompareOp', code) 381 header_output = BasicDeclare.subst(iop) 382 decoder_output = BasicConstructor.subst(iop) 383 decode_block = BasicDecode.subst(iop) 384 exec_output = BasicExecute.subst(iop) 385}}; 386 387