fp.isa revision 4675:598d4c33c38d
1// -*- mode:c++ -*- 2 3// Copyright (c) 2006 The Regents of The University of Michigan 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Korey Sewell 30 31//////////////////////////////////////////////////////////////////// 32// 33// Floating Point operate instructions 34// 35 36output header {{ 37 /** 38 * Base class for FP operations. 39 */ 40 class FPOp : public MipsStaticInst 41 { 42 protected: 43 44 /// Constructor 45 FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) 46 { 47 } 48 49 //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 50 51 //needs function to check for fpEnable or not 52 }; 53 54 class FPCompareOp : public FPOp 55 { 56 protected: 57 FPCompareOp(const char *mnem, MachInst _machInst, OpClass __opClass) : FPOp(mnem, _machInst, __opClass) 58 { 59 } 60 61 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 62 63 }; 64}}; 65 66output decoder {{ 67 std::string FPCompareOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 68 { 69 std::stringstream ss; 70 71 ccprintf(ss, "%-10s ", mnemonic); 72 73 ccprintf(ss,"%d",CC); 74 75 if(_numSrcRegs > 0) { 76 ss << ", "; 77 printReg(ss, _srcRegIdx[0]); 78 } 79 80 if(_numSrcRegs > 1) { 81 ss << ", "; 82 printReg(ss, _srcRegIdx[1]); 83 } 84 85 return ss.str(); 86 } 87}}; 88 89output exec {{ 90 inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) 91 { 92 //@TODO: Implement correct CP0 checks to see if the CP1 93 // unit is enable or not 94 return NoFault; 95 } 96 97 //If any operand is Nan return the appropriate QNaN 98 template <class T> 99 bool 100 fpNanOperands(FPOp *inst, %(CPU_exec_context)s *xc, const T &src_type, 101 Trace::InstRecord *traceData) 102 { 103 uint64_t mips_nan = 0; 104 T src_op = 0; 105 int size = sizeof(src_op) * 8; 106 107 for (int i = 0; i < inst->numSrcRegs(); i++) { 108 uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0, size); 109 110 if (isNan(&src_bits, size) ) { 111 if (isSnan(&src_bits, size)) { 112 switch (size) 113 { 114 case 32: mips_nan = MIPS32_QNAN; break; 115 case 64: mips_nan = MIPS64_QNAN; break; 116 default: panic("Unsupported Floating Point Size (%d)", size); 117 } 118 } else { 119 mips_nan = src_bits; 120 } 121 122 xc->setFloatRegOperandBits(inst, 0, mips_nan, size); 123 if (traceData) { traceData->setData(mips_nan); } 124 return true; 125 } 126 } 127 return false; 128 } 129 130 template <class T> 131 bool 132 fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *cpu, const T dest_val, 133 Trace::InstRecord *traceData) 134 { 135 uint64_t mips_nan = 0; 136 T src_op = dest_val; 137 int size = sizeof(src_op) * 8; 138 139 if (isNan(&src_op, size)) { 140 switch (size) 141 { 142 case 32: mips_nan = MIPS32_QNAN; break; 143 case 64: mips_nan = MIPS64_QNAN; break; 144 default: panic("Unsupported Floating Point Size (%d)", size); 145 } 146 147 //Set value to QNAN 148 cpu->setFloatRegOperandBits(inst, 0, mips_nan, size); 149 150 //Read FCSR from FloatRegFile 151 uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR); 152 153 uint32_t new_fcsr = genInvalidVector(fcsr_bits); 154 155 //Write FCSR from FloatRegFile 156 cpu->tcBase()->setFloatRegBits(FCSR, new_fcsr); 157 158 if (traceData) { traceData->setData(mips_nan); } 159 return true; 160 } 161 162 return false; 163 } 164 165 void 166 fpResetCauseBits(%(CPU_exec_context)s *cpu) 167 { 168 //Read FCSR from FloatRegFile 169 uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FCSR); 170 171 // TODO: Use utility function here 172 fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0); 173 174 //Write FCSR from FloatRegFile 175 cpu->tcBase()->setFloatRegBits(FCSR, fcsr); 176 } 177}}; 178 179def template FloatingPointExecute {{ 180 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 181 { 182 Fault fault = NoFault; 183 184 %(fp_enable_check)s; 185 186 //When is the right time to reset cause bits? 187 //start of every instruction or every cycle? 188#if FULL_SYSTEM 189 fpResetCauseBits(xc); 190#endif 191 %(op_decl)s; 192 %(op_rd)s; 193 194 //Check if any FP operand is a NaN value 195 if (!fpNanOperands((FPOp*)this, xc, Fd, traceData)) { 196 %(code)s; 197 198 //Change this code for Full-System/Sycall Emulation 199 //separation 200 //---- 201 //Should Full System-Mode throw a fault here? 202 //---- 203 //Check for IEEE 754 FP Exceptions 204 //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData); 205 if ( 206#if FULL_SYSTEM 207 !fpInvalidOp((FPOp*)this, xc, Fd, traceData) && 208#endif 209 fault == NoFault) 210 { 211 %(op_wb)s; 212 } 213 } 214 215 return fault; 216 } 217}}; 218 219// Primary format for float point operate instructions: 220def format FloatOp(code, *flags) {{ 221 iop = InstObjParams(name, Name, 'FPOp', code, flags) 222 header_output = BasicDeclare.subst(iop) 223 decoder_output = BasicConstructor.subst(iop) 224 decode_block = BasicDecode.subst(iop) 225 exec_output = FloatingPointExecute.subst(iop) 226}}; 227 228def format FloatCompareOp(cond_code, *flags) {{ 229 import sys 230 231 code = 'bool cond;\n' 232 if '.sf' in cond_code or 'SinglePrecision' in flags: 233 if 'QnanException' in flags: 234 code += 'if (isQnan(&Fs.sf, 32) || isQnan(&Ft.sf, 32)) {\n' 235 code += '\tFCSR = genInvalidVector(FCSR);\n' 236 code += '\treturn NoFault;' 237 code += '}\n else ' 238 code += 'if (isNan(&Fs.sf, 32) || isNan(&Ft.sf, 32)) {\n' 239 elif '.df' in cond_code or 'DoublePrecision' in flags: 240 if 'QnanException' in flags: 241 code += 'if (isQnan(&Fs.df, 64) || isQnan(&Ft.df, 64)) {\n' 242 code += '\tFCSR = genInvalidVector(FCSR);\n' 243 code += '\treturn NoFault;' 244 code += '}\n else ' 245 code += 'if (isNan(&Fs.df, 64) || isNan(&Ft.df, 64)) {\n' 246 else: 247 sys.exit('Decoder Failed: Can\'t Determine Operand Type\n') 248 249 if 'UnorderedTrue' in flags: 250 code += 'cond = 1;\n' 251 elif 'UnorderedFalse' in flags: 252 code += 'cond = 0;\n' 253 else: 254 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n') 255 256 code += '} else {\n' 257 code += cond_code + '}' 258 code += 'FCSR = genCCVector(FCSR, CC, cond);\n' 259 260 iop = InstObjParams(name, Name, 'FPCompareOp', code) 261 header_output = BasicDeclare.subst(iop) 262 decoder_output = BasicConstructor.subst(iop) 263 decode_block = BasicDecode.subst(iop) 264 exec_output = BasicExecute.subst(iop) 265}}; 266 267def format FloatConvertOp(code, *flags) {{ 268 import sys 269 270 #Determine Source Type 271 convert = 'fpConvert(' 272 if '.sf' in code: 273 code = 'float ' + code + '\n' 274 convert += 'SINGLE_TO_' 275 elif '.df' in code: 276 code = 'double ' + code + '\n' 277 convert += 'DOUBLE_TO_' 278 elif '.uw' in code: 279 code = 'uint32_t ' + code + '\n' 280 convert += 'WORD_TO_' 281 elif '.ud' in code: 282 code = 'uint64_t ' + code + '\n' 283 convert += 'LONG_TO_' 284 else: 285 sys.exit("Error Determining Source Type for Conversion") 286 287 #Determine Destination Type 288 if 'ToSingle' in flags: 289 code += 'Fd.uw = ' + convert + 'SINGLE, ' 290 elif 'ToDouble' in flags: 291 code += 'Fd.ud = ' + convert + 'DOUBLE, ' 292 elif 'ToWord' in flags: 293 code += 'Fd.uw = ' + convert + 'WORD, ' 294 elif 'ToLong' in flags: 295 code += 'Fd.ud = ' + convert + 'LONG, ' 296 else: 297 sys.exit("Error Determining Destination Type for Conversion") 298 299 #Figure out how to round value 300 if 'Ceil' in flags: 301 code += 'ceil(val)); ' 302 elif 'Floor' in flags: 303 code += 'floor(val)); ' 304 elif 'Round' in flags: 305 code += 'roundFP(val, 0)); ' 306 elif 'Trunc' in flags: 307 code += 'truncFP(val));' 308 else: 309 code += 'val); ' 310 311 iop = InstObjParams(name, Name, 'FPOp', code) 312 header_output = BasicDeclare.subst(iop) 313 decoder_output = BasicConstructor.subst(iop) 314 decode_block = BasicDecode.subst(iop) 315 exec_output = BasicExecute.subst(iop) 316}}; 317 318def format FloatAccOp(code, *flags) {{ 319 iop = InstObjParams(name, Name, 'FPOp', code, flags) 320 header_output = BasicDeclare.subst(iop) 321 decoder_output = BasicConstructor.subst(iop) 322 decode_block = BasicDecode.subst(iop) 323 exec_output = BasicExecute.subst(iop) 324}}; 325 326// Primary format for float64 operate instructions: 327def format Float64Op(code, *flags) {{ 328 iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags) 329 header_output = BasicDeclare.subst(iop) 330 decoder_output = BasicConstructor.subst(iop) 331 decode_block = BasicDecode.subst(iop) 332 exec_output = BasicExecute.subst(iop) 333}}; 334 335def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{ 336 import sys 337 338 code = 'bool cond1, cond2;\n' 339 code += 'bool code_block1, code_block2;\n' 340 code += 'code_block1 = code_block2 = true;\n' 341 342 if 'QnanException' in flags: 343 code += 'if (isQnan(&Fs1.sf, 32) || isQnan(&Ft1.sf, 32)) {\n' 344 code += '\tFCSR = genInvalidVector(FCSR);\n' 345 code += 'code_block1 = false;' 346 code += '}\n' 347 code += 'if (isQnan(&Fs2.sf, 32) || isQnan(&Ft2.sf, 32)) {\n' 348 code += '\tFCSR = genInvalidVector(FCSR);\n' 349 code += 'code_block2 = false;' 350 code += '}\n' 351 352 code += 'if (code_block1) {' 353 code += '\tif (isNan(&Fs1.sf, 32) || isNan(&Ft1.sf, 32)) {\n' 354 if 'UnorderedTrue' in flags: 355 code += 'cond1 = 1;\n' 356 elif 'UnorderedFalse' in flags: 357 code += 'cond1 = 0;\n' 358 else: 359 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n') 360 code += '} else {\n' 361 code += cond_code1 362 code += 'FCSR = genCCVector(FCSR, CC, cond1);}\n}\n' 363 364 code += 'if (code_block2) {' 365 code += '\tif (isNan(&Fs2.sf, 32) || isNan(&Ft2.sf, 32)) {\n' 366 if 'UnorderedTrue' in flags: 367 code += 'cond2 = 1;\n' 368 elif 'UnorderedFalse' in flags: 369 code += 'cond2 = 0;\n' 370 else: 371 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n') 372 code += '} else {\n' 373 code += cond_code2 374 code += 'FCSR = genCCVector(FCSR, CC, cond2);}\n}' 375 376 iop = InstObjParams(name, Name, 'FPCompareOp', code) 377 header_output = BasicDeclare.subst(iop) 378 decoder_output = BasicConstructor.subst(iop) 379 decode_block = BasicDecode.subst(iop) 380 exec_output = BasicExecute.subst(iop) 381}}; 382 383