fp.isa revision 4661:44458219add1 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Korey Sewell
30
31////////////////////////////////////////////////////////////////////
32//
33// Floating Point operate instructions
34//
35
36output header {{
37        /**
38         * Base class for FP operations.
39         */
40        class FPOp : public MipsStaticInst
41        {
42                protected:
43
44                /// Constructor
45                FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
46                {
47                }
48
49            //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
50
51                //needs function to check for fpEnable or not
52        };
53
54        class FPCompareOp : public FPOp
55        {
56          protected:
57            FPCompareOp(const char *mnem, MachInst _machInst, OpClass __opClass) : FPOp(mnem, _machInst, __opClass)
58                {
59                }
60
61            std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
62
63        };
64}};
65
66output decoder {{
67        std::string FPCompareOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
68        {
69            std::stringstream ss;
70
71            ccprintf(ss, "%-10s ", mnemonic);
72
73            ccprintf(ss,"%d",CC);
74
75            if(_numSrcRegs > 0) {
76                ss << ", ";
77                printReg(ss, _srcRegIdx[0]);
78            }
79
80            if(_numSrcRegs > 1) {
81                ss << ", ";
82                printReg(ss, _srcRegIdx[1]);
83            }
84
85            return ss.str();
86        }
87}};
88
89output exec {{
90        inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
91        {
92            //@TODO: Implement correct CP0 checks to see if the CP1
93            // unit is enable or not
94            return NoFault;
95        }
96
97        //If any operand is Nan return the appropriate QNaN
98        template <class T>
99        bool
100        fpNanOperands(FPOp *inst, %(CPU_exec_context)s *xc, const T &src_type,
101                      Trace::InstRecord *traceData)
102        {
103            uint64_t mips_nan = 0;
104            T src_op = 0;
105            int size = sizeof(src_op) * 8;
106
107            for (int i = 0; i < inst->numSrcRegs(); i++) {
108                uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0, size);
109
110                if (isNan(&src_bits, size) ) {
111                    if (isSnan(&src_bits, size)) {
112                        switch (size)
113                        {
114                          case 32: mips_nan = MIPS32_QNAN; break;
115                          case 64: mips_nan = MIPS64_QNAN; break;
116                          default: panic("Unsupported Floating Point Size (%d)", size);
117                        }
118                    } else {
119                        mips_nan = src_bits;
120                    }
121
122                    xc->setFloatRegOperandBits(inst, 0, mips_nan, size);
123                    if (traceData) { traceData->setData(mips_nan); }
124                    return true;
125                }
126            }
127            return false;
128        }
129
130        template <class T>
131        bool
132        fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *cpu, const T dest_val,
133                    Trace::InstRecord *traceData)
134        {
135            uint64_t mips_nan = 0;
136            T src_op = dest_val;
137            int size = sizeof(src_op) * 8;
138
139            if (isNan(&src_op, size)) {
140                switch (size)
141                {
142                  case 32: mips_nan = MIPS32_QNAN; break;
143                  case 64: mips_nan = MIPS64_QNAN; break;
144                  default: panic("Unsupported Floating Point Size (%d)", size);
145                }
146
147                //Set value to QNAN
148                cpu->setFloatRegOperandBits(inst, 0, mips_nan, size);
149
150                //Read FCSR from FloatRegFile
151                uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR);
152
153                //Write FCSR from FloatRegFile
154                cpu->tcBase()->setFloatRegOperandBits(FCSR, genInvalidVector(fcsr_bits));
155
156                if (traceData) { traceData->setData(mips_nan); }
157                return true;
158            }
159
160            return false;
161        }
162
163        void
164        fpResetCauseBits(%(CPU_exec_context)s *cpu)
165        {
166            //Read FCSR from FloatRegFile
167            uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FCSR);
168
169            // TODO: Use utility function here
170            fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
171
172            //Write FCSR from FloatRegFile
173            cpu->tcBase()->setFloatRegBits(FCSR, fcsr);
174        }
175}};
176
177def template FloatingPointExecute {{
178        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
179        {
180                Fault fault = NoFault;
181
182                %(fp_enable_check)s;
183
184                //When is the right time to reset cause bits?
185                //start of every instruction or every cycle?
186#if FULL_SYSTEM
187                fpResetCauseBits(xc);
188#endif
189                %(op_decl)s;
190                %(op_rd)s;
191
192                //Check if any FP operand is a NaN value
193                if (!fpNanOperands((FPOp*)this, xc, Fd, traceData)) {
194                    %(code)s;
195
196                    //Change this code for Full-System/Sycall Emulation
197                    //separation
198                    //----
199                    //Should Full System-Mode throw a fault here?
200                    //----
201                    //Check for IEEE 754 FP Exceptions
202                    //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
203                    if (
204#if FULL_SYSTEM
205                        !fpInvalidOp((FPOp*)this, xc, Fd, traceData) &&
206#endif
207                        fault == NoFault)
208                    {
209                        %(op_wb)s;
210                    }
211                }
212
213                return fault;
214        }
215}};
216
217// Primary format for float point operate instructions:
218def format FloatOp(code, *flags) {{
219        iop = InstObjParams(name, Name, 'FPOp', code, flags)
220        header_output = BasicDeclare.subst(iop)
221        decoder_output = BasicConstructor.subst(iop)
222        decode_block = BasicDecode.subst(iop)
223        exec_output = FloatingPointExecute.subst(iop)
224}};
225
226def format FloatCompareOp(cond_code, *flags) {{
227    import sys
228
229    code = 'bool cond;\n'
230    if '.sf' in cond_code or 'SinglePrecision' in flags:
231        if 'QnanException' in flags:
232            code += 'if (isQnan(&Fs.sf, 32) || isQnan(&Ft.sf, 32)) {\n'
233            code += '\tFCSR = genInvalidVector(FCSR);\n'
234            code += '\treturn NoFault;'
235            code += '}\n else '
236        code += 'if (isNan(&Fs.sf, 32) || isNan(&Ft.sf, 32)) {\n'
237    elif '.df' in cond_code or 'DoublePrecision' in flags:
238        if 'QnanException' in flags:
239            code += 'if (isQnan(&Fs.df, 64) || isQnan(&Ft.df, 64)) {\n'
240            code += '\tFCSR = genInvalidVector(FCSR);\n'
241            code += '\treturn NoFault;'
242            code += '}\n else '
243        code += 'if (isNan(&Fs.df, 64) || isNan(&Ft.df, 64)) {\n'
244    else:
245       sys.exit('Decoder Failed: Can\'t Determine Operand Type\n')
246
247    if 'UnorderedTrue' in flags:
248       code += 'cond = 1;\n'
249    elif 'UnorderedFalse' in flags:
250       code += 'cond = 0;\n'
251    else:
252       sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
253
254    code += '} else {\n'
255    code +=  cond_code + '}'
256    code += 'FCSR = genCCVector(FCSR, CC, cond);\n'
257
258    iop = InstObjParams(name, Name, 'FPCompareOp', code)
259    header_output = BasicDeclare.subst(iop)
260    decoder_output = BasicConstructor.subst(iop)
261    decode_block = BasicDecode.subst(iop)
262    exec_output = BasicExecute.subst(iop)
263}};
264
265def format FloatConvertOp(code, *flags) {{
266    import sys
267
268    #Determine Source Type
269    convert = 'fpConvert('
270    if '.sf' in code:
271        code = 'float ' + code + '\n'
272        convert += 'SINGLE_TO_'
273    elif '.df' in code:
274        code = 'double ' + code + '\n'
275        convert += 'DOUBLE_TO_'
276    elif '.uw' in code:
277        code = 'uint32_t ' + code + '\n'
278        convert += 'WORD_TO_'
279    elif '.ud' in code:
280        code = 'uint64_t ' + code + '\n'
281        convert += 'LONG_TO_'
282    else:
283        sys.exit("Error Determining Source Type for Conversion")
284
285    #Determine Destination Type
286    if 'ToSingle' in flags:
287        code += 'Fd.uw = ' + convert + 'SINGLE, '
288    elif 'ToDouble' in flags:
289        code += 'Fd.ud = ' + convert + 'DOUBLE, '
290    elif 'ToWord' in flags:
291        code += 'Fd.uw = ' + convert + 'WORD, '
292    elif 'ToLong' in flags:
293        code += 'Fd.ud = ' + convert + 'LONG, '
294    else:
295        sys.exit("Error Determining Destination Type for Conversion")
296
297    #Figure out how to round value
298    if 'Ceil' in flags:
299        code += 'ceil(val)); '
300    elif 'Floor' in flags:
301        code += 'floor(val)); '
302    elif 'Round' in flags:
303        code += 'roundFP(val, 0)); '
304    elif 'Trunc' in flags:
305        code += 'truncFP(val));'
306    else:
307        code += 'val); '
308
309    iop = InstObjParams(name, Name, 'FPOp', code)
310    header_output = BasicDeclare.subst(iop)
311    decoder_output = BasicConstructor.subst(iop)
312    decode_block = BasicDecode.subst(iop)
313    exec_output = BasicExecute.subst(iop)
314}};
315
316def format FloatAccOp(code, *flags) {{
317        iop = InstObjParams(name, Name, 'FPOp', code, flags)
318        header_output = BasicDeclare.subst(iop)
319        decoder_output = BasicConstructor.subst(iop)
320        decode_block = BasicDecode.subst(iop)
321        exec_output = BasicExecute.subst(iop)
322}};
323
324// Primary format for float64 operate instructions:
325def format Float64Op(code, *flags) {{
326        iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags)
327        header_output = BasicDeclare.subst(iop)
328        decoder_output = BasicConstructor.subst(iop)
329        decode_block = BasicDecode.subst(iop)
330        exec_output = BasicExecute.subst(iop)
331}};
332
333def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{
334    import sys
335
336    code = 'bool cond1, cond2;\n'
337    code += 'bool code_block1, code_block2;\n'
338    code += 'code_block1 = code_block2 = true;\n'
339
340    if 'QnanException' in flags:
341        code += 'if (isQnan(&Fs1.sf, 32) || isQnan(&Ft1.sf, 32)) {\n'
342        code += '\tFCSR = genInvalidVector(FCSR);\n'
343        code += 'code_block1 = false;'
344        code += '}\n'
345        code += 'if (isQnan(&Fs2.sf, 32) || isQnan(&Ft2.sf, 32)) {\n'
346        code += '\tFCSR = genInvalidVector(FCSR);\n'
347        code += 'code_block2 = false;'
348        code += '}\n'
349
350    code += 'if (code_block1) {'
351    code += '\tif (isNan(&Fs1.sf, 32) || isNan(&Ft1.sf, 32)) {\n'
352    if 'UnorderedTrue' in flags:
353       code += 'cond1 = 1;\n'
354    elif 'UnorderedFalse' in flags:
355       code += 'cond1 = 0;\n'
356    else:
357       sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
358    code += '} else {\n'
359    code +=  cond_code1
360    code += 'FCSR = genCCVector(FCSR, CC, cond1);}\n}\n'
361
362    code += 'if (code_block2) {'
363    code += '\tif (isNan(&Fs2.sf, 32) || isNan(&Ft2.sf, 32)) {\n'
364    if 'UnorderedTrue' in flags:
365       code += 'cond2 = 1;\n'
366    elif 'UnorderedFalse' in flags:
367       code += 'cond2 = 0;\n'
368    else:
369       sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
370    code += '} else {\n'
371    code +=  cond_code2
372    code += 'FCSR = genCCVector(FCSR, CC, cond2);}\n}'
373
374    iop = InstObjParams(name, Name, 'FPCompareOp', code)
375    header_output = BasicDeclare.subst(iop)
376    decoder_output = BasicConstructor.subst(iop)
377    decode_block = BasicDecode.subst(iop)
378    exec_output = BasicExecute.subst(iop)
379}};
380
381