fp.isa revision 3951:727778d649ae 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Korey Sewell
30
31////////////////////////////////////////////////////////////////////
32//
33// Floating Point operate instructions
34//
35
36output header {{
37        /**
38         * Base class for FP operations.
39         */
40        class FPOp : public MipsStaticInst
41        {
42                protected:
43
44                /// Constructor
45                FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
46                {
47                }
48
49            //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
50
51                //needs function to check for fpEnable or not
52        };
53
54        class FPCompareOp : public FPOp
55        {
56          protected:
57            FPCompareOp(const char *mnem, MachInst _machInst, OpClass __opClass) : FPOp(mnem, _machInst, __opClass)
58                {
59                }
60
61            std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
62
63        };
64}};
65
66output decoder {{
67        std::string FPCompareOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
68        {
69            std::stringstream ss;
70
71            ccprintf(ss, "%-10s ", mnemonic);
72
73            ccprintf(ss,"%d",CC);
74
75            if(_numSrcRegs > 0) {
76                ss << ", ";
77                printReg(ss, _srcRegIdx[0]);
78            }
79
80            if(_numSrcRegs > 1) {
81                ss << ", ";
82                printReg(ss, _srcRegIdx[1]);
83            }
84
85            return ss.str();
86        }
87}};
88
89output exec {{
90
91        //If any operand is Nan return the appropriate QNaN
92        template <class T>
93        bool
94        fpNanOperands(FPOp *inst, %(CPU_exec_context)s *xc, const T &src_type,
95                      Trace::InstRecord *traceData)
96        {
97            uint64_t mips_nan = 0;
98            T src_op = 0;
99            int size = sizeof(src_op) * 8;
100
101            for (int i = 0; i < inst->numSrcRegs(); i++) {
102                uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0, size);
103
104                if (isNan(&src_bits, size) ) {
105                    if (isSnan(&src_bits, size)) {
106                        switch (size)
107                        {
108                          case 32: mips_nan = MIPS32_QNAN; break;
109                          case 64: mips_nan = MIPS64_QNAN; break;
110                          default: panic("Unsupported Floating Point Size (%d)", size);
111                        }
112                    } else {
113                        mips_nan = src_bits;
114                    }
115
116                    xc->setFloatRegOperandBits(inst, 0, mips_nan, size);
117                    if (traceData) { traceData->setData(mips_nan); }
118                    return true;
119                }
120            }
121            return false;
122        }
123
124        template <class T>
125        bool
126        fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *cpu, const T dest_val,
127                    Trace::InstRecord *traceData)
128        {
129            uint64_t mips_nan = 0;
130            T src_op = dest_val;
131            int size = sizeof(src_op) * 8;
132
133            if (isNan(&src_op, size)) {
134                switch (size)
135                {
136                  case 32: mips_nan = MIPS32_QNAN; break;
137                  case 64: mips_nan = MIPS64_QNAN; break;
138                  default: panic("Unsupported Floating Point Size (%d)", size);
139                }
140
141                //Set value to QNAN
142                cpu->setFloatRegOperandBits(inst, 0, mips_nan, size);
143
144                //Read FCSR from FloatRegFile
145                uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR);
146
147                //Write FCSR from FloatRegFile
148                cpu->tcBase()->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits));
149
150                if (traceData) { traceData->setData(mips_nan); }
151                return true;
152            }
153
154            return false;
155        }
156
157        void
158        fpResetCauseBits(%(CPU_exec_context)s *cpu)
159        {
160            //Read FCSR from FloatRegFile
161            uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FCSR);
162
163            fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
164
165            //Write FCSR from FloatRegFile
166            cpu->tcBase()->setFloatRegBits(FCSR, fcsr);
167        }
168}};
169
170def template FloatingPointExecute {{
171        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
172        {
173                Fault fault = NoFault;
174
175                %(fp_enable_check)s;
176
177                //When is the right time to reset cause bits?
178                //start of every instruction or every cycle?
179#if FULL_SYSTEM
180                fpResetCauseBits(xc);
181#endif
182                %(op_decl)s;
183                %(op_rd)s;
184
185                //Check if any FP operand is a NaN value
186                if (!fpNanOperands((FPOp*)this, xc, Fd, traceData)) {
187                    %(code)s;
188
189                    //Change this code for Full-System/Sycall Emulation
190                    //separation
191                    //----
192                    //Should Full System-Mode throw a fault here?
193                    //----
194                    //Check for IEEE 754 FP Exceptions
195                    //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
196                    if (
197#if FULL_SYSTEM
198                        !fpInvalidOp((FPOp*)this, xc, Fd, traceData) &&
199#endif
200                        fault == NoFault)
201                    {
202                        %(op_wb)s;
203                    }
204                }
205
206                return fault;
207        }
208}};
209
210// Primary format for float point operate instructions:
211def format FloatOp(code, *flags) {{
212        iop = InstObjParams(name, Name, 'FPOp', code, flags)
213        header_output = BasicDeclare.subst(iop)
214        decoder_output = BasicConstructor.subst(iop)
215        decode_block = BasicDecode.subst(iop)
216        exec_output = FloatingPointExecute.subst(iop)
217}};
218
219def format FloatCompareOp(cond_code, *flags) {{
220    import sys
221
222    code = 'bool cond;\n'
223    if '.sf' in cond_code or 'SinglePrecision' in flags:
224        if 'QnanException' in flags:
225            code += 'if (isQnan(&Fs.sf, 32) || isQnan(&Ft.sf, 32)) {\n'
226            code += '\tFCSR = genInvalidVector(FCSR);\n'
227            code += '\treturn NoFault;'
228            code += '}\n else '
229        code += 'if (isNan(&Fs.sf, 32) || isNan(&Ft.sf, 32)) {\n'
230    elif '.df' in cond_code or 'DoublePrecision' in flags:
231        if 'QnanException' in flags:
232            code += 'if (isQnan(&Fs.df, 64) || isQnan(&Ft.df, 64)) {\n'
233            code += '\tFCSR = genInvalidVector(FCSR);\n'
234            code += '\treturn NoFault;'
235            code += '}\n else '
236        code += 'if (isNan(&Fs.df, 64) || isNan(&Ft.df, 64)) {\n'
237    else:
238       sys.exit('Decoder Failed: Can\'t Determine Operand Type\n')
239
240    if 'UnorderedTrue' in flags:
241       code += 'cond = 1;\n'
242    elif 'UnorderedFalse' in flags:
243       code += 'cond = 0;\n'
244    else:
245       sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
246
247    code += '} else {\n'
248    code +=  cond_code + '}'
249    code += 'FCSR = genCCVector(FCSR, CC, cond);\n'
250
251    iop = InstObjParams(name, Name, 'FPCompareOp', code)
252    header_output = BasicDeclare.subst(iop)
253    decoder_output = BasicConstructor.subst(iop)
254    decode_block = BasicDecode.subst(iop)
255    exec_output = BasicExecute.subst(iop)
256}};
257
258def format FloatConvertOp(code, *flags) {{
259    import sys
260
261    #Determine Source Type
262    convert = 'fpConvert('
263    if '.sf' in code:
264        code = 'float ' + code + '\n'
265        convert += 'SINGLE_TO_'
266    elif '.df' in code:
267        code = 'double ' + code + '\n'
268        convert += 'DOUBLE_TO_'
269    elif '.uw' in code:
270        code = 'uint32_t ' + code + '\n'
271        convert += 'WORD_TO_'
272    elif '.ud' in code:
273        code = 'uint64_t ' + code + '\n'
274        convert += 'LONG_TO_'
275    else:
276        sys.exit("Error Determining Source Type for Conversion")
277
278    #Determine Destination Type
279    if 'ToSingle' in flags:
280        code += 'Fd.uw = ' + convert + 'SINGLE, '
281    elif 'ToDouble' in flags:
282        code += 'Fd.ud = ' + convert + 'DOUBLE, '
283    elif 'ToWord' in flags:
284        code += 'Fd.uw = ' + convert + 'WORD, '
285    elif 'ToLong' in flags:
286        code += 'Fd.ud = ' + convert + 'LONG, '
287    else:
288        sys.exit("Error Determining Destination Type for Conversion")
289
290    #Figure out how to round value
291    if 'Ceil' in flags:
292        code += 'ceil(val)); '
293    elif 'Floor' in flags:
294        code += 'floor(val)); '
295    elif 'Round' in flags:
296        code += 'roundFP(val, 0)); '
297    elif 'Trunc' in flags:
298        code += 'truncFP(val));'
299    else:
300        code += 'val); '
301
302    iop = InstObjParams(name, Name, 'FPOp', code)
303    header_output = BasicDeclare.subst(iop)
304    decoder_output = BasicConstructor.subst(iop)
305    decode_block = BasicDecode.subst(iop)
306    exec_output = BasicExecute.subst(iop)
307}};
308
309def format FloatAccOp(code, *flags) {{
310        iop = InstObjParams(name, Name, 'FPOp', code, flags)
311        header_output = BasicDeclare.subst(iop)
312        decoder_output = BasicConstructor.subst(iop)
313        decode_block = BasicDecode.subst(iop)
314        exec_output = BasicExecute.subst(iop)
315}};
316
317// Primary format for float64 operate instructions:
318def format Float64Op(code, *flags) {{
319        iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags)
320        header_output = BasicDeclare.subst(iop)
321        decoder_output = BasicConstructor.subst(iop)
322        decode_block = BasicDecode.subst(iop)
323        exec_output = BasicExecute.subst(iop)
324}};
325
326def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{
327    import sys
328
329    code = 'bool cond1, cond2;\n'
330    code += 'bool code_block1, code_block2;\n'
331    code += 'code_block1 = code_block2 = true;\n'
332
333    if 'QnanException' in flags:
334        code += 'if (isQnan(&Fs1.sf, 32) || isQnan(&Ft1.sf, 32)) {\n'
335        code += '\tFCSR = genInvalidVector(FCSR);\n'
336        code += 'code_block1 = false;'
337        code += '}\n'
338        code += 'if (isQnan(&Fs2.sf, 32) || isQnan(&Ft2.sf, 32)) {\n'
339        code += '\tFCSR = genInvalidVector(FCSR);\n'
340        code += 'code_block2 = false;'
341        code += '}\n'
342
343    code += 'if (code_block1) {'
344    code += '\tif (isNan(&Fs1.sf, 32) || isNan(&Ft1.sf, 32)) {\n'
345    if 'UnorderedTrue' in flags:
346       code += 'cond1 = 1;\n'
347    elif 'UnorderedFalse' in flags:
348       code += 'cond1 = 0;\n'
349    else:
350       sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
351    code += '} else {\n'
352    code +=  cond_code1
353    code += 'FCSR = genCCVector(FCSR, CC, cond1);}\n}\n'
354
355    code += 'if (code_block2) {'
356    code += '\tif (isNan(&Fs2.sf, 32) || isNan(&Ft2.sf, 32)) {\n'
357    if 'UnorderedTrue' in flags:
358       code += 'cond2 = 1;\n'
359    elif 'UnorderedFalse' in flags:
360       code += 'cond2 = 0;\n'
361    else:
362       sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
363    code += '} else {\n'
364    code +=  cond_code2
365    code += 'FCSR = genCCVector(FCSR, CC, cond2);}\n}'
366
367    iop = InstObjParams(name, Name, 'FPCompareOp', code)
368    header_output = BasicDeclare.subst(iop)
369    decoder_output = BasicConstructor.subst(iop)
370    decode_block = BasicDecode.subst(iop)
371    exec_output = BasicExecute.subst(iop)
372}};
373
374