fp.isa revision 2754:e3d023bc752c
1// -*- mode:c++ -*- 2 3// Copyright (c) 2006 The Regents of The University of Michigan 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Korey Sewell 30 31//////////////////////////////////////////////////////////////////// 32// 33// Floating Point operate instructions 34// 35 36output header {{ 37 /** 38 * Base class for FP operations. 39 */ 40 class FPOp : public MipsStaticInst 41 { 42 protected: 43 44 /// Constructor 45 FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) 46 { 47 } 48 49 //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 50 51 //needs function to check for fpEnable or not 52 }; 53 54 class FPCompareOp : public FPOp 55 { 56 protected: 57 FPCompareOp(const char *mnem, MachInst _machInst, OpClass __opClass) : FPOp(mnem, _machInst, __opClass) 58 { 59 } 60 61 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 62 63 }; 64}}; 65 66output decoder {{ 67 std::string FPCompareOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 68 { 69 std::stringstream ss; 70 71 ccprintf(ss, "%-10s ", mnemonic); 72 73 ccprintf(ss,"%d",CC); 74 75 if(_numSrcRegs > 0) { 76 ss << ", "; 77 printReg(ss, _srcRegIdx[0]); 78 } 79 80 if(_numSrcRegs > 1) { 81 ss << ", "; 82 printReg(ss, _srcRegIdx[1]); 83 } 84 85 return ss.str(); 86 } 87}}; 88 89output exec {{ 90 91 //If any operand is Nan return the appropriate QNaN 92 template <class T> 93 bool 94 fpNanOperands(FPOp *inst, %(CPU_exec_context)s *xc, const T &src_type, 95 Trace::InstRecord *traceData) 96 { 97 uint64_t mips_nan = 0; 98 T src_op = 0; 99 int size = sizeof(src_op) * 8; 100 101 for (int i = 0; i < inst->numSrcRegs(); i++) { 102 uint64_t src_bits = xc->readFloatRegBits(inst, 0, size); 103 104 if (isNan(&src_bits, size) ) { 105 if (isSnan(&src_bits, size)) { 106 switch (size) 107 { 108 case 32: mips_nan = MIPS32_QNAN; break; 109 case 64: mips_nan = MIPS64_QNAN; break; 110 default: panic("Unsupported Floating Point Size (%d)", size); 111 } 112 } else { 113 mips_nan = src_bits; 114 } 115 116 xc->setFloatRegBits(inst, 0, mips_nan, size); 117 if (traceData) { traceData->setData(mips_nan); } 118 return true; 119 } 120 } 121 return false; 122 } 123 124 template <class T> 125 bool 126 fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *cpu, const T dest_val, 127 Trace::InstRecord *traceData) 128 { 129 uint64_t mips_nan = 0; 130 T src_op = dest_val; 131 int size = sizeof(src_op) * 8; 132 133 if (isNan(&src_op, size)) { 134 switch (size) 135 { 136 case 32: mips_nan = MIPS32_QNAN; break; 137 case 64: mips_nan = MIPS64_QNAN; break; 138 default: panic("Unsupported Floating Point Size (%d)", size); 139 } 140 141 //Set value to QNAN 142 cpu->setFloatRegBits(inst, 0, mips_nan, size); 143 144 //Read FCSR from FloatRegFile 145 uint32_t fcsr_bits = cpu->tc->readFloatRegBits(FCSR); 146 147 //Write FCSR from FloatRegFile 148 cpu->tc->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits)); 149 150 if (traceData) { traceData->setData(mips_nan); } 151 return true; 152 } 153 154 return false; 155 } 156 157 void 158 fpResetCauseBits(%(CPU_exec_context)s *cpu) 159 { 160 //Read FCSR from FloatRegFile 161 uint32_t fcsr = cpu->tc->readFloatRegBits(FCSR); 162 163 fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0); 164 165 //Write FCSR from FloatRegFile 166 cpu->tc->setFloatRegBits(FCSR, fcsr); 167 } 168}}; 169 170def template FloatingPointExecute {{ 171 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 172 { 173 Fault fault = NoFault; 174 175 %(fp_enable_check)s; 176 177 //When is the right time to reset cause bits? 178 //start of every instruction or every cycle? 179 fpResetCauseBits(xc); 180 181 %(op_decl)s; 182 %(op_rd)s; 183 184 //Check if any FP operand is a NaN value 185 if (!fpNanOperands((FPOp*)this, xc, Fd, traceData)) { 186 %(code)s; 187 188 //Change this code for Full-System/Sycall Emulation 189 //separation 190 //---- 191 //Should Full System-Mode throw a fault here? 192 //---- 193 //Check for IEEE 754 FP Exceptions 194 //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData); 195 if (!fpInvalidOp((FPOp*)this, xc, Fd, traceData) && 196 fault == NoFault) 197 { 198 %(op_wb)s; 199 } 200 } 201 202 return fault; 203 } 204}}; 205 206// Primary format for float point operate instructions: 207def format FloatOp(code, *flags) {{ 208 iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code), flags) 209 header_output = BasicDeclare.subst(iop) 210 decoder_output = BasicConstructor.subst(iop) 211 decode_block = BasicDecode.subst(iop) 212 exec_output = FloatingPointExecute.subst(iop) 213}}; 214 215def format FloatCompareOp(cond_code, *flags) {{ 216 import sys 217 218 code = 'bool cond;\n' 219 if '.sf' in cond_code or 'SinglePrecision' in flags: 220 if 'QnanException' in flags: 221 code += 'if (isQnan(&Fs.sf, 32) || isQnan(&Ft.sf, 32)) {\n' 222 code += '\tFCSR = genInvalidVector(FCSR);\n' 223 code += '\treturn NoFault;' 224 code += '}\n else ' 225 code += 'if (isNan(&Fs.sf, 32) || isNan(&Ft.sf, 32)) {\n' 226 elif '.df' in cond_code or 'DoublePrecision' in flags: 227 if 'QnanException' in flags: 228 code += 'if (isQnan(&Fs.df, 64) || isQnan(&Ft.df, 64)) {\n' 229 code += '\tFCSR = genInvalidVector(FCSR);\n' 230 code += '\treturn NoFault;' 231 code += '}\n else ' 232 code += 'if (isNan(&Fs.df, 64) || isNan(&Ft.df, 64)) {\n' 233 else: 234 sys.exit('Decoder Failed: Can\'t Determine Operand Type\n') 235 236 if 'UnorderedTrue' in flags: 237 code += 'cond = 1;\n' 238 elif 'UnorderedFalse' in flags: 239 code += 'cond = 0;\n' 240 else: 241 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n') 242 243 code += '} else {\n' 244 code += cond_code + '}' 245 code += 'FCSR = genCCVector(FCSR, CC, cond);\n' 246 247 iop = InstObjParams(name, Name, 'FPCompareOp', CodeBlock(code)) 248 header_output = BasicDeclare.subst(iop) 249 decoder_output = BasicConstructor.subst(iop) 250 decode_block = BasicDecode.subst(iop) 251 exec_output = BasicExecute.subst(iop) 252}}; 253 254def format FloatConvertOp(code, *flags) {{ 255 import sys 256 257 #Determine Source Type 258 convert = 'fpConvert(' 259 if '.sf' in code: 260 code = 'float ' + code + '\n' 261 convert += 'SINGLE_TO_' 262 elif '.df' in code: 263 code = 'double ' + code + '\n' 264 convert += 'DOUBLE_TO_' 265 elif '.uw' in code: 266 code = 'uint32_t ' + code + '\n' 267 convert += 'WORD_TO_' 268 elif '.ud' in code: 269 code = 'uint64_t ' + code + '\n' 270 convert += 'LONG_TO_' 271 else: 272 sys.exit("Error Determining Source Type for Conversion") 273 274 #Determine Destination Type 275 if 'ToSingle' in flags: 276 code += 'Fd.uw = ' + convert + 'SINGLE, ' 277 elif 'ToDouble' in flags: 278 code += 'Fd.ud = ' + convert + 'DOUBLE, ' 279 elif 'ToWord' in flags: 280 code += 'Fd.uw = ' + convert + 'WORD, ' 281 elif 'ToLong' in flags: 282 code += 'Fd.ud = ' + convert + 'LONG, ' 283 else: 284 sys.exit("Error Determining Destination Type for Conversion") 285 286 #Figure out how to round value 287 if 'Ceil' in flags: 288 code += 'ceil(val)); ' 289 elif 'Floor' in flags: 290 code += 'floor(val)); ' 291 elif 'Round' in flags: 292 code += 'roundFP(val, 0)); ' 293 elif 'Trunc' in flags: 294 code += 'truncFP(val));' 295 else: 296 code += 'val); ' 297 298 iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code)) 299 header_output = BasicDeclare.subst(iop) 300 decoder_output = BasicConstructor.subst(iop) 301 decode_block = BasicDecode.subst(iop) 302 exec_output = BasicExecute.subst(iop) 303}}; 304 305def format FloatAccOp(code, *flags) {{ 306 iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code), flags) 307 header_output = BasicDeclare.subst(iop) 308 decoder_output = BasicConstructor.subst(iop) 309 decode_block = BasicDecode.subst(iop) 310 exec_output = BasicExecute.subst(iop) 311}}; 312 313// Primary format for float64 operate instructions: 314def format Float64Op(code, *flags) {{ 315 iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags) 316 header_output = BasicDeclare.subst(iop) 317 decoder_output = BasicConstructor.subst(iop) 318 decode_block = BasicDecode.subst(iop) 319 exec_output = BasicExecute.subst(iop) 320}}; 321 322def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{ 323 import sys 324 325 code = 'bool cond1, cond2;\n' 326 code += 'bool code_block1, code_block2;\n' 327 code += 'code_block1 = code_block2 = true;\n' 328 329 if 'QnanException' in flags: 330 code += 'if (isQnan(&Fs1.sf, 32) || isQnan(&Ft1.sf, 32)) {\n' 331 code += '\tFCSR = genInvalidVector(FCSR);\n' 332 code += 'code_block1 = false;' 333 code += '}\n' 334 code += 'if (isQnan(&Fs2.sf, 32) || isQnan(&Ft2.sf, 32)) {\n' 335 code += '\tFCSR = genInvalidVector(FCSR);\n' 336 code += 'code_block2 = false;' 337 code += '}\n' 338 339 code += 'if (code_block1) {' 340 code += '\tif (isNan(&Fs1.sf, 32) || isNan(&Ft1.sf, 32)) {\n' 341 if 'UnorderedTrue' in flags: 342 code += 'cond1 = 1;\n' 343 elif 'UnorderedFalse' in flags: 344 code += 'cond1 = 0;\n' 345 else: 346 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n') 347 code += '} else {\n' 348 code += cond_code1 349 code += 'FCSR = genCCVector(FCSR, CC, cond1);}\n}\n' 350 351 code += 'if (code_block2) {' 352 code += '\tif (isNan(&Fs2.sf, 32) || isNan(&Ft2.sf, 32)) {\n' 353 if 'UnorderedTrue' in flags: 354 code += 'cond2 = 1;\n' 355 elif 'UnorderedFalse' in flags: 356 code += 'cond2 = 0;\n' 357 else: 358 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n') 359 code += '} else {\n' 360 code += cond_code2 361 code += 'FCSR = genCCVector(FCSR, CC, cond2);}\n}' 362 363 iop = InstObjParams(name, Name, 'FPCompareOp', CodeBlock(code)) 364 header_output = BasicDeclare.subst(iop) 365 decoder_output = BasicConstructor.subst(iop) 366 decode_block = BasicDecode.subst(iop) 367 exec_output = BasicExecute.subst(iop) 368}}; 369 370