fp.isa revision 5222
12135SN/A// -*- mode:c++ -*- 22135SN/A 35222Sksewell@umich.edu// Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved 45222Sksewell@umich.edu 55222Sksewell@umich.edu// This software is part of the M5 simulator. 65222Sksewell@umich.edu 75222Sksewell@umich.edu// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING 85222Sksewell@umich.edu// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING 95222Sksewell@umich.edu// TO THESE TERMS AND CONDITIONS. 105222Sksewell@umich.edu 115222Sksewell@umich.edu// Permission is granted to use, copy, create derivative works and 125222Sksewell@umich.edu// distribute this software and such derivative works for any purpose, 135222Sksewell@umich.edu// so long as (1) the copyright notice above, this grant of permission, 145222Sksewell@umich.edu// and the disclaimer below appear in all copies and derivative works 155222Sksewell@umich.edu// made, (2) the copyright notice above is augmented as appropriate to 165222Sksewell@umich.edu// reflect the addition of any new copyrightable work in a derivative 175222Sksewell@umich.edu// work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3) 185222Sksewell@umich.edu// the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any 195222Sksewell@umich.edu// advertising or publicity pertaining to the use or distribution of 205222Sksewell@umich.edu// this software without specific, written prior authorization. 215222Sksewell@umich.edu 225222Sksewell@umich.edu// THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B MIPS MAKES NO WARRANTIES AND 235222Sksewell@umich.edu// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR 245222Sksewell@umich.edu// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 255222Sksewell@umich.edu// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND 265222Sksewell@umich.edu// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE. 275222Sksewell@umich.edu// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, 285222Sksewell@umich.edu// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF 295222Sksewell@umich.edu// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT, 305222Sksewell@umich.edu// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY 315222Sksewell@umich.edu// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR 325222Sksewell@umich.edu// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE 335222Sksewell@umich.edu// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE. 345222Sksewell@umich.edu 355222Sksewell@umich.edu//Authors: Korey L. Sewell 362706Sksewell@umich.edu 372038SN/A//////////////////////////////////////////////////////////////////// 382038SN/A// 392038SN/A// Floating Point operate instructions 402038SN/A// 412038SN/A 422038SN/Aoutput header {{ 432038SN/A /** 442135SN/A * Base class for FP operations. 452038SN/A */ 462038SN/A class FPOp : public MipsStaticInst 472038SN/A { 482038SN/A protected: 492038SN/A 502038SN/A /// Constructor 512038SN/A FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) 522038SN/A { 532038SN/A } 542038SN/A 552686Sksewell@umich.edu //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 562686Sksewell@umich.edu 572686Sksewell@umich.edu //needs function to check for fpEnable or not 582686Sksewell@umich.edu }; 592686Sksewell@umich.edu 602686Sksewell@umich.edu class FPCompareOp : public FPOp 612686Sksewell@umich.edu { 622686Sksewell@umich.edu protected: 632686Sksewell@umich.edu FPCompareOp(const char *mnem, MachInst _machInst, OpClass __opClass) : FPOp(mnem, _machInst, __opClass) 642686Sksewell@umich.edu { 652686Sksewell@umich.edu } 662686Sksewell@umich.edu 672686Sksewell@umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 682686Sksewell@umich.edu 692038SN/A }; 702038SN/A}}; 712038SN/A 722038SN/Aoutput decoder {{ 732686Sksewell@umich.edu std::string FPCompareOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 742038SN/A { 752686Sksewell@umich.edu std::stringstream ss; 762686Sksewell@umich.edu 772686Sksewell@umich.edu ccprintf(ss, "%-10s ", mnemonic); 782686Sksewell@umich.edu 792686Sksewell@umich.edu ccprintf(ss,"%d",CC); 802686Sksewell@umich.edu 812686Sksewell@umich.edu if(_numSrcRegs > 0) { 822686Sksewell@umich.edu ss << ", "; 832686Sksewell@umich.edu printReg(ss, _srcRegIdx[0]); 842686Sksewell@umich.edu } 852686Sksewell@umich.edu 862686Sksewell@umich.edu if(_numSrcRegs > 1) { 872686Sksewell@umich.edu ss << ", "; 882686Sksewell@umich.edu printReg(ss, _srcRegIdx[1]); 892686Sksewell@umich.edu } 902686Sksewell@umich.edu 912686Sksewell@umich.edu return ss.str(); 922038SN/A } 932038SN/A}}; 942038SN/A 952686Sksewell@umich.eduoutput exec {{ 964661Sksewell@umich.edu inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) 974661Sksewell@umich.edu { 984661Sksewell@umich.edu //@TODO: Implement correct CP0 checks to see if the CP1 994661Sksewell@umich.edu // unit is enable or not 1005222Sksewell@umich.edu if (!isCoprocessorEnabled(xc, 1)) 1015222Sksewell@umich.edu return new CoprocessorUnusableFault(1); 1025222Sksewell@umich.edu 1035222Sksewell@umich.edu return NoFault; 1044661Sksewell@umich.edu } 1052038SN/A 1062686Sksewell@umich.edu //If any operand is Nan return the appropriate QNaN 1072686Sksewell@umich.edu template <class T> 1082686Sksewell@umich.edu bool 1092686Sksewell@umich.edu fpNanOperands(FPOp *inst, %(CPU_exec_context)s *xc, const T &src_type, 1102686Sksewell@umich.edu Trace::InstRecord *traceData) 1112686Sksewell@umich.edu { 1122686Sksewell@umich.edu uint64_t mips_nan = 0; 1132686Sksewell@umich.edu T src_op = 0; 1142686Sksewell@umich.edu int size = sizeof(src_op) * 8; 1152686Sksewell@umich.edu 1162686Sksewell@umich.edu for (int i = 0; i < inst->numSrcRegs(); i++) { 1173735Sstever@eecs.umich.edu uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0, size); 1182686Sksewell@umich.edu 1192686Sksewell@umich.edu if (isNan(&src_bits, size) ) { 1202686Sksewell@umich.edu if (isSnan(&src_bits, size)) { 1212686Sksewell@umich.edu switch (size) 1222686Sksewell@umich.edu { 1232686Sksewell@umich.edu case 32: mips_nan = MIPS32_QNAN; break; 1242686Sksewell@umich.edu case 64: mips_nan = MIPS64_QNAN; break; 1252686Sksewell@umich.edu default: panic("Unsupported Floating Point Size (%d)", size); 1262686Sksewell@umich.edu } 1272686Sksewell@umich.edu } else { 1282686Sksewell@umich.edu mips_nan = src_bits; 1292686Sksewell@umich.edu } 1302686Sksewell@umich.edu 1313735Sstever@eecs.umich.edu xc->setFloatRegOperandBits(inst, 0, mips_nan, size); 1322686Sksewell@umich.edu if (traceData) { traceData->setData(mips_nan); } 1332686Sksewell@umich.edu return true; 1342686Sksewell@umich.edu } 1352686Sksewell@umich.edu } 1362686Sksewell@umich.edu return false; 1372686Sksewell@umich.edu } 1382686Sksewell@umich.edu 1392686Sksewell@umich.edu template <class T> 1402686Sksewell@umich.edu bool 1412687Sksewell@umich.edu fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *cpu, const T dest_val, 1422686Sksewell@umich.edu Trace::InstRecord *traceData) 1432686Sksewell@umich.edu { 1442686Sksewell@umich.edu uint64_t mips_nan = 0; 1452686Sksewell@umich.edu T src_op = dest_val; 1462686Sksewell@umich.edu int size = sizeof(src_op) * 8; 1472686Sksewell@umich.edu 1482686Sksewell@umich.edu if (isNan(&src_op, size)) { 1492686Sksewell@umich.edu switch (size) 1502686Sksewell@umich.edu { 1512686Sksewell@umich.edu case 32: mips_nan = MIPS32_QNAN; break; 1522686Sksewell@umich.edu case 64: mips_nan = MIPS64_QNAN; break; 1532686Sksewell@umich.edu default: panic("Unsupported Floating Point Size (%d)", size); 1542686Sksewell@umich.edu } 1552686Sksewell@umich.edu 1562686Sksewell@umich.edu //Set value to QNAN 1573735Sstever@eecs.umich.edu cpu->setFloatRegOperandBits(inst, 0, mips_nan, size); 1582686Sksewell@umich.edu 1592686Sksewell@umich.edu //Read FCSR from FloatRegFile 1602847Sksewell@umich.edu uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR); 1612686Sksewell@umich.edu 1624675Sksewell@umich.edu uint32_t new_fcsr = genInvalidVector(fcsr_bits); 1634675Sksewell@umich.edu 1642686Sksewell@umich.edu //Write FCSR from FloatRegFile 1654675Sksewell@umich.edu cpu->tcBase()->setFloatRegBits(FCSR, new_fcsr); 1662686Sksewell@umich.edu 1672686Sksewell@umich.edu if (traceData) { traceData->setData(mips_nan); } 1682686Sksewell@umich.edu return true; 1692686Sksewell@umich.edu } 1702686Sksewell@umich.edu 1712686Sksewell@umich.edu return false; 1722686Sksewell@umich.edu } 1732686Sksewell@umich.edu 1742686Sksewell@umich.edu void 1752687Sksewell@umich.edu fpResetCauseBits(%(CPU_exec_context)s *cpu) 1762686Sksewell@umich.edu { 1772686Sksewell@umich.edu //Read FCSR from FloatRegFile 1782847Sksewell@umich.edu uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FCSR); 1792686Sksewell@umich.edu 1804661Sksewell@umich.edu // TODO: Use utility function here 1812686Sksewell@umich.edu fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0); 1822686Sksewell@umich.edu 1832686Sksewell@umich.edu //Write FCSR from FloatRegFile 1842847Sksewell@umich.edu cpu->tcBase()->setFloatRegBits(FCSR, fcsr); 1852686Sksewell@umich.edu } 1862686Sksewell@umich.edu}}; 1872686Sksewell@umich.edu 1882686Sksewell@umich.edudef template FloatingPointExecute {{ 1892686Sksewell@umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1902686Sksewell@umich.edu { 1912686Sksewell@umich.edu Fault fault = NoFault; 1922686Sksewell@umich.edu 1932686Sksewell@umich.edu %(fp_enable_check)s; 1942686Sksewell@umich.edu 1955222Sksewell@umich.edu 1962686Sksewell@umich.edu //When is the right time to reset cause bits? 1972686Sksewell@umich.edu //start of every instruction or every cycle? 1982847Sksewell@umich.edu#if FULL_SYSTEM 1992686Sksewell@umich.edu fpResetCauseBits(xc); 2002847Sksewell@umich.edu#endif 2012686Sksewell@umich.edu %(op_decl)s; 2022686Sksewell@umich.edu %(op_rd)s; 2032686Sksewell@umich.edu 2042686Sksewell@umich.edu //Check if any FP operand is a NaN value 2052686Sksewell@umich.edu if (!fpNanOperands((FPOp*)this, xc, Fd, traceData)) { 2062686Sksewell@umich.edu %(code)s; 2072686Sksewell@umich.edu 2082686Sksewell@umich.edu //Change this code for Full-System/Sycall Emulation 2092686Sksewell@umich.edu //separation 2102686Sksewell@umich.edu //---- 2112686Sksewell@umich.edu //Should Full System-Mode throw a fault here? 2122686Sksewell@umich.edu //---- 2132686Sksewell@umich.edu //Check for IEEE 754 FP Exceptions 2142686Sksewell@umich.edu //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData); 2152847Sksewell@umich.edu if ( 2162847Sksewell@umich.edu#if FULL_SYSTEM 2172847Sksewell@umich.edu !fpInvalidOp((FPOp*)this, xc, Fd, traceData) && 2182847Sksewell@umich.edu#endif 2192686Sksewell@umich.edu fault == NoFault) 2202686Sksewell@umich.edu { 2212686Sksewell@umich.edu %(op_wb)s; 2222686Sksewell@umich.edu } 2232686Sksewell@umich.edu } 2242686Sksewell@umich.edu 2252686Sksewell@umich.edu return fault; 2262686Sksewell@umich.edu } 2272686Sksewell@umich.edu}}; 2282686Sksewell@umich.edu 2292686Sksewell@umich.edu// Primary format for float point operate instructions: 2302135SN/Adef format FloatOp(code, *flags) {{ 2313951Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'FPOp', code, flags) 2322038SN/A header_output = BasicDeclare.subst(iop) 2332038SN/A decoder_output = BasicConstructor.subst(iop) 2342135SN/A decode_block = BasicDecode.subst(iop) 2352686Sksewell@umich.edu exec_output = FloatingPointExecute.subst(iop) 2362084SN/A}}; 2372084SN/A 2382686Sksewell@umich.edudef format FloatCompareOp(cond_code, *flags) {{ 2392686Sksewell@umich.edu import sys 2402607SN/A 2412686Sksewell@umich.edu code = 'bool cond;\n' 2422686Sksewell@umich.edu if '.sf' in cond_code or 'SinglePrecision' in flags: 2432686Sksewell@umich.edu if 'QnanException' in flags: 2442686Sksewell@umich.edu code += 'if (isQnan(&Fs.sf, 32) || isQnan(&Ft.sf, 32)) {\n' 2452686Sksewell@umich.edu code += '\tFCSR = genInvalidVector(FCSR);\n' 2462686Sksewell@umich.edu code += '\treturn NoFault;' 2472686Sksewell@umich.edu code += '}\n else ' 2482686Sksewell@umich.edu code += 'if (isNan(&Fs.sf, 32) || isNan(&Ft.sf, 32)) {\n' 2492686Sksewell@umich.edu elif '.df' in cond_code or 'DoublePrecision' in flags: 2502686Sksewell@umich.edu if 'QnanException' in flags: 2512686Sksewell@umich.edu code += 'if (isQnan(&Fs.df, 64) || isQnan(&Ft.df, 64)) {\n' 2522686Sksewell@umich.edu code += '\tFCSR = genInvalidVector(FCSR);\n' 2532686Sksewell@umich.edu code += '\treturn NoFault;' 2542686Sksewell@umich.edu code += '}\n else ' 2552686Sksewell@umich.edu code += 'if (isNan(&Fs.df, 64) || isNan(&Ft.df, 64)) {\n' 2562686Sksewell@umich.edu else: 2572686Sksewell@umich.edu sys.exit('Decoder Failed: Can\'t Determine Operand Type\n') 2582686Sksewell@umich.edu 2592686Sksewell@umich.edu if 'UnorderedTrue' in flags: 2602686Sksewell@umich.edu code += 'cond = 1;\n' 2612686Sksewell@umich.edu elif 'UnorderedFalse' in flags: 2622686Sksewell@umich.edu code += 'cond = 0;\n' 2632686Sksewell@umich.edu else: 2642686Sksewell@umich.edu sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n') 2652686Sksewell@umich.edu 2662686Sksewell@umich.edu code += '} else {\n' 2672686Sksewell@umich.edu code += cond_code + '}' 2682686Sksewell@umich.edu code += 'FCSR = genCCVector(FCSR, CC, cond);\n' 2692686Sksewell@umich.edu 2703951Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'FPCompareOp', code) 2712686Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 2722686Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 2732686Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 2742686Sksewell@umich.edu exec_output = BasicExecute.subst(iop) 2752607SN/A}}; 2762607SN/A 2772607SN/Adef format FloatConvertOp(code, *flags) {{ 2782686Sksewell@umich.edu import sys 2792686Sksewell@umich.edu 2802686Sksewell@umich.edu #Determine Source Type 2812686Sksewell@umich.edu convert = 'fpConvert(' 2822686Sksewell@umich.edu if '.sf' in code: 2832686Sksewell@umich.edu code = 'float ' + code + '\n' 2842686Sksewell@umich.edu convert += 'SINGLE_TO_' 2852686Sksewell@umich.edu elif '.df' in code: 2862686Sksewell@umich.edu code = 'double ' + code + '\n' 2872686Sksewell@umich.edu convert += 'DOUBLE_TO_' 2882686Sksewell@umich.edu elif '.uw' in code: 2892686Sksewell@umich.edu code = 'uint32_t ' + code + '\n' 2902686Sksewell@umich.edu convert += 'WORD_TO_' 2912686Sksewell@umich.edu elif '.ud' in code: 2922686Sksewell@umich.edu code = 'uint64_t ' + code + '\n' 2932686Sksewell@umich.edu convert += 'LONG_TO_' 2942686Sksewell@umich.edu else: 2952686Sksewell@umich.edu sys.exit("Error Determining Source Type for Conversion") 2962686Sksewell@umich.edu 2972686Sksewell@umich.edu #Determine Destination Type 2982686Sksewell@umich.edu if 'ToSingle' in flags: 2992686Sksewell@umich.edu code += 'Fd.uw = ' + convert + 'SINGLE, ' 3002686Sksewell@umich.edu elif 'ToDouble' in flags: 3012686Sksewell@umich.edu code += 'Fd.ud = ' + convert + 'DOUBLE, ' 3022686Sksewell@umich.edu elif 'ToWord' in flags: 3032686Sksewell@umich.edu code += 'Fd.uw = ' + convert + 'WORD, ' 3042686Sksewell@umich.edu elif 'ToLong' in flags: 3052686Sksewell@umich.edu code += 'Fd.ud = ' + convert + 'LONG, ' 3062686Sksewell@umich.edu else: 3072686Sksewell@umich.edu sys.exit("Error Determining Destination Type for Conversion") 3082686Sksewell@umich.edu 3092686Sksewell@umich.edu #Figure out how to round value 3102686Sksewell@umich.edu if 'Ceil' in flags: 3112686Sksewell@umich.edu code += 'ceil(val)); ' 3122686Sksewell@umich.edu elif 'Floor' in flags: 3132686Sksewell@umich.edu code += 'floor(val)); ' 3142686Sksewell@umich.edu elif 'Round' in flags: 3152686Sksewell@umich.edu code += 'roundFP(val, 0)); ' 3162686Sksewell@umich.edu elif 'Trunc' in flags: 3172686Sksewell@umich.edu code += 'truncFP(val));' 3182686Sksewell@umich.edu else: 3192686Sksewell@umich.edu code += 'val); ' 3202686Sksewell@umich.edu 3213951Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'FPOp', code) 3222686Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 3232686Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 3242686Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 3252686Sksewell@umich.edu exec_output = BasicExecute.subst(iop) 3262686Sksewell@umich.edu}}; 3272686Sksewell@umich.edu 3282686Sksewell@umich.edudef format FloatAccOp(code, *flags) {{ 3293951Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'FPOp', code, flags) 3302607SN/A header_output = BasicDeclare.subst(iop) 3312607SN/A decoder_output = BasicConstructor.subst(iop) 3322607SN/A decode_block = BasicDecode.subst(iop) 3332607SN/A exec_output = BasicExecute.subst(iop) 3342607SN/A}}; 3352607SN/A 3362573SN/A// Primary format for float64 operate instructions: 3372135SN/Adef format Float64Op(code, *flags) {{ 3383951Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags) 3392084SN/A header_output = BasicDeclare.subst(iop) 3402084SN/A decoder_output = BasicConstructor.subst(iop) 3412135SN/A decode_block = BasicDecode.subst(iop) 3422135SN/A exec_output = BasicExecute.subst(iop) 3432038SN/A}}; 3442607SN/A 3452686Sksewell@umich.edudef format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{ 3462686Sksewell@umich.edu import sys 3472686Sksewell@umich.edu 3482686Sksewell@umich.edu code = 'bool cond1, cond2;\n' 3492686Sksewell@umich.edu code += 'bool code_block1, code_block2;\n' 3502686Sksewell@umich.edu code += 'code_block1 = code_block2 = true;\n' 3512686Sksewell@umich.edu 3522686Sksewell@umich.edu if 'QnanException' in flags: 3532686Sksewell@umich.edu code += 'if (isQnan(&Fs1.sf, 32) || isQnan(&Ft1.sf, 32)) {\n' 3542686Sksewell@umich.edu code += '\tFCSR = genInvalidVector(FCSR);\n' 3552686Sksewell@umich.edu code += 'code_block1 = false;' 3562686Sksewell@umich.edu code += '}\n' 3572686Sksewell@umich.edu code += 'if (isQnan(&Fs2.sf, 32) || isQnan(&Ft2.sf, 32)) {\n' 3582686Sksewell@umich.edu code += '\tFCSR = genInvalidVector(FCSR);\n' 3592686Sksewell@umich.edu code += 'code_block2 = false;' 3602686Sksewell@umich.edu code += '}\n' 3612686Sksewell@umich.edu 3622686Sksewell@umich.edu code += 'if (code_block1) {' 3632686Sksewell@umich.edu code += '\tif (isNan(&Fs1.sf, 32) || isNan(&Ft1.sf, 32)) {\n' 3642686Sksewell@umich.edu if 'UnorderedTrue' in flags: 3652686Sksewell@umich.edu code += 'cond1 = 1;\n' 3662686Sksewell@umich.edu elif 'UnorderedFalse' in flags: 3672686Sksewell@umich.edu code += 'cond1 = 0;\n' 3682686Sksewell@umich.edu else: 3692686Sksewell@umich.edu sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n') 3702686Sksewell@umich.edu code += '} else {\n' 3712686Sksewell@umich.edu code += cond_code1 3722686Sksewell@umich.edu code += 'FCSR = genCCVector(FCSR, CC, cond1);}\n}\n' 3732686Sksewell@umich.edu 3742686Sksewell@umich.edu code += 'if (code_block2) {' 3752686Sksewell@umich.edu code += '\tif (isNan(&Fs2.sf, 32) || isNan(&Ft2.sf, 32)) {\n' 3762686Sksewell@umich.edu if 'UnorderedTrue' in flags: 3772686Sksewell@umich.edu code += 'cond2 = 1;\n' 3782686Sksewell@umich.edu elif 'UnorderedFalse' in flags: 3792686Sksewell@umich.edu code += 'cond2 = 0;\n' 3802686Sksewell@umich.edu else: 3812686Sksewell@umich.edu sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n') 3822686Sksewell@umich.edu code += '} else {\n' 3832686Sksewell@umich.edu code += cond_code2 3842686Sksewell@umich.edu code += 'FCSR = genCCVector(FCSR, CC, cond2);}\n}' 3852686Sksewell@umich.edu 3863951Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'FPCompareOp', code) 3872686Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 3882686Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 3892686Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 3902686Sksewell@umich.edu exec_output = BasicExecute.subst(iop) 3912607SN/A}}; 3922608SN/A 393