fp.isa revision 2706
12135SN/A// -*- mode:c++ -*- 22135SN/A 32706Sksewell@umich.edu// Copyright (c) 2003-2006 The Regents of The University of Michigan 42706Sksewell@umich.edu// All rights reserved. 52706Sksewell@umich.edu// 62706Sksewell@umich.edu// Redistribution and use in source and binary forms, with or without 72706Sksewell@umich.edu// modification, are permitted provided that the following conditions are 82706Sksewell@umich.edu// met: redistributions of source code must retain the above copyright 92706Sksewell@umich.edu// notice, this list of conditions and the following disclaimer; 102706Sksewell@umich.edu// redistributions in binary form must reproduce the above copyright 112706Sksewell@umich.edu// notice, this list of conditions and the following disclaimer in the 122706Sksewell@umich.edu// documentation and/or other materials provided with the distribution; 132706Sksewell@umich.edu// neither the name of the copyright holders nor the names of its 142706Sksewell@umich.edu// contributors may be used to endorse or promote products derived from 152706Sksewell@umich.edu// this software without specific prior written permission. 162706Sksewell@umich.edu// 172706Sksewell@umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182706Sksewell@umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192706Sksewell@umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202706Sksewell@umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212706Sksewell@umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222706Sksewell@umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232706Sksewell@umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242706Sksewell@umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252706Sksewell@umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262706Sksewell@umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272706Sksewell@umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282706Sksewell@umich.edu// 292706Sksewell@umich.edu// Authors: Korey Sewell 302706Sksewell@umich.edu 312038SN/A//////////////////////////////////////////////////////////////////// 322038SN/A// 332038SN/A// Floating Point operate instructions 342038SN/A// 352038SN/A 362038SN/Aoutput header {{ 372038SN/A /** 382135SN/A * Base class for FP operations. 392038SN/A */ 402038SN/A class FPOp : public MipsStaticInst 412038SN/A { 422038SN/A protected: 432038SN/A 442038SN/A /// Constructor 452038SN/A FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) 462038SN/A { 472038SN/A } 482038SN/A 492686Sksewell@umich.edu //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 502686Sksewell@umich.edu 512686Sksewell@umich.edu //needs function to check for fpEnable or not 522686Sksewell@umich.edu }; 532686Sksewell@umich.edu 542686Sksewell@umich.edu class FPCompareOp : public FPOp 552686Sksewell@umich.edu { 562686Sksewell@umich.edu protected: 572686Sksewell@umich.edu FPCompareOp(const char *mnem, MachInst _machInst, OpClass __opClass) : FPOp(mnem, _machInst, __opClass) 582686Sksewell@umich.edu { 592686Sksewell@umich.edu } 602686Sksewell@umich.edu 612686Sksewell@umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 622686Sksewell@umich.edu 632038SN/A }; 642038SN/A}}; 652038SN/A 662038SN/Aoutput decoder {{ 672686Sksewell@umich.edu std::string FPCompareOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 682038SN/A { 692686Sksewell@umich.edu std::stringstream ss; 702686Sksewell@umich.edu 712686Sksewell@umich.edu ccprintf(ss, "%-10s ", mnemonic); 722686Sksewell@umich.edu 732686Sksewell@umich.edu ccprintf(ss,"%d",CC); 742686Sksewell@umich.edu 752686Sksewell@umich.edu if(_numSrcRegs > 0) { 762686Sksewell@umich.edu ss << ", "; 772686Sksewell@umich.edu printReg(ss, _srcRegIdx[0]); 782686Sksewell@umich.edu } 792686Sksewell@umich.edu 802686Sksewell@umich.edu if(_numSrcRegs > 1) { 812686Sksewell@umich.edu ss << ", "; 822686Sksewell@umich.edu printReg(ss, _srcRegIdx[1]); 832686Sksewell@umich.edu } 842686Sksewell@umich.edu 852686Sksewell@umich.edu return ss.str(); 862038SN/A } 872038SN/A}}; 882038SN/A 892686Sksewell@umich.eduoutput exec {{ 902038SN/A 912686Sksewell@umich.edu //If any operand is Nan return the appropriate QNaN 922686Sksewell@umich.edu template <class T> 932686Sksewell@umich.edu bool 942686Sksewell@umich.edu fpNanOperands(FPOp *inst, %(CPU_exec_context)s *xc, const T &src_type, 952686Sksewell@umich.edu Trace::InstRecord *traceData) 962686Sksewell@umich.edu { 972686Sksewell@umich.edu uint64_t mips_nan = 0; 982686Sksewell@umich.edu T src_op = 0; 992686Sksewell@umich.edu int size = sizeof(src_op) * 8; 1002686Sksewell@umich.edu 1012686Sksewell@umich.edu for (int i = 0; i < inst->numSrcRegs(); i++) { 1022686Sksewell@umich.edu uint64_t src_bits = xc->readFloatRegBits(inst, 0, size); 1032686Sksewell@umich.edu 1042686Sksewell@umich.edu if (isNan(&src_bits, size) ) { 1052686Sksewell@umich.edu if (isSnan(&src_bits, size)) { 1062686Sksewell@umich.edu switch (size) 1072686Sksewell@umich.edu { 1082686Sksewell@umich.edu case 32: mips_nan = MIPS32_QNAN; break; 1092686Sksewell@umich.edu case 64: mips_nan = MIPS64_QNAN; break; 1102686Sksewell@umich.edu default: panic("Unsupported Floating Point Size (%d)", size); 1112686Sksewell@umich.edu } 1122686Sksewell@umich.edu } else { 1132686Sksewell@umich.edu mips_nan = src_bits; 1142686Sksewell@umich.edu } 1152686Sksewell@umich.edu 1162686Sksewell@umich.edu xc->setFloatRegBits(inst, 0, mips_nan, size); 1172686Sksewell@umich.edu if (traceData) { traceData->setData(mips_nan); } 1182686Sksewell@umich.edu return true; 1192686Sksewell@umich.edu } 1202686Sksewell@umich.edu } 1212686Sksewell@umich.edu return false; 1222686Sksewell@umich.edu } 1232686Sksewell@umich.edu 1242686Sksewell@umich.edu template <class T> 1252686Sksewell@umich.edu bool 1262687Sksewell@umich.edu fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *cpu, const T dest_val, 1272686Sksewell@umich.edu Trace::InstRecord *traceData) 1282686Sksewell@umich.edu { 1292686Sksewell@umich.edu uint64_t mips_nan = 0; 1302686Sksewell@umich.edu T src_op = dest_val; 1312686Sksewell@umich.edu int size = sizeof(src_op) * 8; 1322686Sksewell@umich.edu 1332686Sksewell@umich.edu if (isNan(&src_op, size)) { 1342686Sksewell@umich.edu switch (size) 1352686Sksewell@umich.edu { 1362686Sksewell@umich.edu case 32: mips_nan = MIPS32_QNAN; break; 1372686Sksewell@umich.edu case 64: mips_nan = MIPS64_QNAN; break; 1382686Sksewell@umich.edu default: panic("Unsupported Floating Point Size (%d)", size); 1392686Sksewell@umich.edu } 1402686Sksewell@umich.edu 1412686Sksewell@umich.edu //Set value to QNAN 1422687Sksewell@umich.edu cpu->setFloatRegBits(inst, 0, mips_nan, size); 1432686Sksewell@umich.edu 1442686Sksewell@umich.edu //Read FCSR from FloatRegFile 1452687Sksewell@umich.edu uint32_t fcsr_bits = cpu->tc->readFloatRegBits(FCSR); 1462686Sksewell@umich.edu 1472686Sksewell@umich.edu //Write FCSR from FloatRegFile 1482687Sksewell@umich.edu cpu->tc->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits)); 1492686Sksewell@umich.edu 1502686Sksewell@umich.edu if (traceData) { traceData->setData(mips_nan); } 1512686Sksewell@umich.edu return true; 1522686Sksewell@umich.edu } 1532686Sksewell@umich.edu 1542686Sksewell@umich.edu return false; 1552686Sksewell@umich.edu } 1562686Sksewell@umich.edu 1572686Sksewell@umich.edu void 1582687Sksewell@umich.edu fpResetCauseBits(%(CPU_exec_context)s *cpu) 1592686Sksewell@umich.edu { 1602686Sksewell@umich.edu //Read FCSR from FloatRegFile 1612687Sksewell@umich.edu uint32_t fcsr = cpu->tc->readFloatRegBits(FCSR); 1622686Sksewell@umich.edu 1632686Sksewell@umich.edu fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0); 1642686Sksewell@umich.edu 1652686Sksewell@umich.edu //Write FCSR from FloatRegFile 1662687Sksewell@umich.edu cpu->tc->setFloatRegBits(FCSR, fcsr); 1672686Sksewell@umich.edu } 1682686Sksewell@umich.edu}}; 1692686Sksewell@umich.edu 1702686Sksewell@umich.edudef template FloatingPointExecute {{ 1712686Sksewell@umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1722686Sksewell@umich.edu { 1732686Sksewell@umich.edu Fault fault = NoFault; 1742686Sksewell@umich.edu 1752686Sksewell@umich.edu %(fp_enable_check)s; 1762686Sksewell@umich.edu 1772686Sksewell@umich.edu //When is the right time to reset cause bits? 1782686Sksewell@umich.edu //start of every instruction or every cycle? 1792686Sksewell@umich.edu fpResetCauseBits(xc); 1802686Sksewell@umich.edu 1812686Sksewell@umich.edu %(op_decl)s; 1822686Sksewell@umich.edu %(op_rd)s; 1832686Sksewell@umich.edu 1842686Sksewell@umich.edu //Check if any FP operand is a NaN value 1852686Sksewell@umich.edu if (!fpNanOperands((FPOp*)this, xc, Fd, traceData)) { 1862686Sksewell@umich.edu %(code)s; 1872686Sksewell@umich.edu 1882686Sksewell@umich.edu //Change this code for Full-System/Sycall Emulation 1892686Sksewell@umich.edu //separation 1902686Sksewell@umich.edu //---- 1912686Sksewell@umich.edu //Should Full System-Mode throw a fault here? 1922686Sksewell@umich.edu //---- 1932686Sksewell@umich.edu //Check for IEEE 754 FP Exceptions 1942686Sksewell@umich.edu //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData); 1952686Sksewell@umich.edu if (!fpInvalidOp((FPOp*)this, xc, Fd, traceData) && 1962686Sksewell@umich.edu fault == NoFault) 1972686Sksewell@umich.edu { 1982686Sksewell@umich.edu %(op_wb)s; 1992686Sksewell@umich.edu } 2002686Sksewell@umich.edu } 2012686Sksewell@umich.edu 2022686Sksewell@umich.edu return fault; 2032686Sksewell@umich.edu } 2042686Sksewell@umich.edu}}; 2052686Sksewell@umich.edu 2062686Sksewell@umich.edu// Primary format for float point operate instructions: 2072135SN/Adef format FloatOp(code, *flags) {{ 2082686Sksewell@umich.edu iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code), flags) 2092038SN/A header_output = BasicDeclare.subst(iop) 2102038SN/A decoder_output = BasicConstructor.subst(iop) 2112135SN/A decode_block = BasicDecode.subst(iop) 2122686Sksewell@umich.edu exec_output = FloatingPointExecute.subst(iop) 2132084SN/A}}; 2142084SN/A 2152686Sksewell@umich.edudef format FloatCompareOp(cond_code, *flags) {{ 2162686Sksewell@umich.edu import sys 2172607SN/A 2182686Sksewell@umich.edu code = 'bool cond;\n' 2192686Sksewell@umich.edu if '.sf' in cond_code or 'SinglePrecision' in flags: 2202686Sksewell@umich.edu if 'QnanException' in flags: 2212686Sksewell@umich.edu code += 'if (isQnan(&Fs.sf, 32) || isQnan(&Ft.sf, 32)) {\n' 2222686Sksewell@umich.edu code += '\tFCSR = genInvalidVector(FCSR);\n' 2232686Sksewell@umich.edu code += '\treturn NoFault;' 2242686Sksewell@umich.edu code += '}\n else ' 2252686Sksewell@umich.edu code += 'if (isNan(&Fs.sf, 32) || isNan(&Ft.sf, 32)) {\n' 2262686Sksewell@umich.edu elif '.df' in cond_code or 'DoublePrecision' in flags: 2272686Sksewell@umich.edu if 'QnanException' in flags: 2282686Sksewell@umich.edu code += 'if (isQnan(&Fs.df, 64) || isQnan(&Ft.df, 64)) {\n' 2292686Sksewell@umich.edu code += '\tFCSR = genInvalidVector(FCSR);\n' 2302686Sksewell@umich.edu code += '\treturn NoFault;' 2312686Sksewell@umich.edu code += '}\n else ' 2322686Sksewell@umich.edu code += 'if (isNan(&Fs.df, 64) || isNan(&Ft.df, 64)) {\n' 2332686Sksewell@umich.edu else: 2342686Sksewell@umich.edu sys.exit('Decoder Failed: Can\'t Determine Operand Type\n') 2352686Sksewell@umich.edu 2362686Sksewell@umich.edu if 'UnorderedTrue' in flags: 2372686Sksewell@umich.edu code += 'cond = 1;\n' 2382686Sksewell@umich.edu elif 'UnorderedFalse' in flags: 2392686Sksewell@umich.edu code += 'cond = 0;\n' 2402686Sksewell@umich.edu else: 2412686Sksewell@umich.edu sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n') 2422686Sksewell@umich.edu 2432686Sksewell@umich.edu code += '} else {\n' 2442686Sksewell@umich.edu code += cond_code + '}' 2452686Sksewell@umich.edu code += 'FCSR = genCCVector(FCSR, CC, cond);\n' 2462686Sksewell@umich.edu 2472686Sksewell@umich.edu iop = InstObjParams(name, Name, 'FPCompareOp', CodeBlock(code)) 2482686Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 2492686Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 2502686Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 2512686Sksewell@umich.edu exec_output = BasicExecute.subst(iop) 2522607SN/A}}; 2532607SN/A 2542607SN/Adef format FloatConvertOp(code, *flags) {{ 2552686Sksewell@umich.edu import sys 2562686Sksewell@umich.edu 2572686Sksewell@umich.edu #Determine Source Type 2582686Sksewell@umich.edu convert = 'fpConvert(' 2592686Sksewell@umich.edu if '.sf' in code: 2602686Sksewell@umich.edu code = 'float ' + code + '\n' 2612686Sksewell@umich.edu convert += 'SINGLE_TO_' 2622686Sksewell@umich.edu elif '.df' in code: 2632686Sksewell@umich.edu code = 'double ' + code + '\n' 2642686Sksewell@umich.edu convert += 'DOUBLE_TO_' 2652686Sksewell@umich.edu elif '.uw' in code: 2662686Sksewell@umich.edu code = 'uint32_t ' + code + '\n' 2672686Sksewell@umich.edu convert += 'WORD_TO_' 2682686Sksewell@umich.edu elif '.ud' in code: 2692686Sksewell@umich.edu code = 'uint64_t ' + code + '\n' 2702686Sksewell@umich.edu convert += 'LONG_TO_' 2712686Sksewell@umich.edu else: 2722686Sksewell@umich.edu sys.exit("Error Determining Source Type for Conversion") 2732686Sksewell@umich.edu 2742686Sksewell@umich.edu #Determine Destination Type 2752686Sksewell@umich.edu if 'ToSingle' in flags: 2762686Sksewell@umich.edu code += 'Fd.uw = ' + convert + 'SINGLE, ' 2772686Sksewell@umich.edu elif 'ToDouble' in flags: 2782686Sksewell@umich.edu code += 'Fd.ud = ' + convert + 'DOUBLE, ' 2792686Sksewell@umich.edu elif 'ToWord' in flags: 2802686Sksewell@umich.edu code += 'Fd.uw = ' + convert + 'WORD, ' 2812686Sksewell@umich.edu elif 'ToLong' in flags: 2822686Sksewell@umich.edu code += 'Fd.ud = ' + convert + 'LONG, ' 2832686Sksewell@umich.edu else: 2842686Sksewell@umich.edu sys.exit("Error Determining Destination Type for Conversion") 2852686Sksewell@umich.edu 2862686Sksewell@umich.edu #Figure out how to round value 2872686Sksewell@umich.edu if 'Ceil' in flags: 2882686Sksewell@umich.edu code += 'ceil(val)); ' 2892686Sksewell@umich.edu elif 'Floor' in flags: 2902686Sksewell@umich.edu code += 'floor(val)); ' 2912686Sksewell@umich.edu elif 'Round' in flags: 2922686Sksewell@umich.edu code += 'roundFP(val, 0)); ' 2932686Sksewell@umich.edu elif 'Trunc' in flags: 2942686Sksewell@umich.edu code += 'truncFP(val));' 2952686Sksewell@umich.edu else: 2962686Sksewell@umich.edu code += 'val); ' 2972686Sksewell@umich.edu 2982686Sksewell@umich.edu iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code)) 2992686Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 3002686Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 3012686Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 3022686Sksewell@umich.edu exec_output = BasicExecute.subst(iop) 3032686Sksewell@umich.edu}}; 3042686Sksewell@umich.edu 3052686Sksewell@umich.edudef format FloatAccOp(code, *flags) {{ 3062686Sksewell@umich.edu iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code), flags) 3072607SN/A header_output = BasicDeclare.subst(iop) 3082607SN/A decoder_output = BasicConstructor.subst(iop) 3092607SN/A decode_block = BasicDecode.subst(iop) 3102607SN/A exec_output = BasicExecute.subst(iop) 3112607SN/A}}; 3122607SN/A 3132573SN/A// Primary format for float64 operate instructions: 3142135SN/Adef format Float64Op(code, *flags) {{ 3152135SN/A iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags) 3162084SN/A header_output = BasicDeclare.subst(iop) 3172084SN/A decoder_output = BasicConstructor.subst(iop) 3182135SN/A decode_block = BasicDecode.subst(iop) 3192135SN/A exec_output = BasicExecute.subst(iop) 3202038SN/A}}; 3212607SN/A 3222686Sksewell@umich.edudef format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{ 3232686Sksewell@umich.edu import sys 3242686Sksewell@umich.edu 3252686Sksewell@umich.edu code = 'bool cond1, cond2;\n' 3262686Sksewell@umich.edu code += 'bool code_block1, code_block2;\n' 3272686Sksewell@umich.edu code += 'code_block1 = code_block2 = true;\n' 3282686Sksewell@umich.edu 3292686Sksewell@umich.edu if 'QnanException' in flags: 3302686Sksewell@umich.edu code += 'if (isQnan(&Fs1.sf, 32) || isQnan(&Ft1.sf, 32)) {\n' 3312686Sksewell@umich.edu code += '\tFCSR = genInvalidVector(FCSR);\n' 3322686Sksewell@umich.edu code += 'code_block1 = false;' 3332686Sksewell@umich.edu code += '}\n' 3342686Sksewell@umich.edu code += 'if (isQnan(&Fs2.sf, 32) || isQnan(&Ft2.sf, 32)) {\n' 3352686Sksewell@umich.edu code += '\tFCSR = genInvalidVector(FCSR);\n' 3362686Sksewell@umich.edu code += 'code_block2 = false;' 3372686Sksewell@umich.edu code += '}\n' 3382686Sksewell@umich.edu 3392686Sksewell@umich.edu code += 'if (code_block1) {' 3402686Sksewell@umich.edu code += '\tif (isNan(&Fs1.sf, 32) || isNan(&Ft1.sf, 32)) {\n' 3412686Sksewell@umich.edu if 'UnorderedTrue' in flags: 3422686Sksewell@umich.edu code += 'cond1 = 1;\n' 3432686Sksewell@umich.edu elif 'UnorderedFalse' in flags: 3442686Sksewell@umich.edu code += 'cond1 = 0;\n' 3452686Sksewell@umich.edu else: 3462686Sksewell@umich.edu sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n') 3472686Sksewell@umich.edu code += '} else {\n' 3482686Sksewell@umich.edu code += cond_code1 3492686Sksewell@umich.edu code += 'FCSR = genCCVector(FCSR, CC, cond1);}\n}\n' 3502686Sksewell@umich.edu 3512686Sksewell@umich.edu code += 'if (code_block2) {' 3522686Sksewell@umich.edu code += '\tif (isNan(&Fs2.sf, 32) || isNan(&Ft2.sf, 32)) {\n' 3532686Sksewell@umich.edu if 'UnorderedTrue' in flags: 3542686Sksewell@umich.edu code += 'cond2 = 1;\n' 3552686Sksewell@umich.edu elif 'UnorderedFalse' in flags: 3562686Sksewell@umich.edu code += 'cond2 = 0;\n' 3572686Sksewell@umich.edu else: 3582686Sksewell@umich.edu sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n') 3592686Sksewell@umich.edu code += '} else {\n' 3602686Sksewell@umich.edu code += cond_code2 3612686Sksewell@umich.edu code += 'FCSR = genCCVector(FCSR, CC, cond2);}\n}' 3622686Sksewell@umich.edu 3632686Sksewell@umich.edu iop = InstObjParams(name, Name, 'FPCompareOp', CodeBlock(code)) 3642686Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 3652686Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 3662686Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 3672686Sksewell@umich.edu exec_output = BasicExecute.subst(iop) 3682607SN/A}}; 3692608SN/A 370