fp.isa revision 2686
12135SN/A// -*- mode:c++ -*- 22135SN/A 32038SN/A//////////////////////////////////////////////////////////////////// 42038SN/A// 52038SN/A// Floating Point operate instructions 62038SN/A// 72038SN/A 82038SN/Aoutput header {{ 92038SN/A /** 102135SN/A * Base class for FP operations. 112038SN/A */ 122038SN/A class FPOp : public MipsStaticInst 132038SN/A { 142038SN/A protected: 152038SN/A 162038SN/A /// Constructor 172038SN/A FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) 182038SN/A { 192038SN/A } 202038SN/A 212686Sksewell@umich.edu //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 222686Sksewell@umich.edu 232686Sksewell@umich.edu //needs function to check for fpEnable or not 242686Sksewell@umich.edu }; 252686Sksewell@umich.edu 262686Sksewell@umich.edu class FPCompareOp : public FPOp 272686Sksewell@umich.edu { 282686Sksewell@umich.edu protected: 292686Sksewell@umich.edu FPCompareOp(const char *mnem, MachInst _machInst, OpClass __opClass) : FPOp(mnem, _machInst, __opClass) 302686Sksewell@umich.edu { 312686Sksewell@umich.edu } 322686Sksewell@umich.edu 332686Sksewell@umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 342686Sksewell@umich.edu 352038SN/A }; 362038SN/A}}; 372038SN/A 382038SN/Aoutput decoder {{ 392686Sksewell@umich.edu std::string FPCompareOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 402038SN/A { 412686Sksewell@umich.edu std::stringstream ss; 422686Sksewell@umich.edu 432686Sksewell@umich.edu ccprintf(ss, "%-10s ", mnemonic); 442686Sksewell@umich.edu 452686Sksewell@umich.edu ccprintf(ss,"%d",CC); 462686Sksewell@umich.edu 472686Sksewell@umich.edu if(_numSrcRegs > 0) { 482686Sksewell@umich.edu ss << ", "; 492686Sksewell@umich.edu printReg(ss, _srcRegIdx[0]); 502686Sksewell@umich.edu } 512686Sksewell@umich.edu 522686Sksewell@umich.edu if(_numSrcRegs > 1) { 532686Sksewell@umich.edu ss << ", "; 542686Sksewell@umich.edu printReg(ss, _srcRegIdx[1]); 552686Sksewell@umich.edu } 562686Sksewell@umich.edu 572686Sksewell@umich.edu return ss.str(); 582038SN/A } 592038SN/A}}; 602038SN/A 612686Sksewell@umich.eduoutput exec {{ 622038SN/A 632686Sksewell@umich.edu //If any operand is Nan return the appropriate QNaN 642686Sksewell@umich.edu template <class T> 652686Sksewell@umich.edu bool 662686Sksewell@umich.edu fpNanOperands(FPOp *inst, %(CPU_exec_context)s *xc, const T &src_type, 672686Sksewell@umich.edu Trace::InstRecord *traceData) 682686Sksewell@umich.edu { 692686Sksewell@umich.edu uint64_t mips_nan = 0; 702686Sksewell@umich.edu T src_op = 0; 712686Sksewell@umich.edu int size = sizeof(src_op) * 8; 722686Sksewell@umich.edu 732686Sksewell@umich.edu for (int i = 0; i < inst->numSrcRegs(); i++) { 742686Sksewell@umich.edu uint64_t src_bits = xc->readFloatRegBits(inst, 0, size); 752686Sksewell@umich.edu 762686Sksewell@umich.edu if (isNan(&src_bits, size) ) { 772686Sksewell@umich.edu if (isSnan(&src_bits, size)) { 782686Sksewell@umich.edu switch (size) 792686Sksewell@umich.edu { 802686Sksewell@umich.edu case 32: mips_nan = MIPS32_QNAN; break; 812686Sksewell@umich.edu case 64: mips_nan = MIPS64_QNAN; break; 822686Sksewell@umich.edu default: panic("Unsupported Floating Point Size (%d)", size); 832686Sksewell@umich.edu } 842686Sksewell@umich.edu } else { 852686Sksewell@umich.edu mips_nan = src_bits; 862686Sksewell@umich.edu } 872686Sksewell@umich.edu 882686Sksewell@umich.edu xc->setFloatRegBits(inst, 0, mips_nan, size); 892686Sksewell@umich.edu if (traceData) { traceData->setData(mips_nan); } 902686Sksewell@umich.edu return true; 912686Sksewell@umich.edu } 922686Sksewell@umich.edu } 932686Sksewell@umich.edu return false; 942686Sksewell@umich.edu } 952686Sksewell@umich.edu 962686Sksewell@umich.edu template <class T> 972686Sksewell@umich.edu bool 982686Sksewell@umich.edu fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *xc, const T dest_val, 992686Sksewell@umich.edu Trace::InstRecord *traceData) 1002686Sksewell@umich.edu { 1012686Sksewell@umich.edu uint64_t mips_nan = 0; 1022686Sksewell@umich.edu T src_op = dest_val; 1032686Sksewell@umich.edu int size = sizeof(src_op) * 8; 1042686Sksewell@umich.edu 1052686Sksewell@umich.edu if (isNan(&src_op, size)) { 1062686Sksewell@umich.edu switch (size) 1072686Sksewell@umich.edu { 1082686Sksewell@umich.edu case 32: mips_nan = MIPS32_QNAN; break; 1092686Sksewell@umich.edu case 64: mips_nan = MIPS64_QNAN; break; 1102686Sksewell@umich.edu default: panic("Unsupported Floating Point Size (%d)", size); 1112686Sksewell@umich.edu } 1122686Sksewell@umich.edu 1132686Sksewell@umich.edu //Set value to QNAN 1142686Sksewell@umich.edu xc->setFloatRegBits(inst, 0, mips_nan, size); 1152686Sksewell@umich.edu 1162686Sksewell@umich.edu //Read FCSR from FloatRegFile 1172686Sksewell@umich.edu uint32_t fcsr_bits = xc->cpuXC->readFloatRegBits(FCSR); 1182686Sksewell@umich.edu 1192686Sksewell@umich.edu //Write FCSR from FloatRegFile 1202686Sksewell@umich.edu xc->cpuXC->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits)); 1212686Sksewell@umich.edu 1222686Sksewell@umich.edu if (traceData) { traceData->setData(mips_nan); } 1232686Sksewell@umich.edu return true; 1242686Sksewell@umich.edu } 1252686Sksewell@umich.edu 1262686Sksewell@umich.edu return false; 1272686Sksewell@umich.edu } 1282686Sksewell@umich.edu 1292686Sksewell@umich.edu void 1302686Sksewell@umich.edu fpResetCauseBits(%(CPU_exec_context)s *xc) 1312686Sksewell@umich.edu { 1322686Sksewell@umich.edu //Read FCSR from FloatRegFile 1332686Sksewell@umich.edu uint32_t fcsr = xc->cpuXC->readFloatRegBits(FCSR); 1342686Sksewell@umich.edu 1352686Sksewell@umich.edu fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0); 1362686Sksewell@umich.edu 1372686Sksewell@umich.edu //Write FCSR from FloatRegFile 1382686Sksewell@umich.edu xc->cpuXC->setFloatRegBits(FCSR, fcsr); 1392686Sksewell@umich.edu } 1402686Sksewell@umich.edu}}; 1412686Sksewell@umich.edu 1422686Sksewell@umich.edudef template FloatingPointExecute {{ 1432686Sksewell@umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1442686Sksewell@umich.edu { 1452686Sksewell@umich.edu Fault fault = NoFault; 1462686Sksewell@umich.edu 1472686Sksewell@umich.edu %(fp_enable_check)s; 1482686Sksewell@umich.edu 1492686Sksewell@umich.edu //When is the right time to reset cause bits? 1502686Sksewell@umich.edu //start of every instruction or every cycle? 1512686Sksewell@umich.edu fpResetCauseBits(xc); 1522686Sksewell@umich.edu 1532686Sksewell@umich.edu %(op_decl)s; 1542686Sksewell@umich.edu %(op_rd)s; 1552686Sksewell@umich.edu 1562686Sksewell@umich.edu //Check if any FP operand is a NaN value 1572686Sksewell@umich.edu if (!fpNanOperands((FPOp*)this, xc, Fd, traceData)) { 1582686Sksewell@umich.edu %(code)s; 1592686Sksewell@umich.edu 1602686Sksewell@umich.edu //Change this code for Full-System/Sycall Emulation 1612686Sksewell@umich.edu //separation 1622686Sksewell@umich.edu //---- 1632686Sksewell@umich.edu //Should Full System-Mode throw a fault here? 1642686Sksewell@umich.edu //---- 1652686Sksewell@umich.edu //Check for IEEE 754 FP Exceptions 1662686Sksewell@umich.edu //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData); 1672686Sksewell@umich.edu if (!fpInvalidOp((FPOp*)this, xc, Fd, traceData) && 1682686Sksewell@umich.edu fault == NoFault) 1692686Sksewell@umich.edu { 1702686Sksewell@umich.edu %(op_wb)s; 1712686Sksewell@umich.edu } 1722686Sksewell@umich.edu } 1732686Sksewell@umich.edu 1742686Sksewell@umich.edu return fault; 1752686Sksewell@umich.edu } 1762686Sksewell@umich.edu}}; 1772686Sksewell@umich.edu 1782686Sksewell@umich.edu// Primary format for float point operate instructions: 1792135SN/Adef format FloatOp(code, *flags) {{ 1802686Sksewell@umich.edu iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code), flags) 1812038SN/A header_output = BasicDeclare.subst(iop) 1822038SN/A decoder_output = BasicConstructor.subst(iop) 1832135SN/A decode_block = BasicDecode.subst(iop) 1842686Sksewell@umich.edu exec_output = FloatingPointExecute.subst(iop) 1852084SN/A}}; 1862084SN/A 1872686Sksewell@umich.edudef format FloatCompareOp(cond_code, *flags) {{ 1882686Sksewell@umich.edu import sys 1892607SN/A 1902686Sksewell@umich.edu code = 'bool cond;\n' 1912686Sksewell@umich.edu if '.sf' in cond_code or 'SinglePrecision' in flags: 1922686Sksewell@umich.edu if 'QnanException' in flags: 1932686Sksewell@umich.edu code += 'if (isQnan(&Fs.sf, 32) || isQnan(&Ft.sf, 32)) {\n' 1942686Sksewell@umich.edu code += '\tFCSR = genInvalidVector(FCSR);\n' 1952686Sksewell@umich.edu code += '\treturn NoFault;' 1962686Sksewell@umich.edu code += '}\n else ' 1972686Sksewell@umich.edu code += 'if (isNan(&Fs.sf, 32) || isNan(&Ft.sf, 32)) {\n' 1982686Sksewell@umich.edu elif '.df' in cond_code or 'DoublePrecision' in flags: 1992686Sksewell@umich.edu if 'QnanException' in flags: 2002686Sksewell@umich.edu code += 'if (isQnan(&Fs.df, 64) || isQnan(&Ft.df, 64)) {\n' 2012686Sksewell@umich.edu code += '\tFCSR = genInvalidVector(FCSR);\n' 2022686Sksewell@umich.edu code += '\treturn NoFault;' 2032686Sksewell@umich.edu code += '}\n else ' 2042686Sksewell@umich.edu code += 'if (isNan(&Fs.df, 64) || isNan(&Ft.df, 64)) {\n' 2052686Sksewell@umich.edu else: 2062686Sksewell@umich.edu sys.exit('Decoder Failed: Can\'t Determine Operand Type\n') 2072686Sksewell@umich.edu 2082686Sksewell@umich.edu if 'UnorderedTrue' in flags: 2092686Sksewell@umich.edu code += 'cond = 1;\n' 2102686Sksewell@umich.edu elif 'UnorderedFalse' in flags: 2112686Sksewell@umich.edu code += 'cond = 0;\n' 2122686Sksewell@umich.edu else: 2132686Sksewell@umich.edu sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n') 2142686Sksewell@umich.edu 2152686Sksewell@umich.edu code += '} else {\n' 2162686Sksewell@umich.edu code += cond_code + '}' 2172686Sksewell@umich.edu code += 'FCSR = genCCVector(FCSR, CC, cond);\n' 2182686Sksewell@umich.edu 2192686Sksewell@umich.edu iop = InstObjParams(name, Name, 'FPCompareOp', CodeBlock(code)) 2202686Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 2212686Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 2222686Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 2232686Sksewell@umich.edu exec_output = BasicExecute.subst(iop) 2242607SN/A}}; 2252607SN/A 2262607SN/Adef format FloatConvertOp(code, *flags) {{ 2272686Sksewell@umich.edu import sys 2282686Sksewell@umich.edu 2292686Sksewell@umich.edu #Determine Source Type 2302686Sksewell@umich.edu convert = 'fpConvert(' 2312686Sksewell@umich.edu if '.sf' in code: 2322686Sksewell@umich.edu code = 'float ' + code + '\n' 2332686Sksewell@umich.edu convert += 'SINGLE_TO_' 2342686Sksewell@umich.edu elif '.df' in code: 2352686Sksewell@umich.edu code = 'double ' + code + '\n' 2362686Sksewell@umich.edu convert += 'DOUBLE_TO_' 2372686Sksewell@umich.edu elif '.uw' in code: 2382686Sksewell@umich.edu code = 'uint32_t ' + code + '\n' 2392686Sksewell@umich.edu convert += 'WORD_TO_' 2402686Sksewell@umich.edu elif '.ud' in code: 2412686Sksewell@umich.edu code = 'uint64_t ' + code + '\n' 2422686Sksewell@umich.edu convert += 'LONG_TO_' 2432686Sksewell@umich.edu else: 2442686Sksewell@umich.edu sys.exit("Error Determining Source Type for Conversion") 2452686Sksewell@umich.edu 2462686Sksewell@umich.edu #Determine Destination Type 2472686Sksewell@umich.edu if 'ToSingle' in flags: 2482686Sksewell@umich.edu code += 'Fd.uw = ' + convert + 'SINGLE, ' 2492686Sksewell@umich.edu elif 'ToDouble' in flags: 2502686Sksewell@umich.edu code += 'Fd.ud = ' + convert + 'DOUBLE, ' 2512686Sksewell@umich.edu elif 'ToWord' in flags: 2522686Sksewell@umich.edu code += 'Fd.uw = ' + convert + 'WORD, ' 2532686Sksewell@umich.edu elif 'ToLong' in flags: 2542686Sksewell@umich.edu code += 'Fd.ud = ' + convert + 'LONG, ' 2552686Sksewell@umich.edu else: 2562686Sksewell@umich.edu sys.exit("Error Determining Destination Type for Conversion") 2572686Sksewell@umich.edu 2582686Sksewell@umich.edu #Figure out how to round value 2592686Sksewell@umich.edu if 'Ceil' in flags: 2602686Sksewell@umich.edu code += 'ceil(val)); ' 2612686Sksewell@umich.edu elif 'Floor' in flags: 2622686Sksewell@umich.edu code += 'floor(val)); ' 2632686Sksewell@umich.edu elif 'Round' in flags: 2642686Sksewell@umich.edu code += 'roundFP(val, 0)); ' 2652686Sksewell@umich.edu elif 'Trunc' in flags: 2662686Sksewell@umich.edu code += 'truncFP(val));' 2672686Sksewell@umich.edu else: 2682686Sksewell@umich.edu code += 'val); ' 2692686Sksewell@umich.edu 2702686Sksewell@umich.edu iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code)) 2712686Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 2722686Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 2732686Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 2742686Sksewell@umich.edu exec_output = BasicExecute.subst(iop) 2752686Sksewell@umich.edu}}; 2762686Sksewell@umich.edu 2772686Sksewell@umich.edudef format FloatAccOp(code, *flags) {{ 2782686Sksewell@umich.edu iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code), flags) 2792607SN/A header_output = BasicDeclare.subst(iop) 2802607SN/A decoder_output = BasicConstructor.subst(iop) 2812607SN/A decode_block = BasicDecode.subst(iop) 2822607SN/A exec_output = BasicExecute.subst(iop) 2832607SN/A}}; 2842607SN/A 2852573SN/A// Primary format for float64 operate instructions: 2862135SN/Adef format Float64Op(code, *flags) {{ 2872135SN/A iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags) 2882084SN/A header_output = BasicDeclare.subst(iop) 2892084SN/A decoder_output = BasicConstructor.subst(iop) 2902135SN/A decode_block = BasicDecode.subst(iop) 2912135SN/A exec_output = BasicExecute.subst(iop) 2922038SN/A}}; 2932607SN/A 2942686Sksewell@umich.edudef format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{ 2952686Sksewell@umich.edu import sys 2962686Sksewell@umich.edu 2972686Sksewell@umich.edu code = 'bool cond1, cond2;\n' 2982686Sksewell@umich.edu code += 'bool code_block1, code_block2;\n' 2992686Sksewell@umich.edu code += 'code_block1 = code_block2 = true;\n' 3002686Sksewell@umich.edu 3012686Sksewell@umich.edu if 'QnanException' in flags: 3022686Sksewell@umich.edu code += 'if (isQnan(&Fs1.sf, 32) || isQnan(&Ft1.sf, 32)) {\n' 3032686Sksewell@umich.edu code += '\tFCSR = genInvalidVector(FCSR);\n' 3042686Sksewell@umich.edu code += 'code_block1 = false;' 3052686Sksewell@umich.edu code += '}\n' 3062686Sksewell@umich.edu code += 'if (isQnan(&Fs2.sf, 32) || isQnan(&Ft2.sf, 32)) {\n' 3072686Sksewell@umich.edu code += '\tFCSR = genInvalidVector(FCSR);\n' 3082686Sksewell@umich.edu code += 'code_block2 = false;' 3092686Sksewell@umich.edu code += '}\n' 3102686Sksewell@umich.edu 3112686Sksewell@umich.edu code += 'if (code_block1) {' 3122686Sksewell@umich.edu code += '\tif (isNan(&Fs1.sf, 32) || isNan(&Ft1.sf, 32)) {\n' 3132686Sksewell@umich.edu if 'UnorderedTrue' in flags: 3142686Sksewell@umich.edu code += 'cond1 = 1;\n' 3152686Sksewell@umich.edu elif 'UnorderedFalse' in flags: 3162686Sksewell@umich.edu code += 'cond1 = 0;\n' 3172686Sksewell@umich.edu else: 3182686Sksewell@umich.edu sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n') 3192686Sksewell@umich.edu code += '} else {\n' 3202686Sksewell@umich.edu code += cond_code1 3212686Sksewell@umich.edu code += 'FCSR = genCCVector(FCSR, CC, cond1);}\n}\n' 3222686Sksewell@umich.edu 3232686Sksewell@umich.edu code += 'if (code_block2) {' 3242686Sksewell@umich.edu code += '\tif (isNan(&Fs2.sf, 32) || isNan(&Ft2.sf, 32)) {\n' 3252686Sksewell@umich.edu if 'UnorderedTrue' in flags: 3262686Sksewell@umich.edu code += 'cond2 = 1;\n' 3272686Sksewell@umich.edu elif 'UnorderedFalse' in flags: 3282686Sksewell@umich.edu code += 'cond2 = 0;\n' 3292686Sksewell@umich.edu else: 3302686Sksewell@umich.edu sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n') 3312686Sksewell@umich.edu code += '} else {\n' 3322686Sksewell@umich.edu code += cond_code2 3332686Sksewell@umich.edu code += 'FCSR = genCCVector(FCSR, CC, cond2);}\n}' 3342686Sksewell@umich.edu 3352686Sksewell@umich.edu iop = InstObjParams(name, Name, 'FPCompareOp', CodeBlock(code)) 3362686Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 3372686Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 3382686Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 3392686Sksewell@umich.edu exec_output = BasicExecute.subst(iop) 3402607SN/A}}; 3412608SN/A 342