fp.isa revision 12616
12135SN/A// -*- mode:c++ -*- 22135SN/A 35268Sksewell@umich.edu// Copyright (c) 2007 MIPS Technologies, Inc. 45268Sksewell@umich.edu// All rights reserved. 55268Sksewell@umich.edu// 65268Sksewell@umich.edu// Redistribution and use in source and binary forms, with or without 75268Sksewell@umich.edu// modification, are permitted provided that the following conditions are 85268Sksewell@umich.edu// met: redistributions of source code must retain the above copyright 95268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer; 105268Sksewell@umich.edu// redistributions in binary form must reproduce the above copyright 115268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer in the 125268Sksewell@umich.edu// documentation and/or other materials provided with the distribution; 135268Sksewell@umich.edu// neither the name of the copyright holders nor the names of its 145268Sksewell@umich.edu// contributors may be used to endorse or promote products derived from 155268Sksewell@umich.edu// this software without specific prior written permission. 165268Sksewell@umich.edu// 175268Sksewell@umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185268Sksewell@umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195268Sksewell@umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205268Sksewell@umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215268Sksewell@umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225268Sksewell@umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235268Sksewell@umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245268Sksewell@umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255268Sksewell@umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265268Sksewell@umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275268Sksewell@umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 285268Sksewell@umich.edu// 295268Sksewell@umich.edu// Authors: Korey Sewell 302706Sksewell@umich.edu 312038SN/A//////////////////////////////////////////////////////////////////// 322038SN/A// 332038SN/A// Floating Point operate instructions 342038SN/A// 352038SN/A 362038SN/Aoutput header {{ 372038SN/A /** 382135SN/A * Base class for FP operations. 392038SN/A */ 402038SN/A class FPOp : public MipsStaticInst 412038SN/A { 422038SN/A protected: 432038SN/A 442038SN/A /// Constructor 452038SN/A FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) 462038SN/A { 472038SN/A } 482038SN/A 492686Sksewell@umich.edu //needs function to check for fpEnable or not 502686Sksewell@umich.edu }; 512686Sksewell@umich.edu 522686Sksewell@umich.edu class FPCompareOp : public FPOp 532686Sksewell@umich.edu { 542686Sksewell@umich.edu protected: 552686Sksewell@umich.edu FPCompareOp(const char *mnem, MachInst _machInst, OpClass __opClass) : FPOp(mnem, _machInst, __opClass) 562686Sksewell@umich.edu { 572686Sksewell@umich.edu } 582686Sksewell@umich.edu 5912616Sgabeblack@google.com std::string generateDisassembly( 6012616Sgabeblack@google.com Addr pc, const SymbolTable *symtab) const override; 612038SN/A }; 622038SN/A}}; 632038SN/A 642038SN/Aoutput decoder {{ 652686Sksewell@umich.edu std::string FPCompareOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 662038SN/A { 672686Sksewell@umich.edu std::stringstream ss; 682686Sksewell@umich.edu 692686Sksewell@umich.edu ccprintf(ss, "%-10s ", mnemonic); 702686Sksewell@umich.edu 712686Sksewell@umich.edu ccprintf(ss,"%d",CC); 722686Sksewell@umich.edu 732686Sksewell@umich.edu if(_numSrcRegs > 0) { 742686Sksewell@umich.edu ss << ", "; 752686Sksewell@umich.edu printReg(ss, _srcRegIdx[0]); 762686Sksewell@umich.edu } 772686Sksewell@umich.edu 782686Sksewell@umich.edu if(_numSrcRegs > 1) { 792686Sksewell@umich.edu ss << ", "; 802686Sksewell@umich.edu printReg(ss, _srcRegIdx[1]); 812686Sksewell@umich.edu } 822686Sksewell@umich.edu 832686Sksewell@umich.edu return ss.str(); 842038SN/A } 852038SN/A}}; 862038SN/A 879554Sandreas.hansson@arm.comoutput header {{ 8812234Sgabeblack@google.com void fpResetCauseBits(ExecContext *cpu); 899554Sandreas.hansson@arm.com 909554Sandreas.hansson@arm.com}}; 919554Sandreas.hansson@arm.com 922686Sksewell@umich.eduoutput exec {{ 9312234Sgabeblack@google.com inline Fault checkFpEnableFault(ExecContext *xc) 944661Sksewell@umich.edu { 954661Sksewell@umich.edu //@TODO: Implement correct CP0 checks to see if the CP1 964661Sksewell@umich.edu // unit is enable or not 975222Sksewell@umich.edu if (!isCoprocessorEnabled(xc, 1)) 9810474Sandreas.hansson@arm.com return std::make_shared<CoprocessorUnusableFault>(1); 995222Sksewell@umich.edu 1005222Sksewell@umich.edu return NoFault; 1014661Sksewell@umich.edu } 1022038SN/A 1032686Sksewell@umich.edu //If any operand is Nan return the appropriate QNaN 1042686Sksewell@umich.edu template <class T> 1052686Sksewell@umich.edu bool 10612234Sgabeblack@google.com fpNanOperands(FPOp *inst, ExecContext *xc, const T &src_type, 1072686Sksewell@umich.edu Trace::InstRecord *traceData) 1082686Sksewell@umich.edu { 1092686Sksewell@umich.edu uint64_t mips_nan = 0; 1106314Sgblack@eecs.umich.edu assert(sizeof(T) == 4); 1112686Sksewell@umich.edu 1122686Sksewell@umich.edu for (int i = 0; i < inst->numSrcRegs(); i++) { 1136314Sgblack@eecs.umich.edu uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0); 1142686Sksewell@umich.edu 1156314Sgblack@eecs.umich.edu if (isNan(&src_bits, 32) ) { 1166314Sgblack@eecs.umich.edu mips_nan = MIPS32_QNAN; 1176314Sgblack@eecs.umich.edu xc->setFloatRegOperandBits(inst, 0, mips_nan); 1182686Sksewell@umich.edu if (traceData) { traceData->setData(mips_nan); } 1192686Sksewell@umich.edu return true; 1202686Sksewell@umich.edu } 1212686Sksewell@umich.edu } 1222686Sksewell@umich.edu return false; 1232686Sksewell@umich.edu } 1242686Sksewell@umich.edu 1252686Sksewell@umich.edu template <class T> 1262686Sksewell@umich.edu bool 12712234Sgabeblack@google.com fpInvalidOp(FPOp *inst, ExecContext *cpu, const T dest_val, 1282686Sksewell@umich.edu Trace::InstRecord *traceData) 1292686Sksewell@umich.edu { 1302686Sksewell@umich.edu uint64_t mips_nan = 0; 1312686Sksewell@umich.edu T src_op = dest_val; 1326314Sgblack@eecs.umich.edu assert(sizeof(T) == 4); 1332686Sksewell@umich.edu 1346314Sgblack@eecs.umich.edu if (isNan(&src_op, 32)) { 1356314Sgblack@eecs.umich.edu mips_nan = MIPS32_QNAN; 1362686Sksewell@umich.edu 1372686Sksewell@umich.edu //Set value to QNAN 1386314Sgblack@eecs.umich.edu cpu->setFloatRegOperandBits(inst, 0, mips_nan); 1392686Sksewell@umich.edu 1402686Sksewell@umich.edu //Read FCSR from FloatRegFile 1416383Sgblack@eecs.umich.edu uint32_t fcsr_bits = 1426383Sgblack@eecs.umich.edu cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR); 1432686Sksewell@umich.edu 1444675Sksewell@umich.edu uint32_t new_fcsr = genInvalidVector(fcsr_bits); 1454675Sksewell@umich.edu 1462686Sksewell@umich.edu //Write FCSR from FloatRegFile 1476383Sgblack@eecs.umich.edu cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, new_fcsr); 1482686Sksewell@umich.edu 1492686Sksewell@umich.edu if (traceData) { traceData->setData(mips_nan); } 1502686Sksewell@umich.edu return true; 1512686Sksewell@umich.edu } 1522686Sksewell@umich.edu 1532686Sksewell@umich.edu return false; 1542686Sksewell@umich.edu } 1552686Sksewell@umich.edu 1562686Sksewell@umich.edu void 15712234Sgabeblack@google.com fpResetCauseBits(ExecContext *cpu) 1582686Sksewell@umich.edu { 1592686Sksewell@umich.edu //Read FCSR from FloatRegFile 1606383Sgblack@eecs.umich.edu uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR); 1612686Sksewell@umich.edu 1624661Sksewell@umich.edu // TODO: Use utility function here 1632686Sksewell@umich.edu fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0); 1642686Sksewell@umich.edu 1652686Sksewell@umich.edu //Write FCSR from FloatRegFile 1666383Sgblack@eecs.umich.edu cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, fcsr); 1672686Sksewell@umich.edu } 1682686Sksewell@umich.edu}}; 1692686Sksewell@umich.edu 1702686Sksewell@umich.edudef template FloatingPointExecute {{ 17112234Sgabeblack@google.com Fault %(class_name)s::execute( 17212234Sgabeblack@google.com ExecContext *xc, Trace::InstRecord *traceData) const 1732686Sksewell@umich.edu { 1742686Sksewell@umich.edu Fault fault = NoFault; 1752686Sksewell@umich.edu 1762686Sksewell@umich.edu %(fp_enable_check)s; 1772686Sksewell@umich.edu 1785222Sksewell@umich.edu 1792686Sksewell@umich.edu //When is the right time to reset cause bits? 1802686Sksewell@umich.edu //start of every instruction or every cycle? 1818738Sgblack@eecs.umich.edu if (FullSystem) 1828564Sgblack@eecs.umich.edu fpResetCauseBits(xc); 1832686Sksewell@umich.edu %(op_decl)s; 1842686Sksewell@umich.edu %(op_rd)s; 1852686Sksewell@umich.edu 1862686Sksewell@umich.edu //Check if any FP operand is a NaN value 1872686Sksewell@umich.edu if (!fpNanOperands((FPOp*)this, xc, Fd, traceData)) { 1882686Sksewell@umich.edu %(code)s; 1892686Sksewell@umich.edu 1902686Sksewell@umich.edu //Change this code for Full-System/Sycall Emulation 1912686Sksewell@umich.edu //separation 1922686Sksewell@umich.edu //---- 1932686Sksewell@umich.edu //Should Full System-Mode throw a fault here? 1942686Sksewell@umich.edu //---- 1952686Sksewell@umich.edu //Check for IEEE 754 FP Exceptions 1962686Sksewell@umich.edu //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData); 1978564Sgblack@eecs.umich.edu bool invalid_op = false; 1988738Sgblack@eecs.umich.edu if (FullSystem) { 1998564Sgblack@eecs.umich.edu invalid_op = 2008564Sgblack@eecs.umich.edu fpInvalidOp((FPOp*)this, xc, Fd, traceData); 2018564Sgblack@eecs.umich.edu } 2028564Sgblack@eecs.umich.edu if (!invalid_op && fault == NoFault) { 2032686Sksewell@umich.edu %(op_wb)s; 2042686Sksewell@umich.edu } 2052686Sksewell@umich.edu } 2062686Sksewell@umich.edu 2072686Sksewell@umich.edu return fault; 2082686Sksewell@umich.edu } 2092686Sksewell@umich.edu}}; 2102686Sksewell@umich.edu 2112686Sksewell@umich.edu// Primary format for float point operate instructions: 2122135SN/Adef format FloatOp(code, *flags) {{ 2133951Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'FPOp', code, flags) 2142038SN/A header_output = BasicDeclare.subst(iop) 2152038SN/A decoder_output = BasicConstructor.subst(iop) 2162135SN/A decode_block = BasicDecode.subst(iop) 2172686Sksewell@umich.edu exec_output = FloatingPointExecute.subst(iop) 2182084SN/A}}; 2192084SN/A 2202686Sksewell@umich.edudef format FloatCompareOp(cond_code, *flags) {{ 2212686Sksewell@umich.edu import sys 2222607SN/A 2232686Sksewell@umich.edu code = 'bool cond;\n' 2248588Sgblack@eecs.umich.edu if '_sf' in cond_code or 'SinglePrecision' in flags: 2252686Sksewell@umich.edu if 'QnanException' in flags: 2268588Sgblack@eecs.umich.edu code += 'if (isQnan(&Fs_sf, 32) || isQnan(&Ft_sf, 32)) {\n' 2272686Sksewell@umich.edu code += '\tFCSR = genInvalidVector(FCSR);\n' 2282686Sksewell@umich.edu code += '\treturn NoFault;' 2292686Sksewell@umich.edu code += '}\n else ' 2308588Sgblack@eecs.umich.edu code += 'if (isNan(&Fs_sf, 32) || isNan(&Ft_sf, 32)) {\n' 2318588Sgblack@eecs.umich.edu elif '_df' in cond_code or 'DoublePrecision' in flags: 2322686Sksewell@umich.edu if 'QnanException' in flags: 2338588Sgblack@eecs.umich.edu code += 'if (isQnan(&Fs_df, 64) || isQnan(&Ft_df, 64)) {\n' 2342686Sksewell@umich.edu code += '\tFCSR = genInvalidVector(FCSR);\n' 2352686Sksewell@umich.edu code += '\treturn NoFault;' 2362686Sksewell@umich.edu code += '}\n else ' 2378588Sgblack@eecs.umich.edu code += 'if (isNan(&Fs_df, 64) || isNan(&Ft_df, 64)) {\n' 2382686Sksewell@umich.edu else: 2392686Sksewell@umich.edu sys.exit('Decoder Failed: Can\'t Determine Operand Type\n') 2402686Sksewell@umich.edu 2412686Sksewell@umich.edu if 'UnorderedTrue' in flags: 2422686Sksewell@umich.edu code += 'cond = 1;\n' 2432686Sksewell@umich.edu elif 'UnorderedFalse' in flags: 2442686Sksewell@umich.edu code += 'cond = 0;\n' 2452686Sksewell@umich.edu else: 2462686Sksewell@umich.edu sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n') 2472686Sksewell@umich.edu 2482686Sksewell@umich.edu code += '} else {\n' 2492686Sksewell@umich.edu code += cond_code + '}' 2502686Sksewell@umich.edu code += 'FCSR = genCCVector(FCSR, CC, cond);\n' 2512686Sksewell@umich.edu 2523951Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'FPCompareOp', code) 2532686Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 2542686Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 2552686Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 2562686Sksewell@umich.edu exec_output = BasicExecute.subst(iop) 2572607SN/A}}; 2582607SN/A 2592607SN/Adef format FloatConvertOp(code, *flags) {{ 2602686Sksewell@umich.edu import sys 2612686Sksewell@umich.edu 2622686Sksewell@umich.edu #Determine Source Type 2632686Sksewell@umich.edu convert = 'fpConvert(' 2648588Sgblack@eecs.umich.edu if '_sf' in code: 2652686Sksewell@umich.edu code = 'float ' + code + '\n' 2662686Sksewell@umich.edu convert += 'SINGLE_TO_' 2678588Sgblack@eecs.umich.edu elif '_df' in code: 2682686Sksewell@umich.edu code = 'double ' + code + '\n' 2692686Sksewell@umich.edu convert += 'DOUBLE_TO_' 2709999Sclt67@cornell.edu elif '_sw' in code: 2719999Sclt67@cornell.edu code = 'int32_t ' + code + '\n' 2722686Sksewell@umich.edu convert += 'WORD_TO_' 2739999Sclt67@cornell.edu elif '_sd' in code: 2749999Sclt67@cornell.edu code = 'int64_t ' + code + '\n' 2752686Sksewell@umich.edu convert += 'LONG_TO_' 2762686Sksewell@umich.edu else: 2772686Sksewell@umich.edu sys.exit("Error Determining Source Type for Conversion") 2782686Sksewell@umich.edu 2792686Sksewell@umich.edu #Determine Destination Type 2802686Sksewell@umich.edu if 'ToSingle' in flags: 2818588Sgblack@eecs.umich.edu code += 'Fd_uw = ' + convert + 'SINGLE, ' 2822686Sksewell@umich.edu elif 'ToDouble' in flags: 2838588Sgblack@eecs.umich.edu code += 'Fd_ud = ' + convert + 'DOUBLE, ' 2842686Sksewell@umich.edu elif 'ToWord' in flags: 2858588Sgblack@eecs.umich.edu code += 'Fd_uw = ' + convert + 'WORD, ' 2862686Sksewell@umich.edu elif 'ToLong' in flags: 2878588Sgblack@eecs.umich.edu code += 'Fd_ud = ' + convert + 'LONG, ' 2882686Sksewell@umich.edu else: 2892686Sksewell@umich.edu sys.exit("Error Determining Destination Type for Conversion") 2902686Sksewell@umich.edu 2912686Sksewell@umich.edu #Figure out how to round value 2922686Sksewell@umich.edu if 'Ceil' in flags: 2932686Sksewell@umich.edu code += 'ceil(val)); ' 2942686Sksewell@umich.edu elif 'Floor' in flags: 2952686Sksewell@umich.edu code += 'floor(val)); ' 2962686Sksewell@umich.edu elif 'Round' in flags: 2972686Sksewell@umich.edu code += 'roundFP(val, 0)); ' 2982686Sksewell@umich.edu elif 'Trunc' in flags: 2992686Sksewell@umich.edu code += 'truncFP(val));' 3002686Sksewell@umich.edu else: 3012686Sksewell@umich.edu code += 'val); ' 3022686Sksewell@umich.edu 3033951Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'FPOp', code) 3042686Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 3052686Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 3062686Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 3072686Sksewell@umich.edu exec_output = BasicExecute.subst(iop) 3082686Sksewell@umich.edu}}; 3092686Sksewell@umich.edu 3102686Sksewell@umich.edudef format FloatAccOp(code, *flags) {{ 3113951Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'FPOp', code, flags) 3122607SN/A header_output = BasicDeclare.subst(iop) 3132607SN/A decoder_output = BasicConstructor.subst(iop) 3142607SN/A decode_block = BasicDecode.subst(iop) 3152607SN/A exec_output = BasicExecute.subst(iop) 3162607SN/A}}; 3172607SN/A 3182573SN/A// Primary format for float64 operate instructions: 3192135SN/Adef format Float64Op(code, *flags) {{ 3203951Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags) 3212084SN/A header_output = BasicDeclare.subst(iop) 3222084SN/A decoder_output = BasicConstructor.subst(iop) 3232135SN/A decode_block = BasicDecode.subst(iop) 3242135SN/A exec_output = BasicExecute.subst(iop) 3252038SN/A}}; 3262607SN/A 3272686Sksewell@umich.edudef format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{ 3282686Sksewell@umich.edu import sys 3292686Sksewell@umich.edu 3302686Sksewell@umich.edu code = 'bool cond1, cond2;\n' 3312686Sksewell@umich.edu code += 'bool code_block1, code_block2;\n' 3322686Sksewell@umich.edu code += 'code_block1 = code_block2 = true;\n' 3332686Sksewell@umich.edu 3342686Sksewell@umich.edu if 'QnanException' in flags: 3358588Sgblack@eecs.umich.edu code += 'if (isQnan(&Fs1_sf, 32) || isQnan(&Ft1_sf, 32)) {\n' 3362686Sksewell@umich.edu code += '\tFCSR = genInvalidVector(FCSR);\n' 3372686Sksewell@umich.edu code += 'code_block1 = false;' 3382686Sksewell@umich.edu code += '}\n' 3398588Sgblack@eecs.umich.edu code += 'if (isQnan(&Fs2_sf, 32) || isQnan(&Ft2_sf, 32)) {\n' 3402686Sksewell@umich.edu code += '\tFCSR = genInvalidVector(FCSR);\n' 3412686Sksewell@umich.edu code += 'code_block2 = false;' 3422686Sksewell@umich.edu code += '}\n' 3432686Sksewell@umich.edu 3442686Sksewell@umich.edu code += 'if (code_block1) {' 3458588Sgblack@eecs.umich.edu code += '\tif (isNan(&Fs1_sf, 32) || isNan(&Ft1_sf, 32)) {\n' 3462686Sksewell@umich.edu if 'UnorderedTrue' in flags: 3472686Sksewell@umich.edu code += 'cond1 = 1;\n' 3482686Sksewell@umich.edu elif 'UnorderedFalse' in flags: 3492686Sksewell@umich.edu code += 'cond1 = 0;\n' 3502686Sksewell@umich.edu else: 3512686Sksewell@umich.edu sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n') 3522686Sksewell@umich.edu code += '} else {\n' 3532686Sksewell@umich.edu code += cond_code1 3542686Sksewell@umich.edu code += 'FCSR = genCCVector(FCSR, CC, cond1);}\n}\n' 3552686Sksewell@umich.edu 3562686Sksewell@umich.edu code += 'if (code_block2) {' 3578588Sgblack@eecs.umich.edu code += '\tif (isNan(&Fs2_sf, 32) || isNan(&Ft2_sf, 32)) {\n' 3582686Sksewell@umich.edu if 'UnorderedTrue' in flags: 3592686Sksewell@umich.edu code += 'cond2 = 1;\n' 3602686Sksewell@umich.edu elif 'UnorderedFalse' in flags: 3612686Sksewell@umich.edu code += 'cond2 = 0;\n' 3622686Sksewell@umich.edu else: 3632686Sksewell@umich.edu sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n') 3642686Sksewell@umich.edu code += '} else {\n' 3652686Sksewell@umich.edu code += cond_code2 3662686Sksewell@umich.edu code += 'FCSR = genCCVector(FCSR, CC, cond2);}\n}' 3672686Sksewell@umich.edu 3683951Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'FPCompareOp', code) 3692686Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 3702686Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 3712686Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 3722686Sksewell@umich.edu exec_output = BasicExecute.subst(iop) 3732607SN/A}}; 3742608SN/A 375