dsp.isa revision 5268
19242SN/A// -*- mode:c++ -*- 29242SN/A 39242SN/A// Copyright (c) 2007 MIPS Technologies, Inc. 49242SN/A// All rights reserved. 59242SN/A// 69242SN/A// Redistribution and use in source and binary forms, with or without 711530Sandreas.sandberg@arm.com// modification, are permitted provided that the following conditions are 811530Sandreas.sandberg@arm.com// met: redistributions of source code must retain the above copyright 911530Sandreas.sandberg@arm.com// notice, this list of conditions and the following disclaimer; 1010036SAli.Saidi@ARM.com// redistributions in binary form must reproduce the above copyright 1110036SAli.Saidi@ARM.com// notice, this list of conditions and the following disclaimer in the 1211530Sandreas.sandberg@arm.com// documentation and/or other materials provided with the distribution; 139242SN/A// neither the name of the copyright holders nor the names of its 149242SN/A// contributors may be used to endorse or promote products derived from 1510616Sandreas.hansson@arm.com// this software without specific prior written permission. 1610616Sandreas.hansson@arm.com// 179242SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 189242SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1910616Sandreas.hansson@arm.com// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2010616Sandreas.hansson@arm.com// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 219242SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 229242SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2310616Sandreas.hansson@arm.com// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2410616Sandreas.hansson@arm.com// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2510616Sandreas.hansson@arm.com// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2610616Sandreas.hansson@arm.com// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2711530Sandreas.sandberg@arm.com// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2811530Sandreas.sandberg@arm.com// 2910616Sandreas.hansson@arm.com// Authors: Korey Sewell 3010616Sandreas.hansson@arm.com// Brett Miller 3110616Sandreas.hansson@arm.com 3211530Sandreas.sandberg@arm.com//////////////////////////////////////////////////////////////////// 339729SN/A// 349729SN/A// DSP integer operate instructions 3510616Sandreas.hansson@arm.com// 3610616Sandreas.hansson@arm.comoutput header {{ 3710616Sandreas.hansson@arm.com#include <iostream> 3810616Sandreas.hansson@arm.com using namespace std; 3910616Sandreas.hansson@arm.com /** 4010616Sandreas.hansson@arm.com * Base class for integer operations. 4110616Sandreas.hansson@arm.com */ 4210616Sandreas.hansson@arm.com class DspIntOp : public MipsStaticInst 4310616Sandreas.hansson@arm.com { 4410616Sandreas.hansson@arm.com protected: 4511530Sandreas.sandberg@arm.com 469242SN/A /// Constructor 479242SN/A DspIntOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 489242SN/A MipsStaticInst(mnem, _machInst, __opClass) 499242SN/A { 509242SN/A } 519242SN/A }; 529242SN/A 539242SN/A class DspHiLoOp : public MipsStaticInst 549242SN/A { 559242SN/A protected: 569242SN/A 579242SN/A /// Constructor 589242SN/A DspHiLoOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 599242SN/A MipsStaticInst(mnem, _machInst, __opClass) 609242SN/A { 619242SN/A } 629242SN/A }; 639242SN/A}}; 649242SN/A 659242SN/A// Dsp instruction class execute method template. 669242SN/Adef template DspExecute {{ 679242SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 689242SN/A { 699242SN/A Fault fault = NoFault; 709242SN/A 7110616Sandreas.hansson@arm.com %(op_decl)s; 729242SN/A 739242SN/A if (isDspPresent(xc)) 749242SN/A { 759242SN/A if (isDspEnabled(xc)) 769242SN/A { 779242SN/A %(op_rd)s; 789242SN/A %(code)s; 799242SN/A } 809242SN/A else 819242SN/A { 829242SN/A fault = new DspStateDisabledFault(); 839242SN/A } 849242SN/A } 859242SN/A else 869242SN/A { 879242SN/A fault = new ReservedInstructionFault(); 889242SN/A } 899242SN/A 909242SN/A if(fault == NoFault) 9110616Sandreas.hansson@arm.com { 929242SN/A %(op_wb)s; 939242SN/A } 949242SN/A return fault; 9510616Sandreas.hansson@arm.com } 969242SN/A}}; 979242SN/A 989242SN/A// DspHiLo instruction class execute method template. 999242SN/Adef template DspHiLoExecute {{ 1009242SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1019242SN/A { 1029242SN/A Fault fault = NoFault; 1039242SN/A 1049242SN/A %(op_decl)s; 1059242SN/A 1069242SN/A if (isDspPresent(xc)) 1079242SN/A { 1089242SN/A if (isDspEnabled(xc)) 1099242SN/A { 1109242SN/A %(op_rd)s; 1119242SN/A %(code)s; 1129242SN/A } 1139242SN/A else 1149242SN/A { 1159242SN/A fault = new DspStateDisabledFault(); 1169242SN/A } 1179242SN/A } 1189242SN/A else 1199242SN/A { 1209242SN/A fault = new ReservedInstructionFault(); 1219242SN/A } 1229242SN/A 1239242SN/A if(fault == NoFault) 12410616Sandreas.hansson@arm.com { 12510616Sandreas.hansson@arm.com %(op_wb)s; 12610616Sandreas.hansson@arm.com //If there are 2 Destination Registers then 12710616Sandreas.hansson@arm.com //concatenate the values for the traceData 12810616Sandreas.hansson@arm.com if(traceData && _numDestRegs == 2) { 12910616Sandreas.hansson@arm.com // FIXME - set the trace value correctly here 13010616Sandreas.hansson@arm.com //uint64_t hilo_final_val = (uint64_t)HI_RD_SEL << 32 | LO_RD_SEL; 13110616Sandreas.hansson@arm.com //traceData->setData(hilo_final_val); 13210616Sandreas.hansson@arm.com } 13310616Sandreas.hansson@arm.com } 13410616Sandreas.hansson@arm.com return fault; 13510616Sandreas.hansson@arm.com } 13610616Sandreas.hansson@arm.com}}; 13710616Sandreas.hansson@arm.com 13810616Sandreas.hansson@arm.com//Outputs to decoder.cc 13910616Sandreas.hansson@arm.comoutput decoder {{ 14010616Sandreas.hansson@arm.com}}; 14110616Sandreas.hansson@arm.com 14210616Sandreas.hansson@arm.comoutput exec {{ 14310616Sandreas.hansson@arm.com bool isDspEnabled(%(CPU_exec_context)s *xc) 14410616Sandreas.hansson@arm.com { 14510616Sandreas.hansson@arm.com#if FULL_SYSTEM 14610616Sandreas.hansson@arm.com if( bits( xc->readMiscReg(MipsISA::Status), 24, 24 ) == 0 ) 1479242SN/A return false; 14810616Sandreas.hansson@arm.com#else 14910616Sandreas.hansson@arm.com //printf("Syscall Emulation Mode: isDspEnabled() check defaults to TRUE\n"); 1509242SN/A#endif 15111201Sandreas.hansson@arm.com return true; 15211201Sandreas.hansson@arm.com } 1539242SN/A}}; 1549242SN/A 1559242SN/Aoutput exec {{ 1569242SN/A bool isDspPresent(%(CPU_exec_context)s *xc) 1579242SN/A { 1589242SN/A#if FULL_SYSTEM 1599242SN/A if( bits( xc->readMiscReg(MipsISA::Config3), 10, 10 ) == 0 ) 1609242SN/A return false; 1619242SN/A#else 1629242SN/A //printf("Syscall Emulation Mode: isDspPresent() check defaults to TRUE\n"); 1639242SN/A#endif 1649242SN/A return true; 1659242SN/A } 1669242SN/A}}; 1679242SN/A 16810892Sandreas.hansson@arm.com// add code to fetch the DSPControl register 16911201Sandreas.hansson@arm.com// and write it back after execution, giving 17011201Sandreas.hansson@arm.com// the instruction the opportunity to modify 17111201Sandreas.hansson@arm.com// it if necessary 1729242SN/Adef format DspIntOp(code, *opt_flags) {{ 1739242SN/A 1749242SN/A decl_code = 'uint32_t dspctl;\n' 17510616Sandreas.hansson@arm.com decl_code += 'dspctl = DSPControl;\n' 17611201Sandreas.hansson@arm.com 17711201Sandreas.hansson@arm.com write_code = 'DSPControl = dspctl;\n' 17810616Sandreas.hansson@arm.com 1799242SN/A code = decl_code + code + write_code 1809242SN/A 1819242SN/A opt_flags += ('IsDspOp',) 1829242SN/A 1839242SN/A iop = InstObjParams(name, Name, 'DspIntOp', code, opt_flags) 1849242SN/A header_output = BasicDeclare.subst(iop) 1859242SN/A decoder_output = BasicConstructor.subst(iop) 1869242SN/A decode_block = BasicDecode.subst(iop) 1879242SN/A exec_output = DspExecute.subst(iop) 1889242SN/A}}; 1899242SN/A 1909242SN/A// add code to fetch the DSPControl register 1919242SN/A// and write it back after execution, giving 1929242SN/A// the instruction the opportunity to modify 19310892Sandreas.hansson@arm.com// it if necessary; also, fetch the appropriate 19411201Sandreas.hansson@arm.com// HI/LO register pair, based on the AC 19511201Sandreas.hansson@arm.com// instruction field. 19611201Sandreas.hansson@arm.com 19711201Sandreas.hansson@arm.comdef format DspHiLoOp(code, *opt_flags) {{ 19811201Sandreas.hansson@arm.com 19910616Sandreas.hansson@arm.com decl_code = 'int64_t dspac;\n' 2009242SN/A decl_code += 'uint32_t dspctl;\n' 2019242SN/A 2029242SN/A fetch_code = 'dspctl = DSPControl;\n' 2039242SN/A fetch_code += 'dspac = HI_RD_SEL;\n' 2049242SN/A fetch_code += 'dspac = dspac << 32 | LO_RD_SEL;\n' 2059242SN/A 2069242SN/A write_code = 'DSPControl = dspctl;\n' 2079242SN/A write_code += 'HI_RD_SEL = dspac<63:32>;\n' 2089242SN/A write_code += 'LO_RD_SEL = dspac<31:0>;\n' 2099242SN/A 2109242SN/A code = decl_code + fetch_code + code + write_code 2119242SN/A 2129242SN/A opt_flags += ('IsDspOp',) 2139242SN/A 2149242SN/A iop = InstObjParams(name, Name, 'DspHiLoOp', code, opt_flags) 2159242SN/A header_output = BasicDeclare.subst(iop) 2169242SN/A decoder_output = BasicConstructor.subst(iop) 2179242SN/A decode_block = BasicDecode.subst(iop) 2189242SN/A exec_output = DspHiLoExecute.subst(iop) 2199242SN/A 2209242SN/A}}; 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