faults.cc revision 8573
12SN/A/* 21762SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32SN/A * Copyright (c) 2007 MIPS Technologies, Inc. 42SN/A * All rights reserved. 52SN/A * 62SN/A * Redistribution and use in source and binary forms, with or without 72SN/A * modification, are permitted provided that the following conditions are 82SN/A * met: redistributions of source code must retain the above copyright 92SN/A * notice, this list of conditions and the following disclaimer; 102SN/A * redistributions in binary form must reproduce the above copyright 112SN/A * notice, this list of conditions and the following disclaimer in the 122SN/A * documentation and/or other materials provided with the distribution; 132SN/A * neither the name of the copyright holders nor the names of its 142SN/A * contributors may be used to endorse or promote products derived from 152SN/A * this software without specific prior written permission. 162SN/A * 172SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272665Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 292665Ssaidi@eecs.umich.edu * Authors: Gabe Black 302665Ssaidi@eecs.umich.edu * Korey Sewell 312SN/A * Jaidev Patwardhan 322SN/A */ 332SN/A 342SN/A#include "arch/mips/faults.hh" 352SN/A#include "arch/mips/pra_constants.hh" 362655Sstever@eecs.umich.edu#include "base/trace.hh" 372655Sstever@eecs.umich.edu#include "cpu/base.hh" 382SN/A#include "cpu/thread_context.hh" 392SN/A#include "debug/MipsPRA.hh" 401399SN/A 411396SN/A#if !FULL_SYSTEM 422SN/A#include "mem/page_table.hh" 432SN/A#include "sim/process.hh" 442729Ssaidi@eecs.umich.edu#endif 452SN/A 461310SN/Anamespace MipsISA 472SN/A{ 482SN/A 492SN/Atypedef MipsFaultBase::FaultVals FaultVals; 502667Sstever@eecs.umich.edu 5156SN/Atemplate <> FaultVals MipsFault<MachineCheckFault>::vals = 52146SN/A { "Machine Check", 0x0401 }; 531388SN/A 5456SN/Atemplate <> FaultVals MipsFault<ResetFault>::vals = 5556SN/A#if FULL_SYSTEM 561311SN/A { "Reset Fault", 0xBFC00000}; 57400SN/A#else 581717SN/A { "Reset Fault", 0x001}; 591717SN/A#endif 602738Sstever@eecs.umich.edu 612738Sstever@eecs.umich.edutemplate <> FaultVals MipsFault<AddressErrorFault>::vals = 62146SN/A { "Address Error", 0x0180 }; 63146SN/A 64146SN/Atemplate <> FaultVals MipsFault<SystemCallFault>::vals = 6556SN/A { "Syscall", 0x0180 }; 6656SN/A 6756SN/Atemplate <> FaultVals MipsFault<CoprocessorUnusableFault>::vals = 68695SN/A { "Coprocessor Unusable Fault", 0x180 }; 69695SN/A 701696SN/Atemplate <> FaultVals MipsFault<ReservedInstructionFault>::vals = 712SN/A { "Reserved Instruction Fault", 0x0180 }; 722SN/A 732SN/Atemplate <> FaultVals MipsFault<ThreadFault>::vals = 742SN/A { "Thread Fault", 0x00F1 }; 752SN/A 762SN/Atemplate <> FaultVals MipsFault<IntegerOverflowFault>::vals = 77329SN/A { "Integer Overflow Exception", 0x180 }; 782SN/A 792SN/Atemplate <> FaultVals MipsFault<InterruptFault>::vals = 802SN/A { "interrupt", 0x0180 }; 812SN/A 822SN/Atemplate <> FaultVals MipsFault<TrapFault>::vals = 832SN/A { "Trap", 0x0180 }; 842SN/A 852SN/Atemplate <> FaultVals MipsFault<BreakpointFault>::vals = 862SN/A { "Breakpoint", 0x0180 }; 872SN/A 882SN/Atemplate <> FaultVals MipsFault<TlbInvalidFault>::vals = 892SN/A { "Invalid TLB Entry Exception", 0x0180 }; 90329SN/A 91329SN/Atemplate <> FaultVals MipsFault<TlbRefillFault>::vals = 92329SN/A { "TLB Refill Exception", 0x0180 }; 93329SN/A 94329SN/Atemplate <> FaultVals MipsFault<TLBModifiedFault>::vals = 95329SN/A { "TLB Modified Exception", 0x0180 }; 96329SN/A 972SN/Atemplate <> FaultVals MipsFault<DspStateDisabledFault>::vals = 982SN/A { "DSP Disabled Fault", 0x001a }; 992SN/A 1002SN/A#if FULL_SYSTEM 1012SN/Avoid 1022SN/AMipsFaultBase::setHandlerPC(Addr HandlerBase, ThreadContext *tc) 1032SN/A{ 1042SN/A tc->setPC(HandlerBase); 105764SN/A tc->setNextPC(HandlerBase + sizeof(MachInst)); 106764SN/A tc->setNextNPC(HandlerBase + 2 * sizeof(MachInst)); 107764SN/A} 108764SN/A 109764SN/Avoid 110764SN/AMipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode) 111764SN/A{ 112764SN/A // modify SRS Ctl - Save CSS, put ESS into CSS 113764SN/A StatusReg status = tc->readMiscReg(MISCREG_STATUS); 114764SN/A if (status.exl != 1 && status.bev != 1) { 115764SN/A // SRS Ctl is modified only if Status_EXL and Status_BEV are not set 116764SN/A SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL); 1172729Ssaidi@eecs.umich.edu srsCtl.pss = srsCtl.css; 1182729Ssaidi@eecs.umich.edu srsCtl.css = srsCtl.ess; 1192729Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_SRSCTL, srsCtl); 1202729Ssaidi@eecs.umich.edu } 1212729Ssaidi@eecs.umich.edu 1222729Ssaidi@eecs.umich.edu // set EXL bit (don't care if it is already set!) 1232729Ssaidi@eecs.umich.edu status.exl = 1; 1242729Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_STATUS, status); 1252729Ssaidi@eecs.umich.edu 1262729Ssaidi@eecs.umich.edu // write EPC 1272729Ssaidi@eecs.umich.edu // CHECK ME or FIXME or FIX ME or POSSIBLE HACK 1282729Ssaidi@eecs.umich.edu // Check to see if the exception occurred in the branch delay slot 1292729Ssaidi@eecs.umich.edu DPRINTF(MipsPRA, "PC: %x, NextPC: %x, NNPC: %x\n", 1302729Ssaidi@eecs.umich.edu tc->readPC(), tc->readNextPC(), tc->readNextNPC()); 1312729Ssaidi@eecs.umich.edu int bd = 0; 1322729Ssaidi@eecs.umich.edu if (tc->readPC() + sizeof(MachInst) != tc->readNextPC()) { 1332729Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_EPC, tc->readPC() - sizeof(MachInst)); 1342729Ssaidi@eecs.umich.edu // In the branch delay slot? set CAUSE_31 1352729Ssaidi@eecs.umich.edu bd = 1; 1362729Ssaidi@eecs.umich.edu } else { 1372729Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_EPC, tc->readPC()); 1382729Ssaidi@eecs.umich.edu // In the branch delay slot? reset CAUSE_31 1392729Ssaidi@eecs.umich.edu bd = 0; 1402729Ssaidi@eecs.umich.edu } 1412729Ssaidi@eecs.umich.edu 1422SN/A // Set Cause_EXCCODE field 1432667Sstever@eecs.umich.edu CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); 1442667Sstever@eecs.umich.edu cause.excCode = excCode; 1452667Sstever@eecs.umich.edu cause.bd = bd; 1462667Sstever@eecs.umich.edu cause.ce = 0; 1472667Sstever@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CAUSE, cause); 1482667Sstever@eecs.umich.edu} 1491388SN/A 1502667Sstever@eecs.umich.eduvoid 1512SN/AIntegerOverflowFault::invoke(ThreadContext *tc, StaticInstPtr inst) 1522667Sstever@eecs.umich.edu{ 1532SN/A DPRINTF(MipsPRA, "%s encountered.\n", name()); 1542667Sstever@eecs.umich.edu setExceptionState(tc, 0xC); 1552667Sstever@eecs.umich.edu 1562667Sstever@eecs.umich.edu // Set new PC 1572667Sstever@eecs.umich.edu Addr HandlerBase; 1582667Sstever@eecs.umich.edu StatusReg status = tc->readMiscReg(MISCREG_STATUS); 1592SN/A // Here, the handler is dependent on BEV, which is not modified by 1602667Sstever@eecs.umich.edu // setExceptionState() 1612667Sstever@eecs.umich.edu if (!status.bev) { 1622667Sstever@eecs.umich.edu // See MIPS ARM Vol 3, Revision 2, Page 38 1632SN/A HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 1642667Sstever@eecs.umich.edu } else { 1652667Sstever@eecs.umich.edu HandlerBase = 0xBFC00200; 1662667Sstever@eecs.umich.edu } 1672SN/A setHandlerPC(HandlerBase, tc); 1682SN/A} 1692667Sstever@eecs.umich.edu 1702SN/Avoid 1712SN/ATrapFault::invoke(ThreadContext *tc, StaticInstPtr inst) 1722SN/A{ 1732SN/A DPRINTF(MipsPRA, "%s encountered.\n", name()); 1742729Ssaidi@eecs.umich.edu setExceptionState(tc, 0xD); 1752729Ssaidi@eecs.umich.edu 1762729Ssaidi@eecs.umich.edu // Set new PC 1772667Sstever@eecs.umich.edu Addr HandlerBase; 1782SN/A // Offset 0x180 - General Exception Vector 1792SN/A HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 1802SN/A setHandlerPC(HandlerBase, tc); 181329SN/A} 182329SN/A 183329SN/Avoid 184764SN/ABreakpointFault::invoke(ThreadContext *tc, StaticInstPtr inst) 1852SN/A{ 1862655Sstever@eecs.umich.edu setExceptionState(tc, 0x9); 1872667Sstever@eecs.umich.edu 1882667Sstever@eecs.umich.edu // Set new PC 1892667Sstever@eecs.umich.edu Addr HandlerBase; 1902667Sstever@eecs.umich.edu // Offset 0x180 - General Exception Vector 1912667Sstever@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 1922667Sstever@eecs.umich.edu setHandlerPC(HandlerBase, tc); 1932729Ssaidi@eecs.umich.edu} 1942667Sstever@eecs.umich.edu 1952729Ssaidi@eecs.umich.eduvoid 1962729Ssaidi@eecs.umich.eduTlbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst) 1972729Ssaidi@eecs.umich.edu{ 1982729Ssaidi@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 1992729Ssaidi@eecs.umich.edu setExceptionState(tc, store ? 0x3 : 0x2); 2002729Ssaidi@eecs.umich.edu 2012729Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); 2022729Ssaidi@eecs.umich.edu EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); 2032729Ssaidi@eecs.umich.edu entryHi.asid = entryHiAsid; 2042667Sstever@eecs.umich.edu entryHi.vpn2 = entryHiVPN2; 2052729Ssaidi@eecs.umich.edu entryHi.vpn2x = entryHiVPN2X; 2062667Sstever@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi); 2072667Sstever@eecs.umich.edu 2082667Sstever@eecs.umich.edu ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); 2092667Sstever@eecs.umich.edu context.badVPN2 = contextBadVPN2; 2102667Sstever@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CONTEXT, context); 2112667Sstever@eecs.umich.edu 2122667Sstever@eecs.umich.edu // Set new PC 2132667Sstever@eecs.umich.edu Addr HandlerBase; 2142667Sstever@eecs.umich.edu // Offset 0x180 - General Exception Vector 2152667Sstever@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 2162667Sstever@eecs.umich.edu setHandlerPC(HandlerBase, tc); 2172667Sstever@eecs.umich.edu} 2182667Sstever@eecs.umich.edu 2192667Sstever@eecs.umich.eduvoid 2202667Sstever@eecs.umich.eduAddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst) 2212667Sstever@eecs.umich.edu{ 2222729Ssaidi@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 2232729Ssaidi@eecs.umich.edu setExceptionState(tc, store ? 0x5 : 0x4); 2242729Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr); 2252667Sstever@eecs.umich.edu 2262667Sstever@eecs.umich.edu // Set new PC 2272667Sstever@eecs.umich.edu Addr HandlerBase; 2282667Sstever@eecs.umich.edu // Offset 0x180 - General Exception Vector 2292667Sstever@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 2302667Sstever@eecs.umich.edu setHandlerPC(HandlerBase, tc); 2312667Sstever@eecs.umich.edu} 2322667Sstever@eecs.umich.edu 2332667Sstever@eecs.umich.eduvoid 2342729Ssaidi@eecs.umich.eduTlbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst) 2352729Ssaidi@eecs.umich.edu{ 2362729Ssaidi@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), MISCREG_BADVADDR); 2372729Ssaidi@eecs.umich.edu setExceptionState(tc, store ? 0x3 : 0x2); 2382729Ssaidi@eecs.umich.edu 2392667Sstever@eecs.umich.edu Addr HandlerBase; 2402667Sstever@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); 2412667Sstever@eecs.umich.edu EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); 2422667Sstever@eecs.umich.edu entryHi.asid = entryHiAsid; 2432667Sstever@eecs.umich.edu entryHi.vpn2 = entryHiVPN2; 2442667Sstever@eecs.umich.edu entryHi.vpn2x = entryHiVPN2X; 2452667Sstever@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi); 2462667Sstever@eecs.umich.edu ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); 2472667Sstever@eecs.umich.edu context.badVPN2 = contextBadVPN2; 2482667Sstever@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CONTEXT, context); 2492667Sstever@eecs.umich.edu 2502667Sstever@eecs.umich.edu StatusReg status = tc->readMiscReg(MISCREG_STATUS); 2512667Sstever@eecs.umich.edu // Since handler depends on EXL bit, must check EXL bit before setting it!! 2522667Sstever@eecs.umich.edu // See MIPS ARM Vol 3, Revision 2, Page 38 2532667Sstever@eecs.umich.edu if (status.exl == 1) { 2542667Sstever@eecs.umich.edu // Offset 0x180 - General Exception Vector 2552667Sstever@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 2562667Sstever@eecs.umich.edu } else { 2572667Sstever@eecs.umich.edu // Offset 0x000 2582655Sstever@eecs.umich.edu HandlerBase = tc->readMiscReg(MISCREG_EBASE); 2592655Sstever@eecs.umich.edu } 2601311SN/A setHandlerPC(HandlerBase, tc); 2612667Sstever@eecs.umich.edu} 2622667Sstever@eecs.umich.edu 2631703SN/Avoid 2642667Sstever@eecs.umich.eduTLBModifiedFault::invoke(ThreadContext *tc, StaticInstPtr inst) 2652667Sstever@eecs.umich.edu{ 2662667Sstever@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 2672667Sstever@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); 2682667Sstever@eecs.umich.edu EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); 2692667Sstever@eecs.umich.edu entryHi.asid = entryHiAsid; 2702667Sstever@eecs.umich.edu entryHi.vpn2 = entryHiVPN2; 2712667Sstever@eecs.umich.edu entryHi.vpn2x = entryHiVPN2X; 2721703SN/A tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi); 2732667Sstever@eecs.umich.edu 2742667Sstever@eecs.umich.edu ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); 2752667Sstever@eecs.umich.edu context.badVPN2 = contextBadVPN2; 2762667Sstever@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CONTEXT, context); 2772667Sstever@eecs.umich.edu 2782SN/A // Set new PC 2792667Sstever@eecs.umich.edu Addr HandlerBase; 2802667Sstever@eecs.umich.edu // Offset 0x180 - General Exception Vector 2812667Sstever@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 2822667Sstever@eecs.umich.edu setExceptionState(tc, 0x1); 2832667Sstever@eecs.umich.edu setHandlerPC(HandlerBase, tc); 2842667Sstever@eecs.umich.edu 2852667Sstever@eecs.umich.edu} 2862667Sstever@eecs.umich.edu 2872667Sstever@eecs.umich.eduvoid 2882667Sstever@eecs.umich.eduSystemCallFault::invoke(ThreadContext *tc, StaticInstPtr inst) 2892667Sstever@eecs.umich.edu{ 2902667Sstever@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 2912667Sstever@eecs.umich.edu setExceptionState(tc, 0x8); 2922667Sstever@eecs.umich.edu 2932667Sstever@eecs.umich.edu // Set new PC 2942667Sstever@eecs.umich.edu Addr HandlerBase; 2952667Sstever@eecs.umich.edu // Offset 0x180 - General Exception Vector 2962667Sstever@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 2972655Sstever@eecs.umich.edu setHandlerPC(HandlerBase, tc); 2982667Sstever@eecs.umich.edu} 2991388SN/A 3002738Sstever@eecs.umich.eduvoid 3012667Sstever@eecs.umich.eduInterruptFault::invoke(ThreadContext *tc, StaticInstPtr inst) 3022738Sstever@eecs.umich.edu{ 3032738Sstever@eecs.umich.edu#if FULL_SYSTEM 3042738Sstever@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 3052738Sstever@eecs.umich.edu setExceptionState(tc, 0x0A); 3062738Sstever@eecs.umich.edu Addr HandlerBase; 3072738Sstever@eecs.umich.edu 3082738Sstever@eecs.umich.edu CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); 3092738Sstever@eecs.umich.edu if (cause.iv) { 3102738Sstever@eecs.umich.edu // Offset 200 for release 2 3112738Sstever@eecs.umich.edu HandlerBase = 0x20 + vect() + tc->readMiscRegNoEffect(MISCREG_EBASE); 3122738Sstever@eecs.umich.edu } else { 3132738Sstever@eecs.umich.edu //Ofset at 180 for release 1 3142738Sstever@eecs.umich.edu HandlerBase = vect() + tc->readMiscRegNoEffect(MISCREG_EBASE); 3152738Sstever@eecs.umich.edu } 3162738Sstever@eecs.umich.edu 3172738Sstever@eecs.umich.edu setHandlerPC(HandlerBase, tc); 3182738Sstever@eecs.umich.edu#endif 3192738Sstever@eecs.umich.edu} 3202738Sstever@eecs.umich.edu 3212738Sstever@eecs.umich.edu#endif // FULL_SYSTEM 3222738Sstever@eecs.umich.edu 3232738Sstever@eecs.umich.eduvoid 3242738Sstever@eecs.umich.eduResetFault::invoke(ThreadContext *tc, StaticInstPtr inst) 3252738Sstever@eecs.umich.edu{ 3262738Sstever@eecs.umich.edu#if FULL_SYSTEM 3272738Sstever@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 3282738Sstever@eecs.umich.edu /* All reset activity must be invoked from here */ 3292738Sstever@eecs.umich.edu tc->setPC(vect()); 3302738Sstever@eecs.umich.edu tc->setNextPC(vect() + sizeof(MachInst)); 3312738Sstever@eecs.umich.edu tc->setNextNPC(vect() + sizeof(MachInst) + sizeof(MachInst)); 3322738Sstever@eecs.umich.edu DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", tc->readPC()); 3332738Sstever@eecs.umich.edu#endif 3342738Sstever@eecs.umich.edu 3352738Sstever@eecs.umich.edu // Set Coprocessor 1 (Floating Point) To Usable 3362738Sstever@eecs.umich.edu StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS); 3372738Sstever@eecs.umich.edu status.cu.cu1 = 1; 3382738Sstever@eecs.umich.edu tc->setMiscReg(MISCREG_STATUS, status); 3392738Sstever@eecs.umich.edu} 3402738Sstever@eecs.umich.edu 3412738Sstever@eecs.umich.eduvoid 3422667Sstever@eecs.umich.eduReservedInstructionFault::invoke(ThreadContext *tc, StaticInstPtr inst) 3432738Sstever@eecs.umich.edu{ 3442667Sstever@eecs.umich.edu#if FULL_SYSTEM 3452738Sstever@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 3462655Sstever@eecs.umich.edu setExceptionState(tc, 0x0A); 3471388SN/A Addr HandlerBase; 3482SN/A // Offset 0x180 - General Exception Vector 3492655Sstever@eecs.umich.edu HandlerBase = vect() + tc->readMiscRegNoEffect(MISCREG_EBASE); 3502SN/A setHandlerPC(HandlerBase, tc); 3511388SN/A#else 3521388SN/A panic("%s encountered.\n", name()); 3532738Sstever@eecs.umich.edu#endif 3542SN/A} 3551310SN/A 3562738Sstever@eecs.umich.eduvoid 3572738Sstever@eecs.umich.eduThreadFault::invoke(ThreadContext *tc, StaticInstPtr inst) 3582738Sstever@eecs.umich.edu{ 3592738Sstever@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 3602738Sstever@eecs.umich.edu panic("%s encountered.\n", name()); 3612738Sstever@eecs.umich.edu} 3622738Sstever@eecs.umich.edu 3632738Sstever@eecs.umich.eduvoid 3642738Sstever@eecs.umich.eduDspStateDisabledFault::invoke(ThreadContext *tc, StaticInstPtr inst) 3652738Sstever@eecs.umich.edu{ 3662738Sstever@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 3672738Sstever@eecs.umich.edu panic("%s encountered.\n", name()); 3682738Sstever@eecs.umich.edu} 3692738Sstever@eecs.umich.edu 3702738Sstever@eecs.umich.eduvoid 3712738Sstever@eecs.umich.eduCoprocessorUnusableFault::invoke(ThreadContext *tc, StaticInstPtr inst) 3722738Sstever@eecs.umich.edu{ 3732738Sstever@eecs.umich.edu#if FULL_SYSTEM 3742738Sstever@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 3752738Sstever@eecs.umich.edu setExceptionState(tc, 0xb); 3762738Sstever@eecs.umich.edu // The ID of the coprocessor causing the exception is stored in 3772738Sstever@eecs.umich.edu // CoprocessorUnusableFault::coProcID 3782738Sstever@eecs.umich.edu CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); 3792738Sstever@eecs.umich.edu cause.ce = coProcID; 3802738Sstever@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CAUSE, cause); 3812738Sstever@eecs.umich.edu 3822738Sstever@eecs.umich.edu Addr HandlerBase; 3832738Sstever@eecs.umich.edu // Offset 0x180 - General Exception Vector 3842738Sstever@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 3852738Sstever@eecs.umich.edu setHandlerPC(HandlerBase, tc); 3862738Sstever@eecs.umich.edu 3872738Sstever@eecs.umich.edu#else 3882738Sstever@eecs.umich.edu warn("%s (CP%d) encountered.\n", name(), coProcID); 3892738Sstever@eecs.umich.edu#endif 3902738Sstever@eecs.umich.edu} 3912738Sstever@eecs.umich.edu 3922738Sstever@eecs.umich.edu} // namespace MipsISA 3932738Sstever@eecs.umich.edu 3942738Sstever@eecs.umich.edu