faults.cc revision 6378:4a2ff62c3b4f 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 *          Korey Sewell
31 *          Jaidev Patwardhan
32 */
33
34#include "arch/mips/faults.hh"
35#include "cpu/thread_context.hh"
36#include "cpu/base.hh"
37#include "base/trace.hh"
38#include "arch/mips/pra_constants.hh"
39#if !FULL_SYSTEM
40#include "sim/process.hh"
41#include "mem/page_table.hh"
42#endif
43
44namespace MipsISA
45{
46
47FaultName MachineCheckFault::_name = "Machine Check";
48FaultVect MachineCheckFault::_vect = 0x0401;
49FaultStat MachineCheckFault::_count;
50
51FaultName AlignmentFault::_name = "Alignment";
52FaultVect AlignmentFault::_vect = 0x0301;
53FaultStat AlignmentFault::_count;
54
55FaultName ResetFault::_name = "Reset Fault";
56#if  FULL_SYSTEM
57FaultVect ResetFault::_vect = 0xBFC00000;
58#else
59FaultVect ResetFault::_vect = 0x001;
60#endif
61FaultStat ResetFault::_count;
62
63FaultName AddressErrorFault::_name = "Address Error";
64FaultVect AddressErrorFault::_vect = 0x0180;
65FaultStat AddressErrorFault::_count;
66
67FaultName StoreAddressErrorFault::_name = "Store Address Error";
68FaultVect StoreAddressErrorFault::_vect = 0x0180;
69FaultStat StoreAddressErrorFault::_count;
70
71
72FaultName SystemCallFault::_name = "Syscall";
73FaultVect SystemCallFault::_vect = 0x0180;
74FaultStat SystemCallFault::_count;
75
76FaultName CoprocessorUnusableFault::_name = "Coprocessor Unusable Fault";
77FaultVect CoprocessorUnusableFault::_vect = 0x180;
78FaultStat CoprocessorUnusableFault::_count;
79
80FaultName ReservedInstructionFault::_name = "Reserved Instruction Fault";
81FaultVect ReservedInstructionFault::_vect = 0x0180;
82FaultStat ReservedInstructionFault::_count;
83
84FaultName ThreadFault::_name = "Thread Fault";
85FaultVect ThreadFault::_vect = 0x00F1;
86FaultStat ThreadFault::_count;
87
88FaultName ArithmeticFault::_name = "Arithmetic Overflow Exception";
89FaultVect ArithmeticFault::_vect = 0x180;
90FaultStat ArithmeticFault::_count;
91
92FaultName UnimplementedOpcodeFault::_name = "opdec";
93FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
94FaultStat UnimplementedOpcodeFault::_count;
95
96FaultName InterruptFault::_name = "interrupt";
97FaultVect InterruptFault::_vect = 0x0180;
98FaultStat InterruptFault::_count;
99
100FaultName TrapFault::_name = "Trap";
101FaultVect TrapFault::_vect = 0x0180;
102FaultStat TrapFault::_count;
103
104FaultName BreakpointFault::_name = "Breakpoint";
105FaultVect BreakpointFault::_vect = 0x0180;
106FaultStat BreakpointFault::_count;
107
108FaultName ItbInvalidFault::_name = "Invalid TLB Entry Exception (I-Fetch/LW)";
109FaultVect ItbInvalidFault::_vect = 0x0180;
110FaultStat ItbInvalidFault::_count;
111
112FaultName ItbPageFault::_name = "itbmiss";
113FaultVect ItbPageFault::_vect = 0x0181;
114FaultStat ItbPageFault::_count;
115
116FaultName ItbMissFault::_name = "itbmiss";
117FaultVect ItbMissFault::_vect = 0x0181;
118FaultStat ItbMissFault::_count;
119
120FaultName ItbAcvFault::_name = "iaccvio";
121FaultVect ItbAcvFault::_vect = 0x0081;
122FaultStat ItbAcvFault::_count;
123
124FaultName ItbRefillFault::_name = "TLB Refill Exception (I-Fetch/LW)";
125FaultVect ItbRefillFault::_vect = 0x0180;
126FaultStat ItbRefillFault::_count;
127
128FaultName NDtbMissFault::_name = "dtb_miss_single";
129FaultVect NDtbMissFault::_vect = 0x0201;
130FaultStat NDtbMissFault::_count;
131
132FaultName PDtbMissFault::_name = "dtb_miss_double";
133FaultVect PDtbMissFault::_vect = 0x0281;
134FaultStat PDtbMissFault::_count;
135
136FaultName DtbPageFault::_name = "dfault";
137FaultVect DtbPageFault::_vect = 0x0381;
138FaultStat DtbPageFault::_count;
139
140FaultName DtbAcvFault::_name = "dfault";
141FaultVect DtbAcvFault::_vect = 0x0381;
142FaultStat DtbAcvFault::_count;
143
144FaultName DtbInvalidFault::_name = "Invalid TLB Entry Exception (Store)";
145FaultVect DtbInvalidFault::_vect = 0x0180;
146FaultStat DtbInvalidFault::_count;
147
148FaultName DtbRefillFault::_name = "TLB Refill Exception (Store)";
149FaultVect DtbRefillFault::_vect = 0x0180;
150FaultStat DtbRefillFault::_count;
151
152FaultName TLBModifiedFault::_name = "TLB Modified Exception";
153FaultVect TLBModifiedFault::_vect = 0x0180;
154FaultStat TLBModifiedFault::_count;
155
156FaultName FloatEnableFault::_name = "float_enable_fault";
157FaultVect FloatEnableFault::_vect = 0x0581;
158FaultStat FloatEnableFault::_count;
159
160FaultName IntegerOverflowFault::_name = "Integer Overflow Fault";
161FaultVect IntegerOverflowFault::_vect = 0x0501;
162FaultStat IntegerOverflowFault::_count;
163
164FaultName DspStateDisabledFault::_name = "DSP Disabled Fault";
165FaultVect DspStateDisabledFault::_vect = 0x001a;
166FaultStat DspStateDisabledFault::_count;
167
168#if FULL_SYSTEM
169void
170MipsFault::setHandlerPC(Addr HandlerBase, ThreadContext *tc)
171{
172    tc->setPC(HandlerBase);
173    tc->setNextPC(HandlerBase + sizeof(MachInst));
174    tc->setNextNPC(HandlerBase + 2 * sizeof(MachInst));
175}
176
177void
178MipsFault::setExceptionState(ThreadContext *tc, uint8_t ExcCode)
179{
180    // modify SRS Ctl - Save CSS, put ESS into CSS
181    MiscReg stat = tc->readMiscReg(MipsISA::Status);
182    if (bits(stat, Status_EXL) != 1 && bits(stat, Status_BEV) != 1) {
183        // SRS Ctl is modified only if Status_EXL and Status_BEV are not set
184        MiscReg srs = tc->readMiscReg(MipsISA::SRSCtl);
185        uint8_t CSS, ESS;
186        CSS = bits(srs, SRSCtl_CSS_HI, SRSCtl_CSS_LO);
187        ESS = bits(srs, SRSCtl_ESS_HI, SRSCtl_ESS_LO);
188        // Move CSS to PSS
189        replaceBits(srs, SRSCtl_PSS_HI, SRSCtl_PSS_LO, CSS);
190        // Move ESS to CSS
191        replaceBits(srs, SRSCtl_CSS_HI, SRSCtl_CSS_LO, ESS);
192        tc->setMiscRegNoEffect(MipsISA::SRSCtl, srs);
193    }
194
195    // set EXL bit (don't care if it is already set!)
196    replaceBits(stat, Status_EXL_HI, Status_EXL_LO, 1);
197    tc->setMiscRegNoEffect(MipsISA::Status, stat);
198
199    // write EPC
200    // CHECK ME  or FIXME or FIX ME or POSSIBLE HACK
201    // Check to see if the exception occurred in the branch delay slot
202    DPRINTF(MipsPRA, "PC: %x, NextPC: %x, NNPC: %x\n",
203            tc->readPC(), tc->readNextPC(), tc->readNextNPC());
204    int C_BD = 0;
205    if (tc->readPC() + sizeof(MachInst) != tc->readNextPC()) {
206        tc->setMiscRegNoEffect(MipsISA::EPC, tc->readPC() - sizeof(MachInst));
207        // In the branch delay slot? set CAUSE_31
208        C_BD = 1;
209    } else {
210        tc->setMiscRegNoEffect(MipsISA::EPC, tc->readPC());
211        // In the branch delay slot? reset CAUSE_31
212        C_BD = 0;
213    }
214
215    // Set Cause_EXCCODE field
216    MiscReg cause = tc->readMiscReg(MipsISA::Cause);
217    replaceBits(cause, Cause_EXCCODE_HI, Cause_EXCCODE_LO, ExcCode);
218    replaceBits(cause, Cause_BD_HI, Cause_BD_LO,C_BD);
219    replaceBits(cause, Cause_CE_HI, Cause_CE_LO,0);
220    tc->setMiscRegNoEffect(MipsISA::Cause, cause);
221}
222
223void
224ArithmeticFault::invoke(ThreadContext *tc)
225{
226    DPRINTF(MipsPRA, "%s encountered.\n", name());
227    setExceptionState(tc, 0xC);
228
229    // Set new PC
230    Addr HandlerBase;
231    MiscReg stat = tc->readMiscReg(MipsISA::Status);
232    // Here, the handler is dependent on BEV, which is not modified by
233    // setExceptionState()
234    if (bits(stat, Status_BEV) == 0 ) {
235        // See MIPS ARM Vol 3, Revision 2, Page 38
236        HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
237    } else {
238        HandlerBase = 0xBFC00200;
239    }
240    setHandlerPC(HandlerBase, tc);
241}
242
243void
244StoreAddressErrorFault::invoke(ThreadContext *tc)
245{
246    DPRINTF(MipsPRA, "%s encountered.\n", name());
247    setExceptionState(tc, 0x5);
248    tc->setMiscRegNoEffect(MipsISA::BadVAddr, BadVAddr);
249
250    // Set new PC
251    Addr HandlerBase;
252    // Offset 0x180 - General Exception Vector
253    HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
254    setHandlerPC(HandlerBase, tc);
255}
256
257void
258TrapFault::invoke(ThreadContext *tc)
259{
260    DPRINTF(MipsPRA, "%s encountered.\n", name());
261    setExceptionState(tc, 0xD);
262
263    // Set new PC
264    Addr HandlerBase;
265    // Offset 0x180 - General Exception Vector
266    HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
267    setHandlerPC(HandlerBase, tc);
268}
269
270void
271BreakpointFault::invoke(ThreadContext *tc)
272{
273    setExceptionState(tc, 0x9);
274
275    // Set new PC
276    Addr HandlerBase;
277    // Offset 0x180 - General Exception Vector
278    HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
279    setHandlerPC(HandlerBase, tc);
280}
281
282void
283DtbInvalidFault::invoke(ThreadContext *tc)
284{
285    DPRINTF(MipsPRA, "%s encountered.\n", name());
286
287    tc->setMiscRegNoEffect(MipsISA::BadVAddr, BadVAddr);
288    MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
289    replaceBits(eh, EntryHi_ASID_HI, EntryHi_ASID_LO, EntryHi_Asid);
290    replaceBits(eh, EntryHi_VPN2_HI, EntryHi_VPN2_LO, EntryHi_VPN2);
291    replaceBits(eh, EntryHi_VPN2X_HI, EntryHi_VPN2X_LO, EntryHi_VPN2X);
292    tc->setMiscRegNoEffect(MipsISA::EntryHi, eh);
293    MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
294    replaceBits(ctxt, Context_BadVPN2_HI, Context_BadVPN2_LO, Context_BadVPN2);
295    tc->setMiscRegNoEffect(MipsISA::Context, ctxt);
296    setExceptionState(tc, 0x3);
297
298
299    // Set new PC
300    Addr HandlerBase;
301    // Offset 0x180 - General Exception Vector
302    HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
303    setHandlerPC(HandlerBase,tc);
304}
305
306void
307AddressErrorFault::invoke(ThreadContext *tc)
308{
309    DPRINTF(MipsPRA, "%s encountered.\n", name());
310    setExceptionState(tc, 0x4);
311    tc->setMiscRegNoEffect(MipsISA::BadVAddr, BadVAddr);
312
313    // Set new PC
314    Addr HandlerBase;
315    // Offset 0x180 - General Exception Vector
316    HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
317    setHandlerPC(HandlerBase, tc);
318}
319
320void
321ItbInvalidFault::invoke(ThreadContext *tc)
322{
323    DPRINTF(MipsPRA, "%s encountered.\n", name());
324    setExceptionState(tc, 0x2);
325    tc->setMiscRegNoEffect(MipsISA::BadVAddr, BadVAddr);
326    MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
327    replaceBits(eh, EntryHi_ASID_HI, EntryHi_ASID_LO, EntryHi_Asid);
328    replaceBits(eh, EntryHi_VPN2_HI, EntryHi_VPN2_LO, EntryHi_VPN2);
329    replaceBits(eh, EntryHi_VPN2X_HI, EntryHi_VPN2X_LO, EntryHi_VPN2X);
330    tc->setMiscRegNoEffect(MipsISA::EntryHi, eh);
331    MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
332    replaceBits(ctxt, Context_BadVPN2_HI, Context_BadVPN2_LO, Context_BadVPN2);
333    tc->setMiscRegNoEffect(MipsISA::Context, ctxt);
334
335
336    // Set new PC
337    Addr HandlerBase;
338    // Offset 0x180 - General Exception Vector
339    HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase);
340    setHandlerPC(HandlerBase,tc);
341    DPRINTF(MipsPRA,"Exception Handler At: %x , EPC set to %x\n",
342            HandlerBase, tc->readMiscReg(MipsISA::EPC));
343}
344
345void
346ItbRefillFault::invoke(ThreadContext *tc)
347{
348    DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), BadVAddr);
349    Addr HandlerBase;
350    tc->setMiscRegNoEffect(MipsISA::BadVAddr, BadVAddr);
351    MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
352    replaceBits(eh, EntryHi_ASID_HI, EntryHi_ASID_LO, EntryHi_Asid);
353    replaceBits(eh, EntryHi_VPN2_HI, EntryHi_VPN2_LO, EntryHi_VPN2);
354    replaceBits(eh, EntryHi_VPN2X_HI, EntryHi_VPN2X_LO, EntryHi_VPN2X);
355    tc->setMiscRegNoEffect(MipsISA::EntryHi, eh);
356    MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
357    replaceBits(ctxt, Context_BadVPN2_HI, Context_BadVPN2_LO, Context_BadVPN2);
358    tc->setMiscRegNoEffect(MipsISA::Context, ctxt);
359
360    MiscReg stat = tc->readMiscReg(MipsISA::Status);
361    // Since handler depends on EXL bit, must check EXL bit before setting it!!
362    // See MIPS ARM Vol 3, Revision 2, Page 38
363    if (bits(stat, Status_EXL) == 1) {
364        // Offset 0x180 - General Exception Vector
365        HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
366    } else {
367        // Offset 0x000
368        HandlerBase = tc->readMiscReg(MipsISA::EBase);
369    }
370
371    setExceptionState(tc, 0x2);
372    setHandlerPC(HandlerBase, tc);
373}
374
375void
376DtbRefillFault::invoke(ThreadContext *tc)
377{
378    // Set new PC
379    DPRINTF(MipsPRA, "%s encountered.\n", name());
380    Addr HandlerBase;
381    tc->setMiscRegNoEffect(MipsISA::BadVAddr, BadVAddr);
382    MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
383    replaceBits(eh, EntryHi_ASID_HI, EntryHi_ASID_LO, EntryHi_Asid);
384    replaceBits(eh, EntryHi_VPN2_HI, EntryHi_VPN2_LO, EntryHi_VPN2);
385    replaceBits(eh, EntryHi_VPN2X_HI, EntryHi_VPN2X_LO, EntryHi_VPN2X);
386    tc->setMiscRegNoEffect(MipsISA::EntryHi, eh);
387    MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
388    replaceBits(ctxt, Context_BadVPN2_HI, Context_BadVPN2_LO, Context_BadVPN2);
389    tc->setMiscRegNoEffect(MipsISA::Context, ctxt);
390
391    MiscReg stat = tc->readMiscReg(MipsISA::Status);
392    // Since handler depends on EXL bit, must check EXL bit before setting it!!
393    // See MIPS ARM Vol 3, Revision 2, Page 38
394    if(bits(stat, Status_EXL) == 1) {
395        // Offset 0x180 - General Exception Vector
396        HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
397    } else {
398        // Offset 0x000
399        HandlerBase = tc->readMiscReg(MipsISA::EBase);
400    }
401
402    setExceptionState(tc, 0x3);
403
404    setHandlerPC(HandlerBase, tc);
405}
406
407void
408TLBModifiedFault::invoke(ThreadContext *tc)
409{
410    DPRINTF(MipsPRA, "%s encountered.\n", name());
411    tc->setMiscRegNoEffect(MipsISA::BadVAddr, BadVAddr);
412    MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
413    replaceBits(eh, EntryHi_ASID_HI, EntryHi_ASID_LO, EntryHi_Asid);
414    replaceBits(eh, EntryHi_VPN2_HI, EntryHi_VPN2_LO, EntryHi_VPN2);
415    replaceBits(eh, EntryHi_VPN2X_HI, EntryHi_VPN2X_LO, EntryHi_VPN2X);
416    tc->setMiscRegNoEffect(MipsISA::EntryHi, eh);
417    MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
418    replaceBits(ctxt, Context_BadVPN2_HI, Context_BadVPN2_LO, Context_BadVPN2);
419    tc->setMiscRegNoEffect(MipsISA::Context, ctxt);
420
421    // Set new PC
422    Addr HandlerBase;
423    // Offset 0x180 - General Exception Vector
424    HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
425    setExceptionState(tc, 0x1);
426    setHandlerPC(HandlerBase, tc);
427
428}
429
430void
431SystemCallFault::invoke(ThreadContext *tc)
432{
433    DPRINTF(MipsPRA, "%s encountered.\n", name());
434    setExceptionState(tc, 0x8);
435
436    // Set new PC
437    Addr HandlerBase;
438    // Offset 0x180 - General Exception Vector
439    HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
440    setHandlerPC(HandlerBase, tc);
441}
442
443void
444InterruptFault::invoke(ThreadContext *tc)
445{
446#if  FULL_SYSTEM
447    DPRINTF(MipsPRA, "%s encountered.\n", name());
448    setExceptionState(tc, 0x0A);
449    Addr HandlerBase;
450
451    uint8_t IV = bits(tc->readMiscRegNoEffect(MipsISA::Cause), Cause_IV);
452    if (IV) {
453        // Offset 200 for release 2
454        HandlerBase = 0x20 + vect() + tc->readMiscRegNoEffect(MipsISA::EBase);
455    } else {
456        //Ofset at 180 for release 1
457        HandlerBase = vect() + tc->readMiscRegNoEffect(MipsISA::EBase);
458    }
459
460    setHandlerPC(HandlerBase, tc);
461#endif
462}
463
464#endif // FULL_SYSTEM
465
466void
467ResetFault::invoke(ThreadContext *tc)
468{
469#if FULL_SYSTEM
470    DPRINTF(MipsPRA, "%s encountered.\n", name());
471    /* All reset activity must be invoked from here */
472    tc->setPC(vect());
473    tc->setNextPC(vect() + sizeof(MachInst));
474    tc->setNextNPC(vect() + sizeof(MachInst) + sizeof(MachInst));
475    DPRINTF(MipsPRA, "(%x)  -  ResetFault::invoke : PC set to %x",
476            (unsigned)tc, (unsigned)tc->readPC());
477#endif
478
479    // Set Coprocessor 1 (Floating Point) To Usable
480    tc->setMiscReg(MipsISA::Status, MipsISA::Status | 0x20000000);
481}
482
483void
484ReservedInstructionFault::invoke(ThreadContext *tc)
485{
486#if  FULL_SYSTEM
487    DPRINTF(MipsPRA, "%s encountered.\n", name());
488    setExceptionState(tc, 0x0A);
489    Addr HandlerBase;
490    // Offset 0x180 - General Exception Vector
491    HandlerBase = vect() + tc->readMiscRegNoEffect(MipsISA::EBase);
492    setHandlerPC(HandlerBase, tc);
493#else
494    panic("%s encountered.\n", name());
495#endif
496}
497
498void
499ThreadFault::invoke(ThreadContext *tc)
500{
501    DPRINTF(MipsPRA, "%s encountered.\n", name());
502    panic("%s encountered.\n", name());
503}
504
505void
506DspStateDisabledFault::invoke(ThreadContext *tc)
507{
508    DPRINTF(MipsPRA, "%s encountered.\n", name());
509    panic("%s encountered.\n", name());
510}
511
512void
513CoprocessorUnusableFault::invoke(ThreadContext *tc)
514{
515#if FULL_SYSTEM
516    DPRINTF(MipsPRA, "%s encountered.\n", name());
517    setExceptionState(tc, 0xb);
518    // The ID of the coprocessor causing the exception is stored in
519    // CoprocessorUnusableFault::coProcID
520    MiscReg cause = tc->readMiscReg(MipsISA::Cause);
521    replaceBits(cause, Cause_CE_HI, Cause_CE_LO, coProcID);
522    tc->setMiscRegNoEffect(MipsISA::Cause, cause);
523
524    Addr HandlerBase;
525    // Offset 0x180 - General Exception Vector
526    HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
527    setHandlerPC(HandlerBase, tc);
528
529#else
530    warn("%s (CP%d) encountered.\n", name(), coProcID);
531#endif
532}
533
534} // namespace MipsISA
535
536