faults.cc revision 8574
12131SN/A/* 25268Sksewell@umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 35254Sksewell@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc. 45254Sksewell@umich.edu * All rights reserved. 52131SN/A * 65254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 75254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 85254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 95254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 105254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 115254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 125254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 135254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 145254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 155254Sksewell@umich.edu * this software without specific prior written permission. 162131SN/A * 175254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245254Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255254Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265254Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275254Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 295254Sksewell@umich.edu * Authors: Gabe Black 305254Sksewell@umich.edu * Korey Sewell 315222Sksewell@umich.edu * Jaidev Patwardhan 322131SN/A */ 332131SN/A 342239SN/A#include "arch/mips/faults.hh" 357676Snate@binkert.org#include "arch/mips/pra_constants.hh" 367676Snate@binkert.org#include "base/trace.hh" 377676Snate@binkert.org#include "cpu/base.hh" 382680Sktlim@umich.edu#include "cpu/thread_context.hh" 398232Snate@binkert.org#include "debug/MipsPRA.hh" 407676Snate@binkert.org 412800Ssaidi@eecs.umich.edu#if !FULL_SYSTEM 427676Snate@binkert.org#include "mem/page_table.hh" 432800Ssaidi@eecs.umich.edu#include "sim/process.hh" 442800Ssaidi@eecs.umich.edu#endif 452131SN/A 462447SN/Anamespace MipsISA 472447SN/A{ 482131SN/A 498566Sgblack@eecs.umich.edutypedef MipsFaultBase::FaultVals FaultVals; 502131SN/A 518566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<MachineCheckFault>::vals = 528566Sgblack@eecs.umich.edu { "Machine Check", 0x0401 }; 532447SN/A 548566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<ResetFault>::vals = 555222Sksewell@umich.edu#if FULL_SYSTEM 568566Sgblack@eecs.umich.edu { "Reset Fault", 0xBFC00000}; 575222Sksewell@umich.edu#else 588566Sgblack@eecs.umich.edu { "Reset Fault", 0x001}; 595222Sksewell@umich.edu#endif 602447SN/A 618566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<AddressErrorFault>::vals = 628566Sgblack@eecs.umich.edu { "Address Error", 0x0180 }; 635222Sksewell@umich.edu 648566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<SystemCallFault>::vals = 658566Sgblack@eecs.umich.edu { "Syscall", 0x0180 }; 665222Sksewell@umich.edu 678566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<CoprocessorUnusableFault>::vals = 688566Sgblack@eecs.umich.edu { "Coprocessor Unusable Fault", 0x180 }; 695222Sksewell@umich.edu 708566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<ReservedInstructionFault>::vals = 718566Sgblack@eecs.umich.edu { "Reserved Instruction Fault", 0x0180 }; 724661Sksewell@umich.edu 738566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<ThreadFault>::vals = 748566Sgblack@eecs.umich.edu { "Thread Fault", 0x00F1 }; 754661Sksewell@umich.edu 768568Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<IntegerOverflowFault>::vals = 778568Sgblack@eecs.umich.edu { "Integer Overflow Exception", 0x180 }; 782447SN/A 798566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<InterruptFault>::vals = 808566Sgblack@eecs.umich.edu { "interrupt", 0x0180 }; 814661Sksewell@umich.edu 828566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<TrapFault>::vals = 838566Sgblack@eecs.umich.edu { "Trap", 0x0180 }; 842447SN/A 858566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<BreakpointFault>::vals = 868566Sgblack@eecs.umich.edu { "Breakpoint", 0x0180 }; 875222Sksewell@umich.edu 888573Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<TlbInvalidFault>::vals = 898573Sgblack@eecs.umich.edu { "Invalid TLB Entry Exception", 0x0180 }; 905222Sksewell@umich.edu 918573Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<TlbRefillFault>::vals = 928573Sgblack@eecs.umich.edu { "TLB Refill Exception", 0x0180 }; 932447SN/A 948566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<TLBModifiedFault>::vals = 958566Sgblack@eecs.umich.edu { "TLB Modified Exception", 0x0180 }; 962447SN/A 978566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<DspStateDisabledFault>::vals = 988566Sgblack@eecs.umich.edu { "DSP Disabled Fault", 0x001a }; 994661Sksewell@umich.edu 1006378Sgblack@eecs.umich.eduvoid 1018566Sgblack@eecs.umich.eduMipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode) 1025222Sksewell@umich.edu{ 1036378Sgblack@eecs.umich.edu // modify SRS Ctl - Save CSS, put ESS into CSS 1046383Sgblack@eecs.umich.edu StatusReg status = tc->readMiscReg(MISCREG_STATUS); 1056379Sgblack@eecs.umich.edu if (status.exl != 1 && status.bev != 1) { 1066378Sgblack@eecs.umich.edu // SRS Ctl is modified only if Status_EXL and Status_BEV are not set 1076383Sgblack@eecs.umich.edu SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL); 1086379Sgblack@eecs.umich.edu srsCtl.pss = srsCtl.css; 1096379Sgblack@eecs.umich.edu srsCtl.css = srsCtl.ess; 1106383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_SRSCTL, srsCtl); 1115222Sksewell@umich.edu } 1125222Sksewell@umich.edu 1136378Sgblack@eecs.umich.edu // set EXL bit (don't care if it is already set!) 1146379Sgblack@eecs.umich.edu status.exl = 1; 1156383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_STATUS, status); 1165222Sksewell@umich.edu 1176378Sgblack@eecs.umich.edu // write EPC 1188574Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 1198574Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "PC: %s\n", pc); 1208574Sgblack@eecs.umich.edu bool delay_slot = pc.pc() + sizeof(MachInst) != pc.npc(); 1218574Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_EPC, 1228574Sgblack@eecs.umich.edu pc.pc() - delay_slot ? sizeof(MachInst) : 0); 1235222Sksewell@umich.edu 1246378Sgblack@eecs.umich.edu // Set Cause_EXCCODE field 1256383Sgblack@eecs.umich.edu CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); 1266379Sgblack@eecs.umich.edu cause.excCode = excCode; 1278574Sgblack@eecs.umich.edu cause.bd = delay_slot ? 1 : 0; 1286379Sgblack@eecs.umich.edu cause.ce = 0; 1296383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CAUSE, cause); 1306378Sgblack@eecs.umich.edu} 1316378Sgblack@eecs.umich.edu 1328574Sgblack@eecs.umich.edu#if FULL_SYSTEM 1338574Sgblack@eecs.umich.eduvoid 1348574Sgblack@eecs.umich.eduMipsFaultBase::setHandlerPC(Addr HandlerBase, ThreadContext *tc) 1358574Sgblack@eecs.umich.edu{ 1368574Sgblack@eecs.umich.edu tc->setPC(HandlerBase); 1378574Sgblack@eecs.umich.edu tc->setNextPC(HandlerBase + sizeof(MachInst)); 1388574Sgblack@eecs.umich.edu tc->setNextNPC(HandlerBase + 2 * sizeof(MachInst)); 1398574Sgblack@eecs.umich.edu} 1408574Sgblack@eecs.umich.edu 1416378Sgblack@eecs.umich.eduvoid 1428568Sgblack@eecs.umich.eduIntegerOverflowFault::invoke(ThreadContext *tc, StaticInstPtr inst) 1436378Sgblack@eecs.umich.edu{ 1446378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 1456378Sgblack@eecs.umich.edu setExceptionState(tc, 0xC); 1466378Sgblack@eecs.umich.edu 1476378Sgblack@eecs.umich.edu // Set new PC 1486378Sgblack@eecs.umich.edu Addr HandlerBase; 1496383Sgblack@eecs.umich.edu StatusReg status = tc->readMiscReg(MISCREG_STATUS); 1506378Sgblack@eecs.umich.edu // Here, the handler is dependent on BEV, which is not modified by 1516378Sgblack@eecs.umich.edu // setExceptionState() 1526379Sgblack@eecs.umich.edu if (!status.bev) { 1536378Sgblack@eecs.umich.edu // See MIPS ARM Vol 3, Revision 2, Page 38 1546383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 1556378Sgblack@eecs.umich.edu } else { 1566378Sgblack@eecs.umich.edu HandlerBase = 0xBFC00200; 1576378Sgblack@eecs.umich.edu } 1586378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 1596378Sgblack@eecs.umich.edu} 1606378Sgblack@eecs.umich.edu 1616378Sgblack@eecs.umich.eduvoid 1627678Sgblack@eecs.umich.eduTrapFault::invoke(ThreadContext *tc, StaticInstPtr inst) 1636378Sgblack@eecs.umich.edu{ 1646378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 1656378Sgblack@eecs.umich.edu setExceptionState(tc, 0xD); 1666378Sgblack@eecs.umich.edu 1676378Sgblack@eecs.umich.edu // Set new PC 1686378Sgblack@eecs.umich.edu Addr HandlerBase; 1696378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 1706383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 1716378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 1726378Sgblack@eecs.umich.edu} 1736378Sgblack@eecs.umich.edu 1746378Sgblack@eecs.umich.eduvoid 1757678Sgblack@eecs.umich.eduBreakpointFault::invoke(ThreadContext *tc, StaticInstPtr inst) 1766378Sgblack@eecs.umich.edu{ 1776378Sgblack@eecs.umich.edu setExceptionState(tc, 0x9); 1786378Sgblack@eecs.umich.edu 1796378Sgblack@eecs.umich.edu // Set new PC 1806378Sgblack@eecs.umich.edu Addr HandlerBase; 1816378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 1826383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 1836378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 1846378Sgblack@eecs.umich.edu} 1856378Sgblack@eecs.umich.edu 1866378Sgblack@eecs.umich.eduvoid 1878573Sgblack@eecs.umich.eduTlbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst) 1886378Sgblack@eecs.umich.edu{ 1896378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 1908573Sgblack@eecs.umich.edu setExceptionState(tc, store ? 0x3 : 0x2); 1916378Sgblack@eecs.umich.edu 1926383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); 1936383Sgblack@eecs.umich.edu EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); 1946379Sgblack@eecs.umich.edu entryHi.asid = entryHiAsid; 1956379Sgblack@eecs.umich.edu entryHi.vpn2 = entryHiVPN2; 1966379Sgblack@eecs.umich.edu entryHi.vpn2x = entryHiVPN2X; 1976383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi); 1986379Sgblack@eecs.umich.edu 1996383Sgblack@eecs.umich.edu ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); 2006379Sgblack@eecs.umich.edu context.badVPN2 = contextBadVPN2; 2016383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CONTEXT, context); 2026378Sgblack@eecs.umich.edu 2036378Sgblack@eecs.umich.edu // Set new PC 2046378Sgblack@eecs.umich.edu Addr HandlerBase; 2056378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 2066383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 2076379Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 2086378Sgblack@eecs.umich.edu} 2096378Sgblack@eecs.umich.edu 2106378Sgblack@eecs.umich.eduvoid 2117678Sgblack@eecs.umich.eduAddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst) 2126378Sgblack@eecs.umich.edu{ 2136378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 2148570Sgblack@eecs.umich.edu setExceptionState(tc, store ? 0x5 : 0x4); 2158570Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr); 2166378Sgblack@eecs.umich.edu 2176378Sgblack@eecs.umich.edu // Set new PC 2186378Sgblack@eecs.umich.edu Addr HandlerBase; 2196378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 2206383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 2216378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 2226378Sgblack@eecs.umich.edu} 2236378Sgblack@eecs.umich.edu 2246378Sgblack@eecs.umich.eduvoid 2258573Sgblack@eecs.umich.eduTlbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst) 2266378Sgblack@eecs.umich.edu{ 2276383Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), MISCREG_BADVADDR); 2288573Sgblack@eecs.umich.edu setExceptionState(tc, store ? 0x3 : 0x2); 2298573Sgblack@eecs.umich.edu 2306378Sgblack@eecs.umich.edu Addr HandlerBase; 2316383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); 2326383Sgblack@eecs.umich.edu EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); 2336379Sgblack@eecs.umich.edu entryHi.asid = entryHiAsid; 2346379Sgblack@eecs.umich.edu entryHi.vpn2 = entryHiVPN2; 2356379Sgblack@eecs.umich.edu entryHi.vpn2x = entryHiVPN2X; 2366383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi); 2376383Sgblack@eecs.umich.edu ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); 2386379Sgblack@eecs.umich.edu context.badVPN2 = contextBadVPN2; 2396383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CONTEXT, context); 2406378Sgblack@eecs.umich.edu 2416383Sgblack@eecs.umich.edu StatusReg status = tc->readMiscReg(MISCREG_STATUS); 2426378Sgblack@eecs.umich.edu // Since handler depends on EXL bit, must check EXL bit before setting it!! 2436378Sgblack@eecs.umich.edu // See MIPS ARM Vol 3, Revision 2, Page 38 2446379Sgblack@eecs.umich.edu if (status.exl == 1) { 2456378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 2466383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 2476378Sgblack@eecs.umich.edu } else { 2486378Sgblack@eecs.umich.edu // Offset 0x000 2496383Sgblack@eecs.umich.edu HandlerBase = tc->readMiscReg(MISCREG_EBASE); 2506378Sgblack@eecs.umich.edu } 2516378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 2526378Sgblack@eecs.umich.edu} 2536378Sgblack@eecs.umich.edu 2546378Sgblack@eecs.umich.eduvoid 2557678Sgblack@eecs.umich.eduTLBModifiedFault::invoke(ThreadContext *tc, StaticInstPtr inst) 2566378Sgblack@eecs.umich.edu{ 2576378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 2586383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); 2596383Sgblack@eecs.umich.edu EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); 2606379Sgblack@eecs.umich.edu entryHi.asid = entryHiAsid; 2616379Sgblack@eecs.umich.edu entryHi.vpn2 = entryHiVPN2; 2626379Sgblack@eecs.umich.edu entryHi.vpn2x = entryHiVPN2X; 2636383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi); 2646379Sgblack@eecs.umich.edu 2656383Sgblack@eecs.umich.edu ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); 2666379Sgblack@eecs.umich.edu context.badVPN2 = contextBadVPN2; 2676383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CONTEXT, context); 2686378Sgblack@eecs.umich.edu 2696378Sgblack@eecs.umich.edu // Set new PC 2706378Sgblack@eecs.umich.edu Addr HandlerBase; 2716378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 2726383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 2736378Sgblack@eecs.umich.edu setExceptionState(tc, 0x1); 2746378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 2755222Sksewell@umich.edu 2765222Sksewell@umich.edu} 2775222Sksewell@umich.edu 2786378Sgblack@eecs.umich.eduvoid 2797678Sgblack@eecs.umich.eduSystemCallFault::invoke(ThreadContext *tc, StaticInstPtr inst) 2805222Sksewell@umich.edu{ 2816378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 2826378Sgblack@eecs.umich.edu setExceptionState(tc, 0x8); 2835222Sksewell@umich.edu 2846378Sgblack@eecs.umich.edu // Set new PC 2856378Sgblack@eecs.umich.edu Addr HandlerBase; 2866378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 2876383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 2886378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 2895222Sksewell@umich.edu} 2905222Sksewell@umich.edu 2916378Sgblack@eecs.umich.eduvoid 2927678Sgblack@eecs.umich.eduInterruptFault::invoke(ThreadContext *tc, StaticInstPtr inst) 2935222Sksewell@umich.edu{ 2945222Sksewell@umich.edu#if FULL_SYSTEM 2956378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 2966378Sgblack@eecs.umich.edu setExceptionState(tc, 0x0A); 2976378Sgblack@eecs.umich.edu Addr HandlerBase; 2985222Sksewell@umich.edu 2996383Sgblack@eecs.umich.edu CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); 3006379Sgblack@eecs.umich.edu if (cause.iv) { 3016378Sgblack@eecs.umich.edu // Offset 200 for release 2 3026383Sgblack@eecs.umich.edu HandlerBase = 0x20 + vect() + tc->readMiscRegNoEffect(MISCREG_EBASE); 3036378Sgblack@eecs.umich.edu } else { 3046378Sgblack@eecs.umich.edu //Ofset at 180 for release 1 3056383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscRegNoEffect(MISCREG_EBASE); 3066378Sgblack@eecs.umich.edu } 3075222Sksewell@umich.edu 3086378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 3095222Sksewell@umich.edu#endif 3105222Sksewell@umich.edu} 3115222Sksewell@umich.edu 3125222Sksewell@umich.edu#endif // FULL_SYSTEM 3135222Sksewell@umich.edu 3146378Sgblack@eecs.umich.eduvoid 3157678Sgblack@eecs.umich.eduResetFault::invoke(ThreadContext *tc, StaticInstPtr inst) 3164661Sksewell@umich.edu{ 3175224Sksewell@umich.edu#if FULL_SYSTEM 3186378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 3196378Sgblack@eecs.umich.edu /* All reset activity must be invoked from here */ 3206378Sgblack@eecs.umich.edu tc->setPC(vect()); 3216378Sgblack@eecs.umich.edu tc->setNextPC(vect() + sizeof(MachInst)); 3226378Sgblack@eecs.umich.edu tc->setNextNPC(vect() + sizeof(MachInst) + sizeof(MachInst)); 3236379Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", tc->readPC()); 3245224Sksewell@umich.edu#endif 3255224Sksewell@umich.edu 3266378Sgblack@eecs.umich.edu // Set Coprocessor 1 (Floating Point) To Usable 3276383Sgblack@eecs.umich.edu StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS); 3286379Sgblack@eecs.umich.edu status.cu.cu1 = 1; 3296383Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_STATUS, status); 3305222Sksewell@umich.edu} 3315222Sksewell@umich.edu 3326378Sgblack@eecs.umich.eduvoid 3337678Sgblack@eecs.umich.eduReservedInstructionFault::invoke(ThreadContext *tc, StaticInstPtr inst) 3345222Sksewell@umich.edu{ 3355222Sksewell@umich.edu#if FULL_SYSTEM 3366378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 3376378Sgblack@eecs.umich.edu setExceptionState(tc, 0x0A); 3386378Sgblack@eecs.umich.edu Addr HandlerBase; 3396378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 3406383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscRegNoEffect(MISCREG_EBASE); 3416378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 3425222Sksewell@umich.edu#else 3435222Sksewell@umich.edu panic("%s encountered.\n", name()); 3445222Sksewell@umich.edu#endif 3455222Sksewell@umich.edu} 3465222Sksewell@umich.edu 3476378Sgblack@eecs.umich.eduvoid 3487678Sgblack@eecs.umich.eduThreadFault::invoke(ThreadContext *tc, StaticInstPtr inst) 3495222Sksewell@umich.edu{ 3506378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 3516378Sgblack@eecs.umich.edu panic("%s encountered.\n", name()); 3525222Sksewell@umich.edu} 3535222Sksewell@umich.edu 3546378Sgblack@eecs.umich.eduvoid 3557678Sgblack@eecs.umich.eduDspStateDisabledFault::invoke(ThreadContext *tc, StaticInstPtr inst) 3565222Sksewell@umich.edu{ 3576378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 3586378Sgblack@eecs.umich.edu panic("%s encountered.\n", name()); 3594661Sksewell@umich.edu} 3604661Sksewell@umich.edu 3616378Sgblack@eecs.umich.eduvoid 3627678Sgblack@eecs.umich.eduCoprocessorUnusableFault::invoke(ThreadContext *tc, StaticInstPtr inst) 3634661Sksewell@umich.edu{ 3645222Sksewell@umich.edu#if FULL_SYSTEM 3656378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 3666378Sgblack@eecs.umich.edu setExceptionState(tc, 0xb); 3676378Sgblack@eecs.umich.edu // The ID of the coprocessor causing the exception is stored in 3686378Sgblack@eecs.umich.edu // CoprocessorUnusableFault::coProcID 3696383Sgblack@eecs.umich.edu CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); 3706379Sgblack@eecs.umich.edu cause.ce = coProcID; 3716383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CAUSE, cause); 3724661Sksewell@umich.edu 3736378Sgblack@eecs.umich.edu Addr HandlerBase; 3746378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 3756383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 3766378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 3774661Sksewell@umich.edu 3785222Sksewell@umich.edu#else 3795224Sksewell@umich.edu warn("%s (CP%d) encountered.\n", name(), coProcID); 3805222Sksewell@umich.edu#endif 3814661Sksewell@umich.edu} 3824661Sksewell@umich.edu 3832447SN/A} // namespace MipsISA 3842447SN/A 385