tlb.hh revision 13892:0182a0601f66
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Gabe Black 41 */ 42 43#ifndef __ARCH_GENERIC_TLB_HH__ 44#define __ARCH_GENERIC_TLB_HH__ 45 46#include "base/logging.hh" 47#include "mem/request.hh" 48#include "sim/sim_object.hh" 49 50class ThreadContext; 51class BaseMasterPort; 52 53class BaseTLB : public SimObject 54{ 55 protected: 56 BaseTLB(const Params *p) : SimObject(p) {} 57 58 public: 59 60 enum Mode { Read, Write, Execute }; 61 62 class Translation 63 { 64 public: 65 virtual ~Translation() 66 {} 67 68 /** 69 * Signal that the translation has been delayed due to a hw page table 70 * walk. 71 */ 72 virtual void markDelayed() = 0; 73 74 /* 75 * The memory for this object may be dynamically allocated, and it may 76 * be responsible for cleaning itself up which will happen in this 77 * function. Once it's called, the object is no longer valid. 78 */ 79 virtual void finish(const Fault &fault, const RequestPtr &req, 80 ThreadContext *tc, Mode mode) = 0; 81 82 /** This function is used by the page table walker to determine if it 83 * should translate the a pending request or if the underlying request 84 * has been squashed. 85 * @ return Is the instruction that requested this translation squashed? 86 */ 87 virtual bool squashed() const { return false; } 88 }; 89 90 public: 91 virtual void demapPage(Addr vaddr, uint64_t asn) = 0; 92 93 virtual Fault translateAtomic( 94 const RequestPtr &req, ThreadContext *tc, Mode mode) = 0; 95 virtual void translateTiming( 96 const RequestPtr &req, ThreadContext *tc, 97 Translation *translation, Mode mode) = 0; 98 virtual Fault 99 translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode) 100 { 101 panic("Not implemented.\n"); 102 } 103 104 /** 105 * Do post-translation physical address finalization. 106 * 107 * This method is used by some architectures that need 108 * post-translation massaging of physical addresses. For example, 109 * X86 uses this to remap physical addresses in the APIC range to 110 * a range of physical memory not normally available to real x86 111 * implementations. 112 * 113 * @param req Request to updated in-place. 114 * @param tc Thread context that created the request. 115 * @param mode Request type (read/write/execute). 116 * @return A fault on failure, NoFault otherwise. 117 */ 118 virtual Fault finalizePhysical( 119 const RequestPtr &req, ThreadContext *tc, Mode mode) const = 0; 120 121 /** 122 * Remove all entries from the TLB 123 */ 124 virtual void flushAll() = 0; 125 126 /** 127 * Take over from an old tlb context 128 */ 129 virtual void takeOverFrom(BaseTLB *otlb) = 0; 130 131 /** 132 * Get the table walker port if present. This is used for 133 * migrating port connections during a CPU takeOverFrom() 134 * call. For architectures that do not have a table walker, NULL 135 * is returned, hence the use of a pointer rather than a 136 * reference. 137 * 138 * @return A pointer to the walker port or NULL if not present 139 */ 140 virtual Port* getTableWalkerPort() { return NULL; } 141 142 void memInvalidate() { flushAll(); } 143}; 144 145class GenericTLB : public BaseTLB 146{ 147 protected: 148 GenericTLB(const Params *p) 149 : BaseTLB(p) 150 {} 151 152 public: 153 void demapPage(Addr vaddr, uint64_t asn) override; 154 155 Fault translateAtomic( 156 const RequestPtr &req, ThreadContext *tc, Mode mode) override; 157 void translateTiming( 158 const RequestPtr &req, ThreadContext *tc, 159 Translation *translation, Mode mode) override; 160 161 Fault finalizePhysical( 162 const RequestPtr &req, ThreadContext *tc, Mode mode) const override; 163}; 164 165#endif // __ARCH_GENERIC_TLB_HH__ 166