tlb.hh revision 13741
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Gabe Black 41 */ 42 43#ifndef __ARCH_GENERIC_TLB_HH__ 44#define __ARCH_GENERIC_TLB_HH__ 45 46#include "base/logging.hh" 47#include "mem/mem_object.hh" 48#include "mem/request.hh" 49 50class ThreadContext; 51class BaseMasterPort; 52 53class BaseTLB : public MemObject 54{ 55 protected: 56 BaseTLB(const Params *p) 57 : MemObject(p) 58 {} 59 60 public: 61 62 enum Mode { Read, Write, Execute }; 63 64 class Translation 65 { 66 public: 67 virtual ~Translation() 68 {} 69 70 /** 71 * Signal that the translation has been delayed due to a hw page table 72 * walk. 73 */ 74 virtual void markDelayed() = 0; 75 76 /* 77 * The memory for this object may be dynamically allocated, and it may 78 * be responsible for cleaning itself up which will happen in this 79 * function. Once it's called, the object is no longer valid. 80 */ 81 virtual void finish(const Fault &fault, const RequestPtr &req, 82 ThreadContext *tc, Mode mode) = 0; 83 84 /** This function is used by the page table walker to determine if it 85 * should translate the a pending request or if the underlying request 86 * has been squashed. 87 * @ return Is the instruction that requested this translation squashed? 88 */ 89 virtual bool squashed() const { return false; } 90 }; 91 92 public: 93 virtual void demapPage(Addr vaddr, uint64_t asn) = 0; 94 95 virtual Fault translateAtomic( 96 const RequestPtr &req, ThreadContext *tc, Mode mode) = 0; 97 virtual void translateTiming( 98 const RequestPtr &req, ThreadContext *tc, 99 Translation *translation, Mode mode) = 0; 100 virtual Fault 101 translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode) 102 { 103 panic("Not implemented.\n"); 104 } 105 106 /** 107 * Do post-translation physical address finalization. 108 * 109 * This method is used by some architectures that need 110 * post-translation massaging of physical addresses. For example, 111 * X86 uses this to remap physical addresses in the APIC range to 112 * a range of physical memory not normally available to real x86 113 * implementations. 114 * 115 * @param req Request to updated in-place. 116 * @param tc Thread context that created the request. 117 * @param mode Request type (read/write/execute). 118 * @return A fault on failure, NoFault otherwise. 119 */ 120 virtual Fault finalizePhysical( 121 const RequestPtr &req, ThreadContext *tc, Mode mode) const = 0; 122 123 /** 124 * Remove all entries from the TLB 125 */ 126 virtual void flushAll() = 0; 127 128 /** 129 * Take over from an old tlb context 130 */ 131 virtual void takeOverFrom(BaseTLB *otlb) = 0; 132 133 /** 134 * Get the table walker master port if present. This is used for 135 * migrating port connections during a CPU takeOverFrom() 136 * call. For architectures that do not have a table walker, NULL 137 * is returned, hence the use of a pointer rather than a 138 * reference. 139 * 140 * @return A pointer to the walker master port or NULL if not present 141 */ 142 virtual BaseMasterPort* getTableWalkerMasterPort() { return NULL; } 143 144 void memInvalidate() { flushAll(); } 145}; 146 147class GenericTLB : public BaseTLB 148{ 149 protected: 150 GenericTLB(const Params *p) 151 : BaseTLB(p) 152 {} 153 154 public: 155 void demapPage(Addr vaddr, uint64_t asn) override; 156 157 Fault translateAtomic( 158 const RequestPtr &req, ThreadContext *tc, Mode mode) override; 159 void translateTiming( 160 const RequestPtr &req, ThreadContext *tc, 161 Translation *translation, Mode mode) override; 162 163 Fault finalizePhysical( 164 const RequestPtr &req, ThreadContext *tc, Mode mode) const override; 165}; 166 167#endif // __ARCH_GENERIC_TLB_HH__ 168