tlb.hh revision 10687
14997SN/A/* 27944SN/A * Copyright (c) 2011 ARM Limited 37944SN/A * All rights reserved. 47944SN/A * 57944SN/A * The license below extends only to copyright in the software and shall 67944SN/A * not be construed as granting a license to any other intellectual 77944SN/A * property including but not limited to intellectual property relating 87944SN/A * to a hardware implementation of the functionality of the software 97944SN/A * licensed hereunder. You may use the software subject to the license 107944SN/A * terms below provided that you ensure that this notice is replicated 117944SN/A * unmodified and in its entirety in all distributions of the software, 127944SN/A * modified or unmodified, in source code or in binary form. 137944SN/A * 144997SN/A * Copyright (c) 2006 The Regents of The University of Michigan 154997SN/A * All rights reserved. 164997SN/A * 174997SN/A * Redistribution and use in source and binary forms, with or without 184997SN/A * modification, are permitted provided that the following conditions are 194997SN/A * met: redistributions of source code must retain the above copyright 204997SN/A * notice, this list of conditions and the following disclaimer; 214997SN/A * redistributions in binary form must reproduce the above copyright 224997SN/A * notice, this list of conditions and the following disclaimer in the 234997SN/A * documentation and/or other materials provided with the distribution; 244997SN/A * neither the name of the copyright holders nor the names of its 254997SN/A * contributors may be used to endorse or promote products derived from 264997SN/A * this software without specific prior written permission. 274997SN/A * 284997SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294997SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 304997SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 314997SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 324997SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334997SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344997SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354997SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 364997SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374997SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 384997SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394997SN/A * 404997SN/A * Authors: Gabe Black 414997SN/A */ 424997SN/A 4310687SAndreas.Sandberg@ARM.com#ifndef __ARCH_GENERIC_TLB_HH__ 4410687SAndreas.Sandberg@ARM.com#define __ARCH_GENERIC_TLB_HH__ 454997SN/A 465004SN/A#include "base/misc.hh" 474997SN/A#include "mem/request.hh" 484997SN/A#include "sim/sim_object.hh" 494997SN/A 504997SN/Aclass ThreadContext; 519294SN/Aclass BaseMasterPort; 524997SN/A 535358SN/Aclass BaseTLB : public SimObject 545004SN/A{ 555004SN/A protected: 566023SN/A BaseTLB(const Params *p) 576023SN/A : SimObject(p) 585004SN/A {} 595004SN/A 604997SN/A public: 616023SN/A enum Mode { Read, Write, Execute }; 626023SN/A 636023SN/A public: 645358SN/A virtual void demapPage(Addr vaddr, uint64_t asn) = 0; 655894SN/A 668922SN/A /** 679423SN/A * Remove all entries from the TLB 689423SN/A */ 699423SN/A virtual void flushAll() = 0; 709423SN/A 719423SN/A /** 7210194SN/A * Take over from an old tlb context 7310194SN/A */ 7410194SN/A virtual void takeOverFrom(BaseTLB *otlb) = 0; 7510194SN/A 7610194SN/A /** 778922SN/A * Get the table walker master port if present. This is used for 788922SN/A * migrating port connections during a CPU takeOverFrom() 798922SN/A * call. For architectures that do not have a table walker, NULL 808922SN/A * is returned, hence the use of a pointer rather than a 818922SN/A * reference. 828922SN/A * 838922SN/A * @return A pointer to the walker master port or NULL if not present 848922SN/A */ 859294SN/A virtual BaseMasterPort* getMasterPort() { return NULL; } 867781SN/A 879423SN/A void memInvalidate() { flushAll(); } 889423SN/A 895894SN/A class Translation 905894SN/A { 915894SN/A public: 925894SN/A virtual ~Translation() 935894SN/A {} 945894SN/A 957944SN/A /** 967944SN/A * Signal that the translation has been delayed due to a hw page table 977944SN/A * walk. 987944SN/A */ 997944SN/A virtual void markDelayed() = 0; 1007944SN/A 1015894SN/A /* 1025894SN/A * The memory for this object may be dynamically allocated, and it may 1035894SN/A * be responsible for cleaning itself up which will happen in this 1045894SN/A * function. Once it's called, the object is no longer valid. 1055894SN/A */ 10610379SN/A virtual void finish(const Fault &fault, RequestPtr req, 10710379SN/A ThreadContext *tc, Mode mode) = 0; 1089258SN/A 1099258SN/A /** This function is used by the page table walker to determine if it 1109258SN/A * should translate the a pending request or if the underlying request 1119258SN/A * has been squashed. 1129258SN/A * @ return Is the instruction that requested this translation squashed? 1139258SN/A */ 1149258SN/A virtual bool squashed() const { return false; } 1155894SN/A }; 1165358SN/A}; 1175358SN/A 1185358SN/Aclass GenericTLB : public BaseTLB 1195358SN/A{ 1205358SN/A protected: 1216023SN/A GenericTLB(const Params *p) 1226023SN/A : BaseTLB(p) 1235358SN/A {} 1245358SN/A 1255358SN/A public: 1265358SN/A void demapPage(Addr vaddr, uint64_t asn); 1275358SN/A 1286023SN/A Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); 1295894SN/A void translateTiming(RequestPtr req, ThreadContext *tc, 1306023SN/A Translation *translation, Mode mode); 1319738SN/A 1329738SN/A 1339738SN/A /** 1349738SN/A * Do post-translation physical address finalization. 1359738SN/A * 1369738SN/A * This method is used by some architectures that need 1379738SN/A * post-translation massaging of physical addresses. For example, 1389738SN/A * X86 uses this to remap physical addresses in the APIC range to 1399738SN/A * a range of physical memory not normally available to real x86 1409738SN/A * implementations. 1419738SN/A * 1429738SN/A * @param req Request to updated in-place. 1439738SN/A * @param tc Thread context that created the request. 1449738SN/A * @param mode Request type (read/write/execute). 1459738SN/A * @return A fault on failure, NoFault otherwise. 1469738SN/A */ 1479738SN/A Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const; 1484997SN/A}; 1494997SN/A 15010687SAndreas.Sandberg@ARM.com#endif // __ARCH_GENERIC_TLB_HH__ 151