tlb.hh revision 10379 
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#ifndef __SIM_TLB_HH__
44#define __SIM_TLB_HH__
45
46#include "base/misc.hh"
47#include "mem/request.hh"
48#include "sim/fault_fwd.hh"
49#include "sim/sim_object.hh"
50
51class ThreadContext;
52class BaseMasterPort;
53
54class BaseTLB : public SimObject
55{
56  protected:
57    BaseTLB(const Params *p)
58        : SimObject(p)
59    {}
60
61  public:
62    enum Mode { Read, Write, Execute };
63
64  public:
65    virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
66
67    /**
68     * Remove all entries from the TLB
69     */
70    virtual void flushAll() = 0;
71
72    /**
73     * Take over from an old tlb context
74     */
75    virtual void takeOverFrom(BaseTLB *otlb) = 0;
76
77    /**
78     * Get the table walker master port if present. This is used for
79     * migrating port connections during a CPU takeOverFrom()
80     * call. For architectures that do not have a table walker, NULL
81     * is returned, hence the use of a pointer rather than a
82     * reference.
83     *
84     * @return A pointer to the walker master port or NULL if not present
85     */
86    virtual BaseMasterPort* getMasterPort() { return NULL; }
87
88    void memInvalidate() { flushAll(); }
89
90    class Translation
91    {
92      public:
93        virtual ~Translation()
94        {}
95
96        /**
97         * Signal that the translation has been delayed due to a hw page table
98         * walk.
99         */
100        virtual void markDelayed() = 0;
101
102        /*
103         * The memory for this object may be dynamically allocated, and it may
104         * be responsible for cleaning itself up which will happen in this
105         * function. Once it's called, the object is no longer valid.
106         */
107        virtual void finish(const Fault &fault, RequestPtr req,
108                            ThreadContext *tc, Mode mode) = 0;
109
110        /** This function is used by the page table walker to determine if it
111         * should translate the a pending request or if the underlying request
112         * has been squashed.
113         * @ return Is the instruction that requested this translation squashed?
114         */
115        virtual bool squashed() const { return false; }
116    };
117};
118
119class GenericTLB : public BaseTLB
120{
121  protected:
122    GenericTLB(const Params *p)
123        : BaseTLB(p)
124    {}
125
126  public:
127    void demapPage(Addr vaddr, uint64_t asn);
128
129    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
130    void translateTiming(RequestPtr req, ThreadContext *tc,
131                         Translation *translation, Mode mode);
132
133
134    /**
135     * Do post-translation physical address finalization.
136     *
137     * This method is used by some architectures that need
138     * post-translation massaging of physical addresses. For example,
139     * X86 uses this to remap physical addresses in the APIC range to
140     * a range of physical memory not normally available to real x86
141     * implementations.
142     *
143     * @param req Request to updated in-place.
144     * @param tc Thread context that created the request.
145     * @param mode Request type (read/write/execute).
146     * @return A fault on failure, NoFault otherwise.
147     */
148    Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
149};
150
151#endif // __ARCH_SPARC_TLB_HH__
152